perf: Remove the nmi parameter from the swevent and overflow interface
[linux-2.6.git] / arch / sh / kernel / traps_32.c
1 /*
2  * 'traps.c' handles hardware traps and faults after we have saved some
3  * state in 'entry.S'.
4  *
5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
6  *                  Copyright (C) 2000 Philipp Rumpf
7  *                  Copyright (C) 2000 David Howells
8  *                  Copyright (C) 2002 - 2010 Paul Mundt
9  *
10  * This file is subject to the terms and conditions of the GNU General Public
11  * License.  See the file "COPYING" in the main directory of this archive
12  * for more details.
13  */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
21 #include <linux/io.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/sysfs.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <asm/system.h>
31 #include <asm/alignment.h>
32 #include <asm/fpu.h>
33 #include <asm/kprobes.h>
34
35 #ifdef CONFIG_CPU_SH2
36 # define TRAP_RESERVED_INST     4
37 # define TRAP_ILLEGAL_SLOT_INST 6
38 # define TRAP_ADDRESS_ERROR     9
39 # ifdef CONFIG_CPU_SH2A
40 #  define TRAP_UBC              12
41 #  define TRAP_FPU_ERROR        13
42 #  define TRAP_DIVZERO_ERROR    17
43 #  define TRAP_DIVOVF_ERROR     18
44 # endif
45 #else
46 #define TRAP_RESERVED_INST      12
47 #define TRAP_ILLEGAL_SLOT_INST  13
48 #endif
49
50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
51 {
52         unsigned long p;
53         int i;
54
55         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
56
57         for (p = bottom & ~31; p < top; ) {
58                 printk("%04lx: ", p & 0xffff);
59
60                 for (i = 0; i < 8; i++, p += 4) {
61                         unsigned int val;
62
63                         if (p < bottom || p >= top)
64                                 printk("         ");
65                         else {
66                                 if (__get_user(val, (unsigned int __user *)p)) {
67                                         printk("\n");
68                                         return;
69                                 }
70                                 printk("%08x ", val);
71                         }
72                 }
73                 printk("\n");
74         }
75 }
76
77 static DEFINE_SPINLOCK(die_lock);
78
79 void die(const char * str, struct pt_regs * regs, long err)
80 {
81         static int die_counter;
82
83         oops_enter();
84
85         spin_lock_irq(&die_lock);
86         console_verbose();
87         bust_spinlocks(1);
88
89         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
90         print_modules();
91         show_regs(regs);
92
93         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
94                         task_pid_nr(current), task_stack_page(current) + 1);
95
96         if (!user_mode(regs) || in_interrupt())
97                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
98                          (unsigned long)task_stack_page(current));
99
100         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
101
102         bust_spinlocks(0);
103         add_taint(TAINT_DIE);
104         spin_unlock_irq(&die_lock);
105         oops_exit();
106
107         if (kexec_should_crash(current))
108                 crash_kexec(regs);
109
110         if (in_interrupt())
111                 panic("Fatal exception in interrupt");
112
113         if (panic_on_oops)
114                 panic("Fatal exception");
115
116         do_exit(SIGSEGV);
117 }
118
119 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
120                                  long err)
121 {
122         if (!user_mode(regs))
123                 die(str, regs, err);
124 }
125
126 /*
127  * try and fix up kernelspace address errors
128  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
129  * - kernel/userspace interfaces cause a jump to an appropriate handler
130  * - other kernel errors are bad
131  */
132 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
133 {
134         if (!user_mode(regs)) {
135                 const struct exception_table_entry *fixup;
136                 fixup = search_exception_tables(regs->pc);
137                 if (fixup) {
138                         regs->pc = fixup->fixup;
139                         return;
140                 }
141
142                 die(str, regs, err);
143         }
144 }
145
146 static inline void sign_extend(unsigned int count, unsigned char *dst)
147 {
148 #ifdef __LITTLE_ENDIAN__
149         if ((count == 1) && dst[0] & 0x80) {
150                 dst[1] = 0xff;
151                 dst[2] = 0xff;
152                 dst[3] = 0xff;
153         }
154         if ((count == 2) && dst[1] & 0x80) {
155                 dst[2] = 0xff;
156                 dst[3] = 0xff;
157         }
158 #else
159         if ((count == 1) && dst[3] & 0x80) {
160                 dst[2] = 0xff;
161                 dst[1] = 0xff;
162                 dst[0] = 0xff;
163         }
164         if ((count == 2) && dst[2] & 0x80) {
165                 dst[1] = 0xff;
166                 dst[0] = 0xff;
167         }
168 #endif
169 }
170
171 static struct mem_access user_mem_access = {
172         copy_from_user,
173         copy_to_user,
174 };
175
176 /*
177  * handle an instruction that does an unaligned memory access by emulating the
178  * desired behaviour
179  * - note that PC _may not_ point to the faulting instruction
180  *   (if that instruction is in a branch delay slot)
181  * - return 0 if emulation okay, -EFAULT on existential error
182  */
183 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
184                                 struct mem_access *ma)
185 {
186         int ret, index, count;
187         unsigned long *rm, *rn;
188         unsigned char *src, *dst;
189         unsigned char __user *srcu, *dstu;
190
191         index = (instruction>>8)&15;    /* 0x0F00 */
192         rn = &regs->regs[index];
193
194         index = (instruction>>4)&15;    /* 0x00F0 */
195         rm = &regs->regs[index];
196
197         count = 1<<(instruction&3);
198
199         switch (count) {
200         case 1: inc_unaligned_byte_access(); break;
201         case 2: inc_unaligned_word_access(); break;
202         case 4: inc_unaligned_dword_access(); break;
203         case 8: inc_unaligned_multi_access(); break;
204         }
205
206         ret = -EFAULT;
207         switch (instruction>>12) {
208         case 0: /* mov.[bwl] to/from memory via r0+rn */
209                 if (instruction & 8) {
210                         /* from memory */
211                         srcu = (unsigned char __user *)*rm;
212                         srcu += regs->regs[0];
213                         dst = (unsigned char *)rn;
214                         *(unsigned long *)dst = 0;
215
216 #if !defined(__LITTLE_ENDIAN__)
217                         dst += 4-count;
218 #endif
219                         if (ma->from(dst, srcu, count))
220                                 goto fetch_fault;
221
222                         sign_extend(count, dst);
223                 } else {
224                         /* to memory */
225                         src = (unsigned char *)rm;
226 #if !defined(__LITTLE_ENDIAN__)
227                         src += 4-count;
228 #endif
229                         dstu = (unsigned char __user *)*rn;
230                         dstu += regs->regs[0];
231
232                         if (ma->to(dstu, src, count))
233                                 goto fetch_fault;
234                 }
235                 ret = 0;
236                 break;
237
238         case 1: /* mov.l Rm,@(disp,Rn) */
239                 src = (unsigned char*) rm;
240                 dstu = (unsigned char __user *)*rn;
241                 dstu += (instruction&0x000F)<<2;
242
243                 if (ma->to(dstu, src, 4))
244                         goto fetch_fault;
245                 ret = 0;
246                 break;
247
248         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
249                 if (instruction & 4)
250                         *rn -= count;
251                 src = (unsigned char*) rm;
252                 dstu = (unsigned char __user *)*rn;
253 #if !defined(__LITTLE_ENDIAN__)
254                 src += 4-count;
255 #endif
256                 if (ma->to(dstu, src, count))
257                         goto fetch_fault;
258                 ret = 0;
259                 break;
260
261         case 5: /* mov.l @(disp,Rm),Rn */
262                 srcu = (unsigned char __user *)*rm;
263                 srcu += (instruction & 0x000F) << 2;
264                 dst = (unsigned char *)rn;
265                 *(unsigned long *)dst = 0;
266
267                 if (ma->from(dst, srcu, 4))
268                         goto fetch_fault;
269                 ret = 0;
270                 break;
271
272         case 6: /* mov.[bwl] from memory, possibly with post-increment */
273                 srcu = (unsigned char __user *)*rm;
274                 if (instruction & 4)
275                         *rm += count;
276                 dst = (unsigned char*) rn;
277                 *(unsigned long*)dst = 0;
278
279 #if !defined(__LITTLE_ENDIAN__)
280                 dst += 4-count;
281 #endif
282                 if (ma->from(dst, srcu, count))
283                         goto fetch_fault;
284                 sign_extend(count, dst);
285                 ret = 0;
286                 break;
287
288         case 8:
289                 switch ((instruction&0xFF00)>>8) {
290                 case 0x81: /* mov.w R0,@(disp,Rn) */
291                         src = (unsigned char *) &regs->regs[0];
292 #if !defined(__LITTLE_ENDIAN__)
293                         src += 2;
294 #endif
295                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
296                         dstu += (instruction & 0x000F) << 1;
297
298                         if (ma->to(dstu, src, 2))
299                                 goto fetch_fault;
300                         ret = 0;
301                         break;
302
303                 case 0x85: /* mov.w @(disp,Rm),R0 */
304                         srcu = (unsigned char __user *)*rm;
305                         srcu += (instruction & 0x000F) << 1;
306                         dst = (unsigned char *) &regs->regs[0];
307                         *(unsigned long *)dst = 0;
308
309 #if !defined(__LITTLE_ENDIAN__)
310                         dst += 2;
311 #endif
312                         if (ma->from(dst, srcu, 2))
313                                 goto fetch_fault;
314                         sign_extend(2, dst);
315                         ret = 0;
316                         break;
317                 }
318                 break;
319         }
320         return ret;
321
322  fetch_fault:
323         /* Argh. Address not only misaligned but also non-existent.
324          * Raise an EFAULT and see if it's trapped
325          */
326         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
327         return -EFAULT;
328 }
329
330 /*
331  * emulate the instruction in the delay slot
332  * - fetches the instruction from PC+2
333  */
334 static inline int handle_delayslot(struct pt_regs *regs,
335                                    insn_size_t old_instruction,
336                                    struct mem_access *ma)
337 {
338         insn_size_t instruction;
339         void __user *addr = (void __user *)(regs->pc +
340                 instruction_size(old_instruction));
341
342         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
343                 /* the instruction-fetch faulted */
344                 if (user_mode(regs))
345                         return -EFAULT;
346
347                 /* kernel */
348                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
349                     regs, 0);
350         }
351
352         return handle_unaligned_ins(instruction, regs, ma);
353 }
354
355 /*
356  * handle an instruction that does an unaligned memory access
357  * - have to be careful of branch delay-slot instructions that fault
358  *  SH3:
359  *   - if the branch would be taken PC points to the branch
360  *   - if the branch would not be taken, PC points to delay-slot
361  *  SH4:
362  *   - PC always points to delayed branch
363  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
364  */
365
366 /* Macros to determine offset from current PC for branch instructions */
367 /* Explicit type coercion is used to force sign extension where needed */
368 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
369 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
370
371 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
372                             struct mem_access *ma, int expected,
373                             unsigned long address)
374 {
375         u_int rm;
376         int ret, index;
377
378         /*
379          * XXX: We can't handle mixed 16/32-bit instructions yet
380          */
381         if (instruction_size(instruction) != 2)
382                 return -EINVAL;
383
384         index = (instruction>>8)&15;    /* 0x0F00 */
385         rm = regs->regs[index];
386
387         /*
388          * Log the unexpected fixups, and then pass them on to perf.
389          *
390          * We intentionally don't report the expected cases to perf as
391          * otherwise the trapped I/O case will skew the results too much
392          * to be useful.
393          */
394         if (!expected) {
395                 unaligned_fixups_notify(current, instruction, regs);
396                 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
397                               regs, address);
398         }
399
400         ret = -EFAULT;
401         switch (instruction&0xF000) {
402         case 0x0000:
403                 if (instruction==0x000B) {
404                         /* rts */
405                         ret = handle_delayslot(regs, instruction, ma);
406                         if (ret==0)
407                                 regs->pc = regs->pr;
408                 }
409                 else if ((instruction&0x00FF)==0x0023) {
410                         /* braf @Rm */
411                         ret = handle_delayslot(regs, instruction, ma);
412                         if (ret==0)
413                                 regs->pc += rm + 4;
414                 }
415                 else if ((instruction&0x00FF)==0x0003) {
416                         /* bsrf @Rm */
417                         ret = handle_delayslot(regs, instruction, ma);
418                         if (ret==0) {
419                                 regs->pr = regs->pc + 4;
420                                 regs->pc += rm + 4;
421                         }
422                 }
423                 else {
424                         /* mov.[bwl] to/from memory via r0+rn */
425                         goto simple;
426                 }
427                 break;
428
429         case 0x1000: /* mov.l Rm,@(disp,Rn) */
430                 goto simple;
431
432         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
433                 goto simple;
434
435         case 0x4000:
436                 if ((instruction&0x00FF)==0x002B) {
437                         /* jmp @Rm */
438                         ret = handle_delayslot(regs, instruction, ma);
439                         if (ret==0)
440                                 regs->pc = rm;
441                 }
442                 else if ((instruction&0x00FF)==0x000B) {
443                         /* jsr @Rm */
444                         ret = handle_delayslot(regs, instruction, ma);
445                         if (ret==0) {
446                                 regs->pr = regs->pc + 4;
447                                 regs->pc = rm;
448                         }
449                 }
450                 else {
451                         /* mov.[bwl] to/from memory via r0+rn */
452                         goto simple;
453                 }
454                 break;
455
456         case 0x5000: /* mov.l @(disp,Rm),Rn */
457                 goto simple;
458
459         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
460                 goto simple;
461
462         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
463                 switch (instruction&0x0F00) {
464                 case 0x0100: /* mov.w R0,@(disp,Rm) */
465                         goto simple;
466                 case 0x0500: /* mov.w @(disp,Rm),R0 */
467                         goto simple;
468                 case 0x0B00: /* bf   lab - no delayslot*/
469                         break;
470                 case 0x0F00: /* bf/s lab */
471                         ret = handle_delayslot(regs, instruction, ma);
472                         if (ret==0) {
473 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
474                                 if ((regs->sr & 0x00000001) != 0)
475                                         regs->pc += 4; /* next after slot */
476                                 else
477 #endif
478                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
479                         }
480                         break;
481                 case 0x0900: /* bt   lab - no delayslot */
482                         break;
483                 case 0x0D00: /* bt/s lab */
484                         ret = handle_delayslot(regs, instruction, ma);
485                         if (ret==0) {
486 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
487                                 if ((regs->sr & 0x00000001) == 0)
488                                         regs->pc += 4; /* next after slot */
489                                 else
490 #endif
491                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
492                         }
493                         break;
494                 }
495                 break;
496
497         case 0xA000: /* bra label */
498                 ret = handle_delayslot(regs, instruction, ma);
499                 if (ret==0)
500                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
501                 break;
502
503         case 0xB000: /* bsr label */
504                 ret = handle_delayslot(regs, instruction, ma);
505                 if (ret==0) {
506                         regs->pr = regs->pc + 4;
507                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
508                 }
509                 break;
510         }
511         return ret;
512
513         /* handle non-delay-slot instruction */
514  simple:
515         ret = handle_unaligned_ins(instruction, regs, ma);
516         if (ret==0)
517                 regs->pc += instruction_size(instruction);
518         return ret;
519 }
520
521 /*
522  * Handle various address error exceptions:
523  *  - instruction address error:
524  *       misaligned PC
525  *       PC >= 0x80000000 in user mode
526  *  - data address error (read and write)
527  *       misaligned data access
528  *       access to >= 0x80000000 is user mode
529  * Unfortuntaly we can't distinguish between instruction address error
530  * and data address errors caused by read accesses.
531  */
532 asmlinkage void do_address_error(struct pt_regs *regs,
533                                  unsigned long writeaccess,
534                                  unsigned long address)
535 {
536         unsigned long error_code = 0;
537         mm_segment_t oldfs;
538         siginfo_t info;
539         insn_size_t instruction;
540         int tmp;
541
542         /* Intentional ifdef */
543 #ifdef CONFIG_CPU_HAS_SR_RB
544         error_code = lookup_exception_vector();
545 #endif
546
547         oldfs = get_fs();
548
549         if (user_mode(regs)) {
550                 int si_code = BUS_ADRERR;
551                 unsigned int user_action;
552
553                 local_irq_enable();
554                 inc_unaligned_user_access();
555
556                 set_fs(USER_DS);
557                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
558                                    sizeof(instruction))) {
559                         set_fs(oldfs);
560                         goto uspace_segv;
561                 }
562                 set_fs(oldfs);
563
564                 /* shout about userspace fixups */
565                 unaligned_fixups_notify(current, instruction, regs);
566
567                 user_action = unaligned_user_action();
568                 if (user_action & UM_FIXUP)
569                         goto fixup;
570                 if (user_action & UM_SIGNAL)
571                         goto uspace_segv;
572                 else {
573                         /* ignore */
574                         regs->pc += instruction_size(instruction);
575                         return;
576                 }
577
578 fixup:
579                 /* bad PC is not something we can fix */
580                 if (regs->pc & 1) {
581                         si_code = BUS_ADRALN;
582                         goto uspace_segv;
583                 }
584
585                 set_fs(USER_DS);
586                 tmp = handle_unaligned_access(instruction, regs,
587                                               &user_mem_access, 0,
588                                               address);
589                 set_fs(oldfs);
590
591                 if (tmp == 0)
592                         return; /* sorted */
593 uspace_segv:
594                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
595                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
596                        regs->pr);
597
598                 info.si_signo = SIGBUS;
599                 info.si_errno = 0;
600                 info.si_code = si_code;
601                 info.si_addr = (void __user *)address;
602                 force_sig_info(SIGBUS, &info, current);
603         } else {
604                 inc_unaligned_kernel_access();
605
606                 if (regs->pc & 1)
607                         die("unaligned program counter", regs, error_code);
608
609                 set_fs(KERNEL_DS);
610                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
611                                    sizeof(instruction))) {
612                         /* Argh. Fault on the instruction itself.
613                            This should never happen non-SMP
614                         */
615                         set_fs(oldfs);
616                         die("insn faulting in do_address_error", regs, 0);
617                 }
618
619                 unaligned_fixups_notify(current, instruction, regs);
620
621                 handle_unaligned_access(instruction, regs, &user_mem_access,
622                                         0, address);
623                 set_fs(oldfs);
624         }
625 }
626
627 #ifdef CONFIG_SH_DSP
628 /*
629  *      SH-DSP support gerg@snapgear.com.
630  */
631 int is_dsp_inst(struct pt_regs *regs)
632 {
633         unsigned short inst = 0;
634
635         /*
636          * Safe guard if DSP mode is already enabled or we're lacking
637          * the DSP altogether.
638          */
639         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
640                 return 0;
641
642         get_user(inst, ((unsigned short *) regs->pc));
643
644         inst &= 0xf000;
645
646         /* Check for any type of DSP or support instruction */
647         if ((inst == 0xf000) || (inst == 0x4000))
648                 return 1;
649
650         return 0;
651 }
652 #else
653 #define is_dsp_inst(regs)       (0)
654 #endif /* CONFIG_SH_DSP */
655
656 #ifdef CONFIG_CPU_SH2A
657 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
658                                 unsigned long r6, unsigned long r7,
659                                 struct pt_regs __regs)
660 {
661         siginfo_t info;
662
663         switch (r4) {
664         case TRAP_DIVZERO_ERROR:
665                 info.si_code = FPE_INTDIV;
666                 break;
667         case TRAP_DIVOVF_ERROR:
668                 info.si_code = FPE_INTOVF;
669                 break;
670         }
671
672         force_sig_info(SIGFPE, &info, current);
673 }
674 #endif
675
676 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
677                                 unsigned long r6, unsigned long r7,
678                                 struct pt_regs __regs)
679 {
680         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
681         unsigned long error_code;
682         struct task_struct *tsk = current;
683
684 #ifdef CONFIG_SH_FPU_EMU
685         unsigned short inst = 0;
686         int err;
687
688         get_user(inst, (unsigned short*)regs->pc);
689
690         err = do_fpu_inst(inst, regs);
691         if (!err) {
692                 regs->pc += instruction_size(inst);
693                 return;
694         }
695         /* not a FPU inst. */
696 #endif
697
698 #ifdef CONFIG_SH_DSP
699         /* Check if it's a DSP instruction */
700         if (is_dsp_inst(regs)) {
701                 /* Enable DSP mode, and restart instruction. */
702                 regs->sr |= SR_DSP;
703                 /* Save DSP mode */
704                 tsk->thread.dsp_status.status |= SR_DSP;
705                 return;
706         }
707 #endif
708
709         error_code = lookup_exception_vector();
710
711         local_irq_enable();
712         force_sig(SIGILL, tsk);
713         die_if_no_fixup("reserved instruction", regs, error_code);
714 }
715
716 #ifdef CONFIG_SH_FPU_EMU
717 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
718 {
719         /*
720          * bfs: 8fxx: PC+=d*2+4;
721          * bts: 8dxx: PC+=d*2+4;
722          * bra: axxx: PC+=D*2+4;
723          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
724          * braf:0x23: PC+=Rn*2+4;
725          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
726          * jmp: 4x2b: PC=Rn;
727          * jsr: 4x0b: PC=Rn      after PR=PC+4;
728          * rts: 000b: PC=PR;
729          */
730         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
731             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
732             ((inst & 0xf0ff) == 0x400b))        /* jsr */
733                 regs->pr = regs->pc + 4;
734
735         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
736                 regs->pc += SH_PC_8BIT_OFFSET(inst);
737                 return 0;
738         }
739
740         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
741                 regs->pc += SH_PC_12BIT_OFFSET(inst);
742                 return 0;
743         }
744
745         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
746                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
747                 return 0;
748         }
749
750         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
751                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
752                 return 0;
753         }
754
755         if ((inst & 0xffff) == 0x000b) {        /* rts */
756                 regs->pc = regs->pr;
757                 return 0;
758         }
759
760         return 1;
761 }
762 #endif
763
764 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
765                                 unsigned long r6, unsigned long r7,
766                                 struct pt_regs __regs)
767 {
768         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
769         unsigned long inst;
770         struct task_struct *tsk = current;
771
772         if (kprobe_handle_illslot(regs->pc) == 0)
773                 return;
774
775 #ifdef CONFIG_SH_FPU_EMU
776         get_user(inst, (unsigned short *)regs->pc + 1);
777         if (!do_fpu_inst(inst, regs)) {
778                 get_user(inst, (unsigned short *)regs->pc);
779                 if (!emulate_branch(inst, regs))
780                         return;
781                 /* fault in branch.*/
782         }
783         /* not a FPU inst. */
784 #endif
785
786         inst = lookup_exception_vector();
787
788         local_irq_enable();
789         force_sig(SIGILL, tsk);
790         die_if_no_fixup("illegal slot instruction", regs, inst);
791 }
792
793 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
794                                    unsigned long r6, unsigned long r7,
795                                    struct pt_regs __regs)
796 {
797         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
798         long ex;
799
800         ex = lookup_exception_vector();
801         die_if_kernel("exception", regs, ex);
802 }
803
804 void __cpuinit per_cpu_trap_init(void)
805 {
806         extern void *vbr_base;
807
808         /* NOTE: The VBR value should be at P1
809            (or P2, virtural "fixed" address space).
810            It's definitely should not in physical address.  */
811
812         asm volatile("ldc       %0, vbr"
813                      : /* no output */
814                      : "r" (&vbr_base)
815                      : "memory");
816
817         /* disable exception blocking now when the vbr has been setup */
818         clear_bl_bit();
819 }
820
821 void *set_exception_table_vec(unsigned int vec, void *handler)
822 {
823         extern void *exception_handling_table[];
824         void *old_handler;
825
826         old_handler = exception_handling_table[vec];
827         exception_handling_table[vec] = handler;
828         return old_handler;
829 }
830
831 void __init trap_init(void)
832 {
833         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
834         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
835
836 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
837     defined(CONFIG_SH_FPU_EMU)
838         /*
839          * For SH-4 lacking an FPU, treat floating point instructions as
840          * reserved. They'll be handled in the math-emu case, or faulted on
841          * otherwise.
842          */
843         set_exception_table_evt(0x800, do_reserved_inst);
844         set_exception_table_evt(0x820, do_illegal_slot_inst);
845 #elif defined(CONFIG_SH_FPU)
846         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
847         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
848 #endif
849
850 #ifdef CONFIG_CPU_SH2
851         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
852 #endif
853 #ifdef CONFIG_CPU_SH2A
854         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
855         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
856 #ifdef CONFIG_SH_FPU
857         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
858 #endif
859 #endif
860
861 #ifdef TRAP_UBC
862         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
863 #endif
864 }
865
866 void show_stack(struct task_struct *tsk, unsigned long *sp)
867 {
868         unsigned long stack;
869
870         if (!tsk)
871                 tsk = current;
872         if (tsk == current)
873                 sp = (unsigned long *)current_stack_pointer;
874         else
875                 sp = (unsigned long *)tsk->thread.sp;
876
877         stack = (unsigned long)sp;
878         dump_mem("Stack: ", stack, THREAD_SIZE +
879                  (unsigned long)task_stack_page(tsk));
880         show_trace(tsk, sp, NULL);
881 }
882
883 void dump_stack(void)
884 {
885         show_stack(NULL, NULL);
886 }
887 EXPORT_SYMBOL(dump_stack);