sh: Tidy up a couple of section mismatches.
[linux-2.6.git] / arch / sh / kernel / perf_event.c
1 /*
2  * Performance event support framework for SuperH hardware counters.
3  *
4  *  Copyright (C) 2009  Paul Mundt
5  *
6  * Heavily based on the x86 and PowerPC implementations.
7  *
8  * x86:
9  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
10  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
11  *  Copyright (C) 2009 Jaswinder Singh Rajput
12  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
13  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
14  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
15  *
16  * ppc:
17  *  Copyright 2008-2009 Paul Mackerras, IBM Corporation.
18  *
19  * This file is subject to the terms and conditions of the GNU General Public
20  * License.  See the file "COPYING" in the main directory of this archive
21  * for more details.
22  */
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/perf_event.h>
28 #include <asm/processor.h>
29
30 struct cpu_hw_events {
31         struct perf_event       *events[MAX_HWEVENTS];
32         unsigned long           used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
33         unsigned long           active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
34 };
35
36 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
37
38 static struct sh_pmu *sh_pmu __read_mostly;
39
40 /* Number of perf_events counting hardware events */
41 static atomic_t num_events;
42 /* Used to avoid races in calling reserve/release_pmc_hardware */
43 static DEFINE_MUTEX(pmc_reserve_mutex);
44
45 /*
46  * Stub these out for now, do something more profound later.
47  */
48 int reserve_pmc_hardware(void)
49 {
50         return 0;
51 }
52
53 void release_pmc_hardware(void)
54 {
55 }
56
57 static inline int sh_pmu_initialized(void)
58 {
59         return !!sh_pmu;
60 }
61
62 /*
63  * Release the PMU if this is the last perf_event.
64  */
65 static void hw_perf_event_destroy(struct perf_event *event)
66 {
67         if (!atomic_add_unless(&num_events, -1, 1)) {
68                 mutex_lock(&pmc_reserve_mutex);
69                 if (atomic_dec_return(&num_events) == 0)
70                         release_pmc_hardware();
71                 mutex_unlock(&pmc_reserve_mutex);
72         }
73 }
74
75 static int hw_perf_cache_event(int config, int *evp)
76 {
77         unsigned long type, op, result;
78         int ev;
79
80         if (!sh_pmu->cache_events)
81                 return -EINVAL;
82
83         /* unpack config */
84         type = config & 0xff;
85         op = (config >> 8) & 0xff;
86         result = (config >> 16) & 0xff;
87
88         if (type >= PERF_COUNT_HW_CACHE_MAX ||
89             op >= PERF_COUNT_HW_CACHE_OP_MAX ||
90             result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
91                 return -EINVAL;
92
93         ev = (*sh_pmu->cache_events)[type][op][result];
94         if (ev == 0)
95                 return -EOPNOTSUPP;
96         if (ev == -1)
97                 return -EINVAL;
98         *evp = ev;
99         return 0;
100 }
101
102 static int __hw_perf_event_init(struct perf_event *event)
103 {
104         struct perf_event_attr *attr = &event->attr;
105         struct hw_perf_event *hwc = &event->hw;
106         int config = -1;
107         int err;
108
109         if (!sh_pmu_initialized())
110                 return -ENODEV;
111
112         /*
113          * All of the on-chip counters are "limited", in that they have
114          * no interrupts, and are therefore unable to do sampling without
115          * further work and timer assistance.
116          */
117         if (hwc->sample_period)
118                 return -EINVAL;
119
120         /*
121          * See if we need to reserve the counter.
122          *
123          * If no events are currently in use, then we have to take a
124          * mutex to ensure that we don't race with another task doing
125          * reserve_pmc_hardware or release_pmc_hardware.
126          */
127         err = 0;
128         if (!atomic_inc_not_zero(&num_events)) {
129                 mutex_lock(&pmc_reserve_mutex);
130                 if (atomic_read(&num_events) == 0 &&
131                     reserve_pmc_hardware())
132                         err = -EBUSY;
133                 else
134                         atomic_inc(&num_events);
135                 mutex_unlock(&pmc_reserve_mutex);
136         }
137
138         if (err)
139                 return err;
140
141         event->destroy = hw_perf_event_destroy;
142
143         switch (attr->type) {
144         case PERF_TYPE_RAW:
145                 config = attr->config & sh_pmu->raw_event_mask;
146                 break;
147         case PERF_TYPE_HW_CACHE:
148                 err = hw_perf_cache_event(attr->config, &config);
149                 if (err)
150                         return err;
151                 break;
152         case PERF_TYPE_HARDWARE:
153                 if (attr->config >= sh_pmu->max_events)
154                         return -EINVAL;
155
156                 config = sh_pmu->event_map(attr->config);
157                 break;
158         }
159
160         if (config == -1)
161                 return -EINVAL;
162
163         hwc->config |= config;
164
165         return 0;
166 }
167
168 static void sh_perf_event_update(struct perf_event *event,
169                                    struct hw_perf_event *hwc, int idx)
170 {
171         u64 prev_raw_count, new_raw_count;
172         s64 delta;
173         int shift = 0;
174
175         /*
176          * Depending on the counter configuration, they may or may not
177          * be chained, in which case the previous counter value can be
178          * updated underneath us if the lower-half overflows.
179          *
180          * Our tactic to handle this is to first atomically read and
181          * exchange a new raw count - then add that new-prev delta
182          * count to the generic counter atomically.
183          *
184          * As there is no interrupt associated with the overflow events,
185          * this is the simplest approach for maintaining consistency.
186          */
187 again:
188         prev_raw_count = atomic64_read(&hwc->prev_count);
189         new_raw_count = sh_pmu->read(idx);
190
191         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
192                              new_raw_count) != prev_raw_count)
193                 goto again;
194
195         /*
196          * Now we have the new raw value and have updated the prev
197          * timestamp already. We can now calculate the elapsed delta
198          * (counter-)time and add that to the generic counter.
199          *
200          * Careful, not all hw sign-extends above the physical width
201          * of the count.
202          */
203         delta = (new_raw_count << shift) - (prev_raw_count << shift);
204         delta >>= shift;
205
206         atomic64_add(delta, &event->count);
207 }
208
209 static void sh_pmu_disable(struct perf_event *event)
210 {
211         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
212         struct hw_perf_event *hwc = &event->hw;
213         int idx = hwc->idx;
214
215         clear_bit(idx, cpuc->active_mask);
216         sh_pmu->disable(hwc, idx);
217
218         barrier();
219
220         sh_perf_event_update(event, &event->hw, idx);
221
222         cpuc->events[idx] = NULL;
223         clear_bit(idx, cpuc->used_mask);
224
225         perf_event_update_userpage(event);
226 }
227
228 static int sh_pmu_enable(struct perf_event *event)
229 {
230         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
231         struct hw_perf_event *hwc = &event->hw;
232         int idx = hwc->idx;
233
234         if (test_and_set_bit(idx, cpuc->used_mask)) {
235                 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
236                 if (idx == sh_pmu->num_events)
237                         return -EAGAIN;
238
239                 set_bit(idx, cpuc->used_mask);
240                 hwc->idx = idx;
241         }
242
243         sh_pmu->disable(hwc, idx);
244
245         cpuc->events[idx] = event;
246         set_bit(idx, cpuc->active_mask);
247
248         sh_pmu->enable(hwc, idx);
249
250         perf_event_update_userpage(event);
251
252         return 0;
253 }
254
255 static void sh_pmu_read(struct perf_event *event)
256 {
257         sh_perf_event_update(event, &event->hw, event->hw.idx);
258 }
259
260 static const struct pmu pmu = {
261         .enable         = sh_pmu_enable,
262         .disable        = sh_pmu_disable,
263         .read           = sh_pmu_read,
264 };
265
266 const struct pmu *hw_perf_event_init(struct perf_event *event)
267 {
268         int err = __hw_perf_event_init(event);
269         if (unlikely(err)) {
270                 if (event->destroy)
271                         event->destroy(event);
272                 return ERR_PTR(err);
273         }
274
275         return &pmu;
276 }
277
278 static void sh_pmu_setup(int cpu)
279 {
280         struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
281
282         memset(cpuhw, 0, sizeof(struct cpu_hw_events));
283 }
284
285 static int __cpuinit
286 sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
287 {
288         unsigned int cpu = (long)hcpu;
289
290         switch (action & ~CPU_TASKS_FROZEN) {
291         case CPU_UP_PREPARE:
292                 sh_pmu_setup(cpu);
293                 break;
294
295         default:
296                 break;
297         }
298
299         return NOTIFY_OK;
300 }
301
302 void hw_perf_enable(void)
303 {
304         if (!sh_pmu_initialized())
305                 return;
306
307         sh_pmu->enable_all();
308 }
309
310 void hw_perf_disable(void)
311 {
312         if (!sh_pmu_initialized())
313                 return;
314
315         sh_pmu->disable_all();
316 }
317
318 int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
319 {
320         if (sh_pmu)
321                 return -EBUSY;
322         sh_pmu = pmu;
323
324         pr_info("Performance Events: %s support registered\n", pmu->name);
325
326         WARN_ON(pmu->num_events > MAX_HWEVENTS);
327
328         perf_cpu_notifier(sh_pmu_notifier);
329         return 0;
330 }