Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / sh / kernel / cpu / sh4a / setup-sh7770.c
1 /*
2  * SH7770 Setup
3  *
4  *  Copyright (C) 2006 - 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_timer.h>
15 #include <linux/io.h>
16
17 static struct plat_sci_port scif0_platform_data = {
18         .mapbase        = 0xff923000,
19         .flags          = UPF_BOOT_AUTOCONF,
20         .type           = PORT_SCIF,
21         .irqs           = { 61, 61, 61, 61 },
22 };
23
24 static struct platform_device scif0_device = {
25         .name           = "sh-sci",
26         .id             = 0,
27         .dev            = {
28                 .platform_data  = &scif0_platform_data,
29         },
30 };
31
32 static struct plat_sci_port scif1_platform_data = {
33         .mapbase        = 0xff924000,
34         .flags          = UPF_BOOT_AUTOCONF,
35         .type           = PORT_SCIF,
36         .irqs           = { 62, 62, 62, 62 },
37 };
38
39 static struct platform_device scif1_device = {
40         .name           = "sh-sci",
41         .id             = 1,
42         .dev            = {
43                 .platform_data  = &scif1_platform_data,
44         },
45 };
46
47 static struct plat_sci_port scif2_platform_data = {
48         .mapbase        = 0xff925000,
49         .flags          = UPF_BOOT_AUTOCONF,
50         .type           = PORT_SCIF,
51         .irqs           = { 63, 63, 63, 63 },
52 };
53
54 static struct platform_device scif2_device = {
55         .name           = "sh-sci",
56         .id             = 2,
57         .dev            = {
58                 .platform_data  = &scif2_platform_data,
59         },
60 };
61
62 static struct plat_sci_port scif3_platform_data = {
63         .mapbase        = 0xff926000,
64         .flags          = UPF_BOOT_AUTOCONF,
65         .type           = PORT_SCIF,
66         .irqs           = { 64, 64, 64, 64 },
67 };
68
69 static struct platform_device scif3_device = {
70         .name           = "sh-sci",
71         .id             = 3,
72         .dev            = {
73                 .platform_data  = &scif3_platform_data,
74         },
75 };
76
77 static struct plat_sci_port scif4_platform_data = {
78         .mapbase        = 0xff927000,
79         .flags          = UPF_BOOT_AUTOCONF,
80         .type           = PORT_SCIF,
81         .irqs           = { 65, 65, 65, 65 },
82 };
83
84 static struct platform_device scif4_device = {
85         .name           = "sh-sci",
86         .id             = 4,
87         .dev            = {
88                 .platform_data  = &scif4_platform_data,
89         },
90 };
91
92 static struct plat_sci_port scif5_platform_data = {
93         .mapbase        = 0xff928000,
94         .flags          = UPF_BOOT_AUTOCONF,
95         .type           = PORT_SCIF,
96         .irqs           = { 66, 66, 66, 66 },
97 };
98
99 static struct platform_device scif5_device = {
100         .name           = "sh-sci",
101         .id             = 5,
102         .dev            = {
103                 .platform_data  = &scif5_platform_data,
104         },
105 };
106
107 static struct plat_sci_port scif6_platform_data = {
108         .mapbase        = 0xff929000,
109         .flags          = UPF_BOOT_AUTOCONF,
110         .type           = PORT_SCIF,
111         .irqs           = { 67, 67, 67, 67 },
112 };
113
114 static struct platform_device scif6_device = {
115         .name           = "sh-sci",
116         .id             = 6,
117         .dev            = {
118                 .platform_data  = &scif6_platform_data,
119         },
120 };
121
122 static struct plat_sci_port scif7_platform_data = {
123         .mapbase        = 0xff92a000,
124         .flags          = UPF_BOOT_AUTOCONF,
125         .type           = PORT_SCIF,
126         .irqs           = { 68, 68, 68, 68 },
127 };
128
129 static struct platform_device scif7_device = {
130         .name           = "sh-sci",
131         .id             = 7,
132         .dev            = {
133                 .platform_data  = &scif7_platform_data,
134         },
135 };
136
137 static struct plat_sci_port scif8_platform_data = {
138         .mapbase        = 0xff92b000,
139         .flags          = UPF_BOOT_AUTOCONF,
140         .type           = PORT_SCIF,
141         .irqs           = { 69, 69, 69, 69 },
142 };
143
144 static struct platform_device scif8_device = {
145         .name           = "sh-sci",
146         .id             = 8,
147         .dev            = {
148                 .platform_data  = &scif8_platform_data,
149         },
150 };
151
152 static struct plat_sci_port scif9_platform_data = {
153         .mapbase        = 0xff92c000,
154         .flags          = UPF_BOOT_AUTOCONF,
155         .type           = PORT_SCIF,
156         .irqs           = { 70, 70, 70, 70 },
157 };
158
159 static struct platform_device scif9_device = {
160         .name           = "sh-sci",
161         .id             = 9,
162         .dev            = {
163                 .platform_data  = &scif9_platform_data,
164         },
165 };
166
167 static struct sh_timer_config tmu0_platform_data = {
168         .name = "TMU0",
169         .channel_offset = 0x04,
170         .timer_bit = 0,
171         .clk = "peripheral_clk",
172         .clockevent_rating = 200,
173 };
174
175 static struct resource tmu0_resources[] = {
176         [0] = {
177                 .name   = "TMU0",
178                 .start  = 0xffd80008,
179                 .end    = 0xffd80013,
180                 .flags  = IORESOURCE_MEM,
181         },
182         [1] = {
183                 .start  = 16,
184                 .flags  = IORESOURCE_IRQ,
185         },
186 };
187
188 static struct platform_device tmu0_device = {
189         .name           = "sh_tmu",
190         .id             = 0,
191         .dev = {
192                 .platform_data  = &tmu0_platform_data,
193         },
194         .resource       = tmu0_resources,
195         .num_resources  = ARRAY_SIZE(tmu0_resources),
196 };
197
198 static struct sh_timer_config tmu1_platform_data = {
199         .name = "TMU1",
200         .channel_offset = 0x10,
201         .timer_bit = 1,
202         .clk = "peripheral_clk",
203         .clocksource_rating = 200,
204 };
205
206 static struct resource tmu1_resources[] = {
207         [0] = {
208                 .name   = "TMU1",
209                 .start  = 0xffd80014,
210                 .end    = 0xffd8001f,
211                 .flags  = IORESOURCE_MEM,
212         },
213         [1] = {
214                 .start  = 17,
215                 .flags  = IORESOURCE_IRQ,
216         },
217 };
218
219 static struct platform_device tmu1_device = {
220         .name           = "sh_tmu",
221         .id             = 1,
222         .dev = {
223                 .platform_data  = &tmu1_platform_data,
224         },
225         .resource       = tmu1_resources,
226         .num_resources  = ARRAY_SIZE(tmu1_resources),
227 };
228
229 static struct sh_timer_config tmu2_platform_data = {
230         .name = "TMU2",
231         .channel_offset = 0x1c,
232         .timer_bit = 2,
233         .clk = "peripheral_clk",
234 };
235
236 static struct resource tmu2_resources[] = {
237         [0] = {
238                 .name   = "TMU2",
239                 .start  = 0xffd80020,
240                 .end    = 0xffd8002f,
241                 .flags  = IORESOURCE_MEM,
242         },
243         [1] = {
244                 .start  = 18,
245                 .flags  = IORESOURCE_IRQ,
246         },
247 };
248
249 static struct platform_device tmu2_device = {
250         .name           = "sh_tmu",
251         .id             = 2,
252         .dev = {
253                 .platform_data  = &tmu2_platform_data,
254         },
255         .resource       = tmu2_resources,
256         .num_resources  = ARRAY_SIZE(tmu2_resources),
257 };
258
259 static struct sh_timer_config tmu3_platform_data = {
260         .name = "TMU3",
261         .channel_offset = 0x04,
262         .timer_bit = 0,
263         .clk = "peripheral_clk",
264 };
265
266 static struct resource tmu3_resources[] = {
267         [0] = {
268                 .name   = "TMU3",
269                 .start  = 0xffd81008,
270                 .end    = 0xffd81013,
271                 .flags  = IORESOURCE_MEM,
272         },
273         [1] = {
274                 .start  = 19,
275                 .flags  = IORESOURCE_IRQ,
276         },
277 };
278
279 static struct platform_device tmu3_device = {
280         .name           = "sh_tmu",
281         .id             = 3,
282         .dev = {
283                 .platform_data  = &tmu3_platform_data,
284         },
285         .resource       = tmu3_resources,
286         .num_resources  = ARRAY_SIZE(tmu3_resources),
287 };
288
289 static struct sh_timer_config tmu4_platform_data = {
290         .name = "TMU4",
291         .channel_offset = 0x10,
292         .timer_bit = 1,
293         .clk = "peripheral_clk",
294 };
295
296 static struct resource tmu4_resources[] = {
297         [0] = {
298                 .name   = "TMU4",
299                 .start  = 0xffd81014,
300                 .end    = 0xffd8101f,
301                 .flags  = IORESOURCE_MEM,
302         },
303         [1] = {
304                 .start  = 20,
305                 .flags  = IORESOURCE_IRQ,
306         },
307 };
308
309 static struct platform_device tmu4_device = {
310         .name           = "sh_tmu",
311         .id             = 4,
312         .dev = {
313                 .platform_data  = &tmu4_platform_data,
314         },
315         .resource       = tmu4_resources,
316         .num_resources  = ARRAY_SIZE(tmu4_resources),
317 };
318
319 static struct sh_timer_config tmu5_platform_data = {
320         .name = "TMU5",
321         .channel_offset = 0x1c,
322         .timer_bit = 2,
323         .clk = "peripheral_clk",
324 };
325
326 static struct resource tmu5_resources[] = {
327         [0] = {
328                 .name   = "TMU5",
329                 .start  = 0xffd81020,
330                 .end    = 0xffd8102f,
331                 .flags  = IORESOURCE_MEM,
332         },
333         [1] = {
334                 .start  = 21,
335                 .flags  = IORESOURCE_IRQ,
336         },
337 };
338
339 static struct platform_device tmu5_device = {
340         .name           = "sh_tmu",
341         .id             = 5,
342         .dev = {
343                 .platform_data  = &tmu5_platform_data,
344         },
345         .resource       = tmu5_resources,
346         .num_resources  = ARRAY_SIZE(tmu5_resources),
347 };
348
349 static struct sh_timer_config tmu6_platform_data = {
350         .name = "TMU6",
351         .channel_offset = 0x04,
352         .timer_bit = 0,
353         .clk = "peripheral_clk",
354 };
355
356 static struct resource tmu6_resources[] = {
357         [0] = {
358                 .name   = "TMU6",
359                 .start  = 0xffd82008,
360                 .end    = 0xffd82013,
361                 .flags  = IORESOURCE_MEM,
362         },
363         [1] = {
364                 .start  = 22,
365                 .flags  = IORESOURCE_IRQ,
366         },
367 };
368
369 static struct platform_device tmu6_device = {
370         .name           = "sh_tmu",
371         .id             = 6,
372         .dev = {
373                 .platform_data  = &tmu6_platform_data,
374         },
375         .resource       = tmu6_resources,
376         .num_resources  = ARRAY_SIZE(tmu6_resources),
377 };
378
379 static struct sh_timer_config tmu7_platform_data = {
380         .name = "TMU7",
381         .channel_offset = 0x10,
382         .timer_bit = 1,
383         .clk = "peripheral_clk",
384 };
385
386 static struct resource tmu7_resources[] = {
387         [0] = {
388                 .name   = "TMU7",
389                 .start  = 0xffd82014,
390                 .end    = 0xffd8201f,
391                 .flags  = IORESOURCE_MEM,
392         },
393         [1] = {
394                 .start  = 23,
395                 .flags  = IORESOURCE_IRQ,
396         },
397 };
398
399 static struct platform_device tmu7_device = {
400         .name           = "sh_tmu",
401         .id             = 7,
402         .dev = {
403                 .platform_data  = &tmu7_platform_data,
404         },
405         .resource       = tmu7_resources,
406         .num_resources  = ARRAY_SIZE(tmu7_resources),
407 };
408
409 static struct sh_timer_config tmu8_platform_data = {
410         .name = "TMU8",
411         .channel_offset = 0x1c,
412         .timer_bit = 2,
413         .clk = "peripheral_clk",
414 };
415
416 static struct resource tmu8_resources[] = {
417         [0] = {
418                 .name   = "TMU8",
419                 .start  = 0xffd82020,
420                 .end    = 0xffd8202b,
421                 .flags  = IORESOURCE_MEM,
422         },
423         [1] = {
424                 .start  = 24,
425                 .flags  = IORESOURCE_IRQ,
426         },
427 };
428
429 static struct platform_device tmu8_device = {
430         .name           = "sh_tmu",
431         .id             = 8,
432         .dev = {
433                 .platform_data  = &tmu8_platform_data,
434         },
435         .resource       = tmu8_resources,
436         .num_resources  = ARRAY_SIZE(tmu8_resources),
437 };
438
439 static struct platform_device *sh7770_devices[] __initdata = {
440         &scif0_device,
441         &scif1_device,
442         &scif2_device,
443         &scif3_device,
444         &scif4_device,
445         &scif5_device,
446         &scif6_device,
447         &scif7_device,
448         &scif8_device,
449         &scif9_device,
450         &tmu0_device,
451         &tmu1_device,
452         &tmu2_device,
453         &tmu3_device,
454         &tmu4_device,
455         &tmu5_device,
456         &tmu6_device,
457         &tmu7_device,
458         &tmu8_device,
459 };
460
461 static int __init sh7770_devices_setup(void)
462 {
463         return platform_add_devices(sh7770_devices,
464                                     ARRAY_SIZE(sh7770_devices));
465 }
466 arch_initcall(sh7770_devices_setup);
467
468 static struct platform_device *sh7770_early_devices[] __initdata = {
469         &scif0_device,
470         &scif1_device,
471         &scif2_device,
472         &scif3_device,
473         &scif4_device,
474         &scif5_device,
475         &scif6_device,
476         &scif7_device,
477         &scif8_device,
478         &scif9_device,
479         &tmu0_device,
480         &tmu1_device,
481         &tmu2_device,
482         &tmu3_device,
483         &tmu4_device,
484         &tmu5_device,
485         &tmu6_device,
486         &tmu7_device,
487         &tmu8_device,
488 };
489
490 void __init plat_early_device_setup(void)
491 {
492         early_platform_add_devices(sh7770_early_devices,
493                                    ARRAY_SIZE(sh7770_early_devices));
494 }
495
496 enum {
497         UNUSED = 0,
498
499         /* interrupt sources */
500         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
501         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
502         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
503         IRL_HHLL, IRL_HHLH, IRL_HHHL,
504
505         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
506
507         GPIO,
508         TMU0, TMU1, TMU2, TMU2_TICPI,
509         TMU3, TMU4, TMU5, TMU5_TICPI,
510         TMU6, TMU7, TMU8,
511         HAC, IPI, SPDIF, HUDI, I2C,
512         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
513         I2S0, I2S1, I2S2, I2S3,
514         SRC_RX, SRC_TX, SRC_SPDIF,
515         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
516         GFX3D_MBX, GFX3D_DMAC,
517         EXBUS_ATA,
518         SPI0, SPI1,
519         SCIF089, SCIF1234, SCIF567,
520         ADC,
521         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
522         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
523         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
524
525         /* interrupt groups */
526         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
527 };
528
529 static struct intc_vect vectors[] __initdata = {
530         INTC_VECT(GPIO, 0x3e0),
531         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
532         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
533         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
534         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
535         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
536         INTC_VECT(TMU8, 0x540),
537         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
538         INTC_VECT(SPDIF, 0x5e0),
539         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
540         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
541         INTC_VECT(DMAC0_DMINT2, 0x680),
542         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
543         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
544         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
545         INTC_VECT(SRC_SPDIF, 0x760),
546         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
547         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
548         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
549         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
550         INTC_VECT(GFX2D, 0x8c0),
551         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
552         INTC_VECT(EXBUS_ATA, 0x940),
553         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
554         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
555         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
556         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
557         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
558         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
559         INTC_VECT(ADC, 0xb20),
560         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
561         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
562         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
563         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
564         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
565         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
566         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
567         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
568         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
569         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
570         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
571         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
572         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
573         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
574         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
575         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
576 };
577
578 static struct intc_group groups[] __initdata = {
579         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
580                    TMU5_TICPI, TMU6, TMU7, TMU8),
581         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
582         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
583         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
584         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
585         INTC_GROUP(SPI, SPI0, SPI1),
586         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
587         INTC_GROUP(BBDMAC,
588                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
589                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
590                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
591 };
592
593 static struct intc_mask_reg mask_registers[] __initdata = {
594         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
595           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
596             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
597             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
598 };
599
600 static struct intc_prio_reg prio_registers[] __initdata = {
601         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
602         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
603         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
604         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
605         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
606         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
607         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
608         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
609         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
610           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
611         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
612           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
613         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
614           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
615         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
616           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
617         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
618           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
619         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
620           { TMU7, TMU8 } },
621 };
622
623 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
624                          mask_registers, prio_registers, NULL);
625
626 /* Support for external interrupt pins in IRQ mode */
627 static struct intc_vect irq_vectors[] __initdata = {
628         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
629         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
630         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
631 };
632
633 static struct intc_mask_reg irq_mask_registers[] __initdata = {
634         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
635           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
636 };
637
638 static struct intc_prio_reg irq_prio_registers[] __initdata = {
639         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
640                                                IRQ4, IRQ5, } },
641 };
642
643 static struct intc_sense_reg irq_sense_registers[] __initdata = {
644         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
645                                             IRQ4, IRQ5, } },
646 };
647
648 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
649                          NULL, irq_mask_registers, irq_prio_registers,
650                          irq_sense_registers);
651
652 /* External interrupt pins in IRL mode */
653 static struct intc_vect irl_vectors[] __initdata = {
654         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
655         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
656         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
657         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
658         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
659         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
660         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
661         INTC_VECT(IRL_HHHL, 0x3c0),
662 };
663
664 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
665         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
666           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
667             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
668             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
669             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
670 };
671
672 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
673         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
674           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
675             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
676             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
677             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
678             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
679 };
680
681 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
682                          NULL, irl7654_mask_registers, NULL, NULL);
683
684 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
685                          NULL, irl3210_mask_registers, NULL, NULL);
686
687 #define INTC_ICR0       0xffd00000
688 #define INTC_INTMSK0    0xffd00044
689 #define INTC_INTMSK1    0xffd00048
690 #define INTC_INTMSK2    0xffd40080
691 #define INTC_INTMSKCLR1 0xffd00068
692 #define INTC_INTMSKCLR2 0xffd40084
693
694 void __init plat_irq_setup(void)
695 {
696         /* disable IRQ7-0 */
697         ctrl_outl(0xff000000, INTC_INTMSK0);
698
699         /* disable IRL3-0 + IRL7-4 */
700         ctrl_outl(0xc0000000, INTC_INTMSK1);
701         ctrl_outl(0xfffefffe, INTC_INTMSK2);
702
703         /* select IRL mode for IRL3-0 + IRL7-4 */
704         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
705
706         /* disable holding function, ie enable "SH-4 Mode" */
707         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
708
709         register_intc_controller(&intc_desc);
710 }
711
712 void __init plat_irq_setup_pins(int mode)
713 {
714         switch (mode) {
715         case IRQ_MODE_IRQ:
716                 /* select IRQ mode for IRL3-0 + IRL7-4 */
717                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
718                 register_intc_controller(&intc_irq_desc);
719                 break;
720         case IRQ_MODE_IRL7654:
721                 /* enable IRL7-4 but don't provide any masking */
722                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
723                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
724                 break;
725         case IRQ_MODE_IRL3210:
726                 /* enable IRL0-3 but don't provide any masking */
727                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
728                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
729                 break;
730         case IRQ_MODE_IRL7654_MASK:
731                 /* enable IRL7-4 and mask using cpu intc controller */
732                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
733                 register_intc_controller(&intc_irl7654_desc);
734                 break;
735         case IRQ_MODE_IRL3210_MASK:
736                 /* enable IRL0-3 and mask using cpu intc controller */
737                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
738                 register_intc_controller(&intc_irl3210_desc);
739                 break;
740         default:
741                 BUG();
742         }
743 }