1 #ifndef __ASM_CPU_SH2A_CACHEFLUSH_H
2 #define __ASM_CPU_SH2A_CACHEFLUSH_H
7 * - flush_cache_all() flushes entire cache
8 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
9 * - flush_cache_dup mm(mm) handles cache flushing when forking
10 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
11 * - flush_cache_range(vma, start, end) flushes a range of pages
13 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
14 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
15 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
17 * Caches are indexed (effectively) by physical address on SH-2, so
20 #define flush_cache_all() do { } while (0)
21 #define flush_cache_mm(mm) do { } while (0)
22 #define flush_cache_dup_mm(mm) do { } while (0)
23 #define flush_cache_range(vma, start, end) do { } while (0)
24 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
25 #define flush_dcache_page(page) do { } while (0)
26 void flush_icache_range(unsigned long start, unsigned long end);
27 #define flush_icache_page(vma,pg) do { } while (0)
28 #define flush_cache_sigtramp(vaddr) do { } while (0)
30 #endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */