powerpc: Convert to new irq_* function names
[linux-2.6.git] / arch / powerpc / sysdev / qe_lib / qe_ic.c
1 /*
2  * arch/powerpc/sysdev/qe_lib/qe_ic.c
3  *
4  * Copyright (C) 2006 Freescale Semicondutor, Inc.  All rights reserved.
5  *
6  * Author: Li Yang <leoli@freescale.com>
7  * Based on code from Shlomi Gridish <gridish@freescale.com>
8  *
9  * QUICC ENGINE Interrupt Controller
10  *
11  * This program is free software; you can redistribute  it and/or modify it
12  * under  the terms of  the GNU General  Public License as published by the
13  * Free Software Foundation;  either version 2 of the  License, or (at your
14  * option) any later version.
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/slab.h>
22 #include <linux/stddef.h>
23 #include <linux/sched.h>
24 #include <linux/signal.h>
25 #include <linux/sysdev.h>
26 #include <linux/device.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <asm/irq.h>
30 #include <asm/io.h>
31 #include <asm/prom.h>
32 #include <asm/qe_ic.h>
33
34 #include "qe_ic.h"
35
36 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
37
38 static struct qe_ic_info qe_ic_info[] = {
39         [1] = {
40                .mask = 0x00008000,
41                .mask_reg = QEIC_CIMR,
42                .pri_code = 0,
43                .pri_reg = QEIC_CIPWCC,
44                },
45         [2] = {
46                .mask = 0x00004000,
47                .mask_reg = QEIC_CIMR,
48                .pri_code = 1,
49                .pri_reg = QEIC_CIPWCC,
50                },
51         [3] = {
52                .mask = 0x00002000,
53                .mask_reg = QEIC_CIMR,
54                .pri_code = 2,
55                .pri_reg = QEIC_CIPWCC,
56                },
57         [10] = {
58                 .mask = 0x00000040,
59                 .mask_reg = QEIC_CIMR,
60                 .pri_code = 1,
61                 .pri_reg = QEIC_CIPZCC,
62                 },
63         [11] = {
64                 .mask = 0x00000020,
65                 .mask_reg = QEIC_CIMR,
66                 .pri_code = 2,
67                 .pri_reg = QEIC_CIPZCC,
68                 },
69         [12] = {
70                 .mask = 0x00000010,
71                 .mask_reg = QEIC_CIMR,
72                 .pri_code = 3,
73                 .pri_reg = QEIC_CIPZCC,
74                 },
75         [13] = {
76                 .mask = 0x00000008,
77                 .mask_reg = QEIC_CIMR,
78                 .pri_code = 4,
79                 .pri_reg = QEIC_CIPZCC,
80                 },
81         [14] = {
82                 .mask = 0x00000004,
83                 .mask_reg = QEIC_CIMR,
84                 .pri_code = 5,
85                 .pri_reg = QEIC_CIPZCC,
86                 },
87         [15] = {
88                 .mask = 0x00000002,
89                 .mask_reg = QEIC_CIMR,
90                 .pri_code = 6,
91                 .pri_reg = QEIC_CIPZCC,
92                 },
93         [20] = {
94                 .mask = 0x10000000,
95                 .mask_reg = QEIC_CRIMR,
96                 .pri_code = 3,
97                 .pri_reg = QEIC_CIPRTA,
98                 },
99         [25] = {
100                 .mask = 0x00800000,
101                 .mask_reg = QEIC_CRIMR,
102                 .pri_code = 0,
103                 .pri_reg = QEIC_CIPRTB,
104                 },
105         [26] = {
106                 .mask = 0x00400000,
107                 .mask_reg = QEIC_CRIMR,
108                 .pri_code = 1,
109                 .pri_reg = QEIC_CIPRTB,
110                 },
111         [27] = {
112                 .mask = 0x00200000,
113                 .mask_reg = QEIC_CRIMR,
114                 .pri_code = 2,
115                 .pri_reg = QEIC_CIPRTB,
116                 },
117         [28] = {
118                 .mask = 0x00100000,
119                 .mask_reg = QEIC_CRIMR,
120                 .pri_code = 3,
121                 .pri_reg = QEIC_CIPRTB,
122                 },
123         [32] = {
124                 .mask = 0x80000000,
125                 .mask_reg = QEIC_CIMR,
126                 .pri_code = 0,
127                 .pri_reg = QEIC_CIPXCC,
128                 },
129         [33] = {
130                 .mask = 0x40000000,
131                 .mask_reg = QEIC_CIMR,
132                 .pri_code = 1,
133                 .pri_reg = QEIC_CIPXCC,
134                 },
135         [34] = {
136                 .mask = 0x20000000,
137                 .mask_reg = QEIC_CIMR,
138                 .pri_code = 2,
139                 .pri_reg = QEIC_CIPXCC,
140                 },
141         [35] = {
142                 .mask = 0x10000000,
143                 .mask_reg = QEIC_CIMR,
144                 .pri_code = 3,
145                 .pri_reg = QEIC_CIPXCC,
146                 },
147         [36] = {
148                 .mask = 0x08000000,
149                 .mask_reg = QEIC_CIMR,
150                 .pri_code = 4,
151                 .pri_reg = QEIC_CIPXCC,
152                 },
153         [40] = {
154                 .mask = 0x00800000,
155                 .mask_reg = QEIC_CIMR,
156                 .pri_code = 0,
157                 .pri_reg = QEIC_CIPYCC,
158                 },
159         [41] = {
160                 .mask = 0x00400000,
161                 .mask_reg = QEIC_CIMR,
162                 .pri_code = 1,
163                 .pri_reg = QEIC_CIPYCC,
164                 },
165         [42] = {
166                 .mask = 0x00200000,
167                 .mask_reg = QEIC_CIMR,
168                 .pri_code = 2,
169                 .pri_reg = QEIC_CIPYCC,
170                 },
171         [43] = {
172                 .mask = 0x00100000,
173                 .mask_reg = QEIC_CIMR,
174                 .pri_code = 3,
175                 .pri_reg = QEIC_CIPYCC,
176                 },
177 };
178
179 static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
180 {
181         return in_be32(base + (reg >> 2));
182 }
183
184 static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
185                                u32 value)
186 {
187         out_be32(base + (reg >> 2), value);
188 }
189
190 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191 {
192         return irq_get_chip_data(virq);
193 }
194
195 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
196 {
197         return irq_data_get_irq_chip_data(d);
198 }
199
200 #define virq_to_hw(virq)        ((unsigned int)irq_map[virq].hwirq)
201
202 static void qe_ic_unmask_irq(struct irq_data *d)
203 {
204         struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
205         unsigned int src = virq_to_hw(d->irq);
206         unsigned long flags;
207         u32 temp;
208
209         raw_spin_lock_irqsave(&qe_ic_lock, flags);
210
211         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
212         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
213                     temp | qe_ic_info[src].mask);
214
215         raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
216 }
217
218 static void qe_ic_mask_irq(struct irq_data *d)
219 {
220         struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
221         unsigned int src = virq_to_hw(d->irq);
222         unsigned long flags;
223         u32 temp;
224
225         raw_spin_lock_irqsave(&qe_ic_lock, flags);
226
227         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
228         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
229                     temp & ~qe_ic_info[src].mask);
230
231         /* Flush the above write before enabling interrupts; otherwise,
232          * spurious interrupts will sometimes happen.  To be 100% sure
233          * that the write has reached the device before interrupts are
234          * enabled, the mask register would have to be read back; however,
235          * this is not required for correctness, only to avoid wasting
236          * time on a large number of spurious interrupts.  In testing,
237          * a sync reduced the observed spurious interrupts to zero.
238          */
239         mb();
240
241         raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
242 }
243
244 static struct irq_chip qe_ic_irq_chip = {
245         .name = "QEIC",
246         .irq_unmask = qe_ic_unmask_irq,
247         .irq_mask = qe_ic_mask_irq,
248         .irq_mask_ack = qe_ic_mask_irq,
249 };
250
251 static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
252 {
253         /* Exact match, unless qe_ic node is NULL */
254         return h->of_node == NULL || h->of_node == node;
255 }
256
257 static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
258                           irq_hw_number_t hw)
259 {
260         struct qe_ic *qe_ic = h->host_data;
261         struct irq_chip *chip;
262
263         if (qe_ic_info[hw].mask == 0) {
264                 printk(KERN_ERR "Can't map reserved IRQ\n");
265                 return -EINVAL;
266         }
267         /* Default chip */
268         chip = &qe_ic->hc_irq;
269
270         irq_set_chip_data(virq, qe_ic);
271         irq_set_status_flags(virq, IRQ_LEVEL);
272
273         irq_set_chip_and_handler(virq, chip, handle_level_irq);
274
275         return 0;
276 }
277
278 static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
279                             const u32 * intspec, unsigned int intsize,
280                             irq_hw_number_t * out_hwirq,
281                             unsigned int *out_flags)
282 {
283         *out_hwirq = intspec[0];
284         if (intsize > 1)
285                 *out_flags = intspec[1];
286         else
287                 *out_flags = IRQ_TYPE_NONE;
288         return 0;
289 }
290
291 static struct irq_host_ops qe_ic_host_ops = {
292         .match = qe_ic_host_match,
293         .map = qe_ic_host_map,
294         .xlate = qe_ic_host_xlate,
295 };
296
297 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
298 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
299 {
300         int irq;
301
302         BUG_ON(qe_ic == NULL);
303
304         /* get the interrupt source vector. */
305         irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
306
307         if (irq == 0)
308                 return NO_IRQ;
309
310         return irq_linear_revmap(qe_ic->irqhost, irq);
311 }
312
313 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
314 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
315 {
316         int irq;
317
318         BUG_ON(qe_ic == NULL);
319
320         /* get the interrupt source vector. */
321         irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
322
323         if (irq == 0)
324                 return NO_IRQ;
325
326         return irq_linear_revmap(qe_ic->irqhost, irq);
327 }
328
329 void __init qe_ic_init(struct device_node *node, unsigned int flags,
330                 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
331                 void (*high_handler)(unsigned int irq, struct irq_desc *desc))
332 {
333         struct qe_ic *qe_ic;
334         struct resource res;
335         u32 temp = 0, ret, high_active = 0;
336
337         ret = of_address_to_resource(node, 0, &res);
338         if (ret)
339                 return;
340
341         qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
342         if (qe_ic == NULL)
343                 return;
344
345         qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
346                                         NR_QE_IC_INTS, &qe_ic_host_ops, 0);
347         if (qe_ic->irqhost == NULL) {
348                 kfree(qe_ic);
349                 return;
350         }
351
352         qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
353
354         qe_ic->irqhost->host_data = qe_ic;
355         qe_ic->hc_irq = qe_ic_irq_chip;
356
357         qe_ic->virq_high = irq_of_parse_and_map(node, 0);
358         qe_ic->virq_low = irq_of_parse_and_map(node, 1);
359
360         if (qe_ic->virq_low == NO_IRQ) {
361                 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
362                 kfree(qe_ic);
363                 return;
364         }
365
366         /* default priority scheme is grouped. If spread mode is    */
367         /* required, configure cicr accordingly.                    */
368         if (flags & QE_IC_SPREADMODE_GRP_W)
369                 temp |= CICR_GWCC;
370         if (flags & QE_IC_SPREADMODE_GRP_X)
371                 temp |= CICR_GXCC;
372         if (flags & QE_IC_SPREADMODE_GRP_Y)
373                 temp |= CICR_GYCC;
374         if (flags & QE_IC_SPREADMODE_GRP_Z)
375                 temp |= CICR_GZCC;
376         if (flags & QE_IC_SPREADMODE_GRP_RISCA)
377                 temp |= CICR_GRTA;
378         if (flags & QE_IC_SPREADMODE_GRP_RISCB)
379                 temp |= CICR_GRTB;
380
381         /* choose destination signal for highest priority interrupt */
382         if (flags & QE_IC_HIGH_SIGNAL) {
383                 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
384                 high_active = 1;
385         }
386
387         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
388
389         irq_set_handler_data(qe_ic->virq_low, qe_ic);
390         irq_set_chained_handler(qe_ic->virq_low, low_handler);
391
392         if (qe_ic->virq_high != NO_IRQ &&
393                         qe_ic->virq_high != qe_ic->virq_low) {
394                 irq_set_handler_data(qe_ic->virq_high, qe_ic);
395                 irq_set_chained_handler(qe_ic->virq_high, high_handler);
396         }
397 }
398
399 void qe_ic_set_highest_priority(unsigned int virq, int high)
400 {
401         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
402         unsigned int src = virq_to_hw(virq);
403         u32 temp = 0;
404
405         temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
406
407         temp &= ~CICR_HP_MASK;
408         temp |= src << CICR_HP_SHIFT;
409
410         temp &= ~CICR_HPIT_MASK;
411         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
412
413         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
414 }
415
416 /* Set Priority level within its group, from 1 to 8 */
417 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
418 {
419         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
420         unsigned int src = virq_to_hw(virq);
421         u32 temp;
422
423         if (priority > 8 || priority == 0)
424                 return -EINVAL;
425         if (src > 127)
426                 return -EINVAL;
427         if (qe_ic_info[src].pri_reg == 0)
428                 return -EINVAL;
429
430         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
431
432         if (priority < 4) {
433                 temp &= ~(0x7 << (32 - priority * 3));
434                 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
435         } else {
436                 temp &= ~(0x7 << (24 - priority * 3));
437                 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
438         }
439
440         qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
441
442         return 0;
443 }
444
445 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
446 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
447 {
448         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
449         unsigned int src = virq_to_hw(virq);
450         u32 temp, control_reg = QEIC_CICNR, shift = 0;
451
452         if (priority > 2 || priority == 0)
453                 return -EINVAL;
454
455         switch (qe_ic_info[src].pri_reg) {
456         case QEIC_CIPZCC:
457                 shift = CICNR_ZCC1T_SHIFT;
458                 break;
459         case QEIC_CIPWCC:
460                 shift = CICNR_WCC1T_SHIFT;
461                 break;
462         case QEIC_CIPYCC:
463                 shift = CICNR_YCC1T_SHIFT;
464                 break;
465         case QEIC_CIPXCC:
466                 shift = CICNR_XCC1T_SHIFT;
467                 break;
468         case QEIC_CIPRTA:
469                 shift = CRICR_RTA1T_SHIFT;
470                 control_reg = QEIC_CRICR;
471                 break;
472         case QEIC_CIPRTB:
473                 shift = CRICR_RTB1T_SHIFT;
474                 control_reg = QEIC_CRICR;
475                 break;
476         default:
477                 return -EINVAL;
478         }
479
480         shift += (2 - priority) * 2;
481         temp = qe_ic_read(qe_ic->regs, control_reg);
482         temp &= ~(SIGNAL_MASK << shift);
483         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
484         qe_ic_write(qe_ic->regs, control_reg, temp);
485
486         return 0;
487 }
488
489 static struct sysdev_class qe_ic_sysclass = {
490         .name = "qe_ic",
491 };
492
493 static struct sys_device device_qe_ic = {
494         .id = 0,
495         .cls = &qe_ic_sysclass,
496 };
497
498 static int __init init_qe_ic_sysfs(void)
499 {
500         int rc;
501
502         printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
503
504         rc = sysdev_class_register(&qe_ic_sysclass);
505         if (rc) {
506                 printk(KERN_ERR "Failed registering qe_ic sys class\n");
507                 return -ENODEV;
508         }
509         rc = sysdev_register(&device_qe_ic);
510         if (rc) {
511                 printk(KERN_ERR "Failed registering qe_ic sys device\n");
512                 return -ENODEV;
513         }
514         return 0;
515 }
516
517 subsys_initcall(init_qe_ic_sysfs);