6898e8241cd03826335aae8653e82a1775b5eb24
[linux-2.6.git] / arch / powerpc / platforms / powermac / smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
36
37 #include <asm/ptrace.h>
38 #include <asm/atomic.h>
39 #include <asm/code-patching.h>
40 #include <asm/irq.h>
41 #include <asm/page.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
44 #include <asm/io.h>
45 #include <asm/prom.h>
46 #include <asm/smp.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
49 #include <asm/time.h>
50 #include <asm/mpic.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
55
56 #undef DEBUG
57
58 #ifdef DEBUG
59 #define DBG(fmt...) udbg_printf(fmt)
60 #else
61 #define DBG(fmt...)
62 #endif
63
64 extern void __secondary_start_pmac_0(void);
65 extern int pmac_pfunc_base_install(void);
66
67 static void (*pmac_tb_freeze)(int freeze);
68 static u64 timebase;
69 static int tb_req;
70
71 #ifdef CONFIG_PPC32
72
73 /*
74  * Powersurge (old powermac SMP) support.
75  */
76
77 /* Addresses for powersurge registers */
78 #define HAMMERHEAD_BASE         0xf8000000
79 #define HHEAD_CONFIG            0x90
80 #define HHEAD_SEC_INTR          0xc0
81
82 /* register for interrupting the primary processor on the powersurge */
83 /* N.B. this is actually the ethernet ROM! */
84 #define PSURGE_PRI_INTR         0xf3019000
85
86 /* register for storing the start address for the secondary processor */
87 /* N.B. this is the PCI config space address register for the 1st bridge */
88 #define PSURGE_START            0xf2800000
89
90 /* Daystar/XLR8 4-CPU card */
91 #define PSURGE_QUAD_REG_ADDR    0xf8800000
92
93 #define PSURGE_QUAD_IRQ_SET     0
94 #define PSURGE_QUAD_IRQ_CLR     1
95 #define PSURGE_QUAD_IRQ_PRIMARY 2
96 #define PSURGE_QUAD_CKSTOP_CTL  3
97 #define PSURGE_QUAD_PRIMARY_ARB 4
98 #define PSURGE_QUAD_BOARD_ID    6
99 #define PSURGE_QUAD_WHICH_CPU   7
100 #define PSURGE_QUAD_CKSTOP_RDBK 8
101 #define PSURGE_QUAD_RESET_CTL   11
102
103 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
104 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
105 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
106 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
107
108 /* virtual addresses for the above */
109 static volatile u8 __iomem *hhead_base;
110 static volatile u8 __iomem *quad_base;
111 static volatile u32 __iomem *psurge_pri_intr;
112 static volatile u8 __iomem *psurge_sec_intr;
113 static volatile u32 __iomem *psurge_start;
114
115 /* values for psurge_type */
116 #define PSURGE_NONE             -1
117 #define PSURGE_DUAL             0
118 #define PSURGE_QUAD_OKEE        1
119 #define PSURGE_QUAD_COTTON      2
120 #define PSURGE_QUAD_ICEGRASS    3
121
122 /* what sort of powersurge board we have */
123 static int psurge_type = PSURGE_NONE;
124
125 /*
126  * Set and clear IPIs for powersurge.
127  */
128 static inline void psurge_set_ipi(int cpu)
129 {
130         if (psurge_type == PSURGE_NONE)
131                 return;
132         if (cpu == 0)
133                 in_be32(psurge_pri_intr);
134         else if (psurge_type == PSURGE_DUAL)
135                 out_8(psurge_sec_intr, 0);
136         else
137                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
138 }
139
140 static inline void psurge_clr_ipi(int cpu)
141 {
142         if (cpu > 0) {
143                 switch(psurge_type) {
144                 case PSURGE_DUAL:
145                         out_8(psurge_sec_intr, ~0);
146                 case PSURGE_NONE:
147                         break;
148                 default:
149                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
150                 }
151         }
152 }
153
154 /*
155  * On powersurge (old SMP powermac architecture) we don't have
156  * separate IPIs for separate messages like openpic does.  Instead
157  * we have a bitmap for each processor, where a 1 bit means that
158  * the corresponding message is pending for that processor.
159  * Ideally each cpu's entry would be in a different cache line.
160  *  -- paulus.
161  */
162 static unsigned long psurge_smp_message[NR_CPUS];
163
164 void psurge_smp_message_recv(void)
165 {
166         int cpu = smp_processor_id();
167         int msg;
168
169         /* clear interrupt */
170         psurge_clr_ipi(cpu);
171
172         if (num_online_cpus() < 2)
173                 return;
174
175         /* make sure there is a message there */
176         for (msg = 0; msg < 4; msg++)
177                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
178                         smp_message_recv(msg);
179 }
180
181 irqreturn_t psurge_primary_intr(int irq, void *d)
182 {
183         psurge_smp_message_recv();
184         return IRQ_HANDLED;
185 }
186
187 static void smp_psurge_message_pass(int target, int msg)
188 {
189         int i;
190
191         if (num_online_cpus() < 2)
192                 return;
193
194         for_each_online_cpu(i) {
195                 if (target == MSG_ALL
196                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
197                     || target == i) {
198                         set_bit(msg, &psurge_smp_message[i]);
199                         psurge_set_ipi(i);
200                 }
201         }
202 }
203
204 /*
205  * Determine a quad card presence. We read the board ID register, we
206  * force the data bus to change to something else, and we read it again.
207  * It it's stable, then the register probably exist (ugh !)
208  */
209 static int __init psurge_quad_probe(void)
210 {
211         int type;
212         unsigned int i;
213
214         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
215         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
216             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
217                 return PSURGE_DUAL;
218
219         /* looks OK, try a slightly more rigorous test */
220         /* bogus is not necessarily cacheline-aligned,
221            though I don't suppose that really matters.  -- paulus */
222         for (i = 0; i < 100; i++) {
223                 volatile u32 bogus[8];
224                 bogus[(0+i)%8] = 0x00000000;
225                 bogus[(1+i)%8] = 0x55555555;
226                 bogus[(2+i)%8] = 0xFFFFFFFF;
227                 bogus[(3+i)%8] = 0xAAAAAAAA;
228                 bogus[(4+i)%8] = 0x33333333;
229                 bogus[(5+i)%8] = 0xCCCCCCCC;
230                 bogus[(6+i)%8] = 0xCCCCCCCC;
231                 bogus[(7+i)%8] = 0x33333333;
232                 wmb();
233                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
234                 mb();
235                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
236                         return PSURGE_DUAL;
237         }
238         return type;
239 }
240
241 static void __init psurge_quad_init(void)
242 {
243         int procbits;
244
245         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
246         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
247         if (psurge_type == PSURGE_QUAD_ICEGRASS)
248                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
249         else
250                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
251         mdelay(33);
252         out_8(psurge_sec_intr, ~0);
253         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
254         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
255         if (psurge_type != PSURGE_QUAD_ICEGRASS)
256                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
257         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
258         mdelay(33);
259         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
260         mdelay(33);
261         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
262         mdelay(33);
263 }
264
265 static int __init smp_psurge_probe(void)
266 {
267         int i, ncpus;
268         struct device_node *dn;
269
270         /* We don't do SMP on the PPC601 -- paulus */
271         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
272                 return 1;
273
274         /*
275          * The powersurge cpu board can be used in the generation
276          * of powermacs that have a socket for an upgradeable cpu card,
277          * including the 7500, 8500, 9500, 9600.
278          * The device tree doesn't tell you if you have 2 cpus because
279          * OF doesn't know anything about the 2nd processor.
280          * Instead we look for magic bits in magic registers,
281          * in the hammerhead memory controller in the case of the
282          * dual-cpu powersurge board.  -- paulus.
283          */
284         dn = of_find_node_by_name(NULL, "hammerhead");
285         if (dn == NULL)
286                 return 1;
287         of_node_put(dn);
288
289         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
290         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
291         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
292
293         psurge_type = psurge_quad_probe();
294         if (psurge_type != PSURGE_DUAL) {
295                 psurge_quad_init();
296                 /* All released cards using this HW design have 4 CPUs */
297                 ncpus = 4;
298                 /* No sure how timebase sync works on those, let's use SW */
299                 smp_ops->give_timebase = smp_generic_give_timebase;
300                 smp_ops->take_timebase = smp_generic_take_timebase;
301         } else {
302                 iounmap(quad_base);
303                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
304                         /* not a dual-cpu card */
305                         iounmap(hhead_base);
306                         psurge_type = PSURGE_NONE;
307                         return 1;
308                 }
309                 ncpus = 2;
310         }
311
312         psurge_start = ioremap(PSURGE_START, 4);
313         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
314
315         /* This is necessary because OF doesn't know about the
316          * secondary cpu(s), and thus there aren't nodes in the
317          * device tree for them, and smp_setup_cpu_maps hasn't
318          * set their bits in cpu_present_map.
319          */
320         if (ncpus > NR_CPUS)
321                 ncpus = NR_CPUS;
322         for (i = 1; i < ncpus ; ++i)
323                 set_cpu_present(i, true);
324
325         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
326
327         return ncpus;
328 }
329
330 static void __init smp_psurge_kick_cpu(int nr)
331 {
332         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
333         unsigned long a, flags;
334         int i, j;
335
336         /* Defining this here is evil ... but I prefer hiding that
337          * crap to avoid giving people ideas that they can do the
338          * same.
339          */
340         extern volatile unsigned int cpu_callin_map[NR_CPUS];
341
342         /* may need to flush here if secondary bats aren't setup */
343         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
344                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
345         asm volatile("sync");
346
347         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
348
349         /* This is going to freeze the timeebase, we disable interrupts */
350         local_irq_save(flags);
351
352         out_be32(psurge_start, start);
353         mb();
354
355         psurge_set_ipi(nr);
356
357         /*
358          * We can't use udelay here because the timebase is now frozen.
359          */
360         for (i = 0; i < 2000; ++i)
361                 asm volatile("nop" : : : "memory");
362         psurge_clr_ipi(nr);
363
364         /*
365          * Also, because the timebase is frozen, we must not return to the
366          * caller which will try to do udelay's etc... Instead, we wait -here-
367          * for the CPU to callin.
368          */
369         for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
370                 for (j = 1; j < 10000; j++)
371                         asm volatile("nop" : : : "memory");
372                 asm volatile("sync" : : : "memory");
373         }
374         if (!cpu_callin_map[nr])
375                 goto stuck;
376
377         /* And we do the TB sync here too for standard dual CPU cards */
378         if (psurge_type == PSURGE_DUAL) {
379                 while(!tb_req)
380                         barrier();
381                 tb_req = 0;
382                 mb();
383                 timebase = get_tb();
384                 mb();
385                 while (timebase)
386                         barrier();
387                 mb();
388         }
389  stuck:
390         /* now interrupt the secondary, restarting both TBs */
391         if (psurge_type == PSURGE_DUAL)
392                 psurge_set_ipi(1);
393
394         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
395 }
396
397 static struct irqaction psurge_irqaction = {
398         .handler = psurge_primary_intr,
399         .flags = IRQF_DISABLED,
400         .name = "primary IPI",
401 };
402
403 static void __init smp_psurge_setup_cpu(int cpu_nr)
404 {
405         if (cpu_nr != 0)
406                 return;
407
408         /* reset the entry point so if we get another intr we won't
409          * try to startup again */
410         out_be32(psurge_start, 0x100);
411         if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
412                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
413 }
414
415 void __init smp_psurge_take_timebase(void)
416 {
417         if (psurge_type != PSURGE_DUAL)
418                 return;
419
420         tb_req = 1;
421         mb();
422         while (!timebase)
423                 barrier();
424         mb();
425         set_tb(timebase >> 32, timebase & 0xffffffff);
426         timebase = 0;
427         mb();
428         set_dec(tb_ticks_per_jiffy/2);
429 }
430
431 void __init smp_psurge_give_timebase(void)
432 {
433         /* Nothing to do here */
434 }
435
436 /* PowerSurge-style Macs */
437 struct smp_ops_t psurge_smp_ops = {
438         .message_pass   = smp_psurge_message_pass,
439         .probe          = smp_psurge_probe,
440         .kick_cpu       = smp_psurge_kick_cpu,
441         .setup_cpu      = smp_psurge_setup_cpu,
442         .give_timebase  = smp_psurge_give_timebase,
443         .take_timebase  = smp_psurge_take_timebase,
444 };
445 #endif /* CONFIG_PPC32 - actually powersurge support */
446
447 /*
448  * Core 99 and later support
449  */
450
451
452 static void smp_core99_give_timebase(void)
453 {
454         unsigned long flags;
455
456         local_irq_save(flags);
457
458         while(!tb_req)
459                 barrier();
460         tb_req = 0;
461         (*pmac_tb_freeze)(1);
462         mb();
463         timebase = get_tb();
464         mb();
465         while (timebase)
466                 barrier();
467         mb();
468         (*pmac_tb_freeze)(0);
469         mb();
470
471         local_irq_restore(flags);
472 }
473
474
475 static void __devinit smp_core99_take_timebase(void)
476 {
477         unsigned long flags;
478
479         local_irq_save(flags);
480
481         tb_req = 1;
482         mb();
483         while (!timebase)
484                 barrier();
485         mb();
486         set_tb(timebase >> 32, timebase & 0xffffffff);
487         timebase = 0;
488         mb();
489
490         local_irq_restore(flags);
491 }
492
493 #ifdef CONFIG_PPC64
494 /*
495  * G5s enable/disable the timebase via an i2c-connected clock chip.
496  */
497 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
498 static u8 pmac_tb_pulsar_addr;
499
500 static void smp_core99_cypress_tb_freeze(int freeze)
501 {
502         u8 data;
503         int rc;
504
505         /* Strangely, the device-tree says address is 0xd2, but darwin
506          * accesses 0xd0 ...
507          */
508         pmac_i2c_setmode(pmac_tb_clock_chip_host,
509                          pmac_i2c_mode_combined);
510         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
511                            0xd0 | pmac_i2c_read,
512                            1, 0x81, &data, 1);
513         if (rc != 0)
514                 goto bail;
515
516         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
517
518         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
519         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
520                            0xd0 | pmac_i2c_write,
521                            1, 0x81, &data, 1);
522
523  bail:
524         if (rc != 0) {
525                 printk("Cypress Timebase %s rc: %d\n",
526                        freeze ? "freeze" : "unfreeze", rc);
527                 panic("Timebase freeze failed !\n");
528         }
529 }
530
531
532 static void smp_core99_pulsar_tb_freeze(int freeze)
533 {
534         u8 data;
535         int rc;
536
537         pmac_i2c_setmode(pmac_tb_clock_chip_host,
538                          pmac_i2c_mode_combined);
539         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
540                            pmac_tb_pulsar_addr | pmac_i2c_read,
541                            1, 0x2e, &data, 1);
542         if (rc != 0)
543                 goto bail;
544
545         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
546
547         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
548         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
549                            pmac_tb_pulsar_addr | pmac_i2c_write,
550                            1, 0x2e, &data, 1);
551  bail:
552         if (rc != 0) {
553                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
554                        freeze ? "freeze" : "unfreeze", rc);
555                 panic("Timebase freeze failed !\n");
556         }
557 }
558
559 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
560 {
561         struct device_node *cc = NULL;  
562         struct device_node *p;
563         const char *name = NULL;
564         const u32 *reg;
565         int ok;
566
567         /* Look for the clock chip */
568         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
569                 p = of_get_parent(cc);
570                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
571                 of_node_put(p);
572                 if (!ok)
573                         continue;
574
575                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
576                 if (pmac_tb_clock_chip_host == NULL)
577                         continue;
578                 reg = of_get_property(cc, "reg", NULL);
579                 if (reg == NULL)
580                         continue;
581                 switch (*reg) {
582                 case 0xd2:
583                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
584                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
585                                 pmac_tb_pulsar_addr = 0xd2;
586                                 name = "Pulsar";
587                         } else if (of_device_is_compatible(cc, "cy28508")) {
588                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
589                                 name = "Cypress";
590                         }
591                         break;
592                 case 0xd4:
593                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
594                         pmac_tb_pulsar_addr = 0xd4;
595                         name = "Pulsar";
596                         break;
597                 }
598                 if (pmac_tb_freeze != NULL)
599                         break;
600         }
601         if (pmac_tb_freeze != NULL) {
602                 /* Open i2c bus for synchronous access */
603                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
604                         printk(KERN_ERR "Failed top open i2c bus for clock"
605                                " sync, fallback to software sync !\n");
606                         goto no_i2c_sync;
607                 }
608                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
609                        name);
610                 return;
611         }
612  no_i2c_sync:
613         pmac_tb_freeze = NULL;
614         pmac_tb_clock_chip_host = NULL;
615 }
616
617
618
619 /*
620  * Newer G5s uses a platform function
621  */
622
623 static void smp_core99_pfunc_tb_freeze(int freeze)
624 {
625         struct device_node *cpus;
626         struct pmf_args args;
627
628         cpus = of_find_node_by_path("/cpus");
629         BUG_ON(cpus == NULL);
630         args.count = 1;
631         args.u[0].v = !freeze;
632         pmf_call_function(cpus, "cpu-timebase", &args);
633         of_node_put(cpus);
634 }
635
636 #else /* CONFIG_PPC64 */
637
638 /*
639  * SMP G4 use a GPIO to enable/disable the timebase.
640  */
641
642 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
643
644 static void smp_core99_gpio_tb_freeze(int freeze)
645 {
646         if (freeze)
647                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
648         else
649                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
650         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
651 }
652
653
654 #endif /* !CONFIG_PPC64 */
655
656 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
657 volatile static long int core99_l2_cache;
658 volatile static long int core99_l3_cache;
659
660 static void __devinit core99_init_caches(int cpu)
661 {
662 #ifndef CONFIG_PPC64
663         if (!cpu_has_feature(CPU_FTR_L2CR))
664                 return;
665
666         if (cpu == 0) {
667                 core99_l2_cache = _get_L2CR();
668                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
669         } else {
670                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
671                 _set_L2CR(0);
672                 _set_L2CR(core99_l2_cache);
673                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
674         }
675
676         if (!cpu_has_feature(CPU_FTR_L3CR))
677                 return;
678
679         if (cpu == 0){
680                 core99_l3_cache = _get_L3CR();
681                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
682         } else {
683                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
684                 _set_L3CR(0);
685                 _set_L3CR(core99_l3_cache);
686                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
687         }
688 #endif /* !CONFIG_PPC64 */
689 }
690
691 static void __init smp_core99_setup(int ncpus)
692 {
693 #ifdef CONFIG_PPC64
694
695         /* i2c based HW sync on some G5s */
696         if (of_machine_is_compatible("PowerMac7,2") ||
697             of_machine_is_compatible("PowerMac7,3") ||
698             of_machine_is_compatible("RackMac3,1"))
699                 smp_core99_setup_i2c_hwsync(ncpus);
700
701         /* pfunc based HW sync on recent G5s */
702         if (pmac_tb_freeze == NULL) {
703                 struct device_node *cpus =
704                         of_find_node_by_path("/cpus");
705                 if (cpus &&
706                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
707                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
708                         printk(KERN_INFO "Processor timebase sync using"
709                                " platform function\n");
710                 }
711         }
712
713 #else /* CONFIG_PPC64 */
714
715         /* GPIO based HW sync on ppc32 Core99 */
716         if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
717                 struct device_node *cpu;
718                 const u32 *tbprop = NULL;
719
720                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
721                 cpu = of_find_node_by_type(NULL, "cpu");
722                 if (cpu != NULL) {
723                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
724                         if (tbprop)
725                                 core99_tb_gpio = *tbprop;
726                         of_node_put(cpu);
727                 }
728                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
729                 printk(KERN_INFO "Processor timebase sync using"
730                        " GPIO 0x%02x\n", core99_tb_gpio);
731         }
732
733 #endif /* CONFIG_PPC64 */
734
735         /* No timebase sync, fallback to software */
736         if (pmac_tb_freeze == NULL) {
737                 smp_ops->give_timebase = smp_generic_give_timebase;
738                 smp_ops->take_timebase = smp_generic_take_timebase;
739                 printk(KERN_INFO "Processor timebase sync using software\n");
740         }
741
742 #ifndef CONFIG_PPC64
743         {
744                 int i;
745
746                 /* XXX should get this from reg properties */
747                 for (i = 1; i < ncpus; ++i)
748                         set_hard_smp_processor_id(i, i);
749         }
750 #endif
751
752         /* 32 bits SMP can't NAP */
753         if (!of_machine_is_compatible("MacRISC4"))
754                 powersave_nap = 0;
755 }
756
757 static int __init smp_core99_probe(void)
758 {
759         struct device_node *cpus;
760         int ncpus = 0;
761
762         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
763
764         /* Count CPUs in the device-tree */
765         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
766                 ++ncpus;
767
768         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
769
770         /* Nothing more to do if less than 2 of them */
771         if (ncpus <= 1)
772                 return 1;
773
774         /* We need to perform some early initialisations before we can start
775          * setting up SMP as we are running before initcalls
776          */
777         pmac_pfunc_base_install();
778         pmac_i2c_init();
779
780         /* Setup various bits like timebase sync method, ability to nap, ... */
781         smp_core99_setup(ncpus);
782
783         /* Install IPIs */
784         mpic_request_ipis();
785
786         /* Collect l2cr and l3cr values from CPU 0 */
787         core99_init_caches(0);
788
789         return ncpus;
790 }
791
792 static void __devinit smp_core99_kick_cpu(int nr)
793 {
794         unsigned int save_vector;
795         unsigned long target, flags;
796         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
797
798         if (nr < 0 || nr > 3)
799                 return;
800
801         if (ppc_md.progress)
802                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
803
804         local_irq_save(flags);
805
806         /* Save reset vector */
807         save_vector = *vector;
808
809         /* Setup fake reset vector that does
810          *   b __secondary_start_pmac_0 + nr*8
811          */
812         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
813         patch_branch(vector, target, BRANCH_SET_LINK);
814
815         /* Put some life in our friend */
816         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
817
818         /* FIXME: We wait a bit for the CPU to take the exception, I should
819          * instead wait for the entry code to set something for me. Well,
820          * ideally, all that crap will be done in prom.c and the CPU left
821          * in a RAM-based wait loop like CHRP.
822          */
823         mdelay(1);
824
825         /* Restore our exception vector */
826         *vector = save_vector;
827         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
828
829         local_irq_restore(flags);
830         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
831 }
832
833 static void __devinit smp_core99_setup_cpu(int cpu_nr)
834 {
835         /* Setup L2/L3 */
836         if (cpu_nr != 0)
837                 core99_init_caches(cpu_nr);
838
839         /* Setup openpic */
840         mpic_setup_this_cpu();
841
842         if (cpu_nr == 0) {
843 #ifdef CONFIG_PPC64
844                 extern void g5_phy_disable_cpu1(void);
845
846                 /* Close i2c bus if it was used for tb sync */
847                 if (pmac_tb_clock_chip_host) {
848                         pmac_i2c_close(pmac_tb_clock_chip_host);
849                         pmac_tb_clock_chip_host = NULL;
850                 }
851
852                 /* If we didn't start the second CPU, we must take
853                  * it off the bus
854                  */
855                 if (of_machine_is_compatible("MacRISC4") &&
856                     num_online_cpus() < 2)              
857                         g5_phy_disable_cpu1();
858 #endif /* CONFIG_PPC64 */
859
860                 if (ppc_md.progress)
861                         ppc_md.progress("core99_setup_cpu 0 done", 0x349);
862         }
863 }
864
865
866 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
867
868 int smp_core99_cpu_disable(void)
869 {
870         set_cpu_online(smp_processor_id(), false);
871
872         /* XXX reset cpu affinity here */
873         mpic_cpu_set_priority(0xf);
874         asm volatile("mtdec %0" : : "r" (0x7fffffff));
875         mb();
876         udelay(20);
877         asm volatile("mtdec %0" : : "r" (0x7fffffff));
878         return 0;
879 }
880
881 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
882 static int cpu_dead[NR_CPUS];
883
884 void cpu_die(void)
885 {
886         local_irq_disable();
887         cpu_dead[smp_processor_id()] = 1;
888         mb();
889         low_cpu_die();
890 }
891
892 void smp_core99_cpu_die(unsigned int cpu)
893 {
894         int timeout;
895
896         timeout = 1000;
897         while (!cpu_dead[cpu]) {
898                 if (--timeout == 0) {
899                         printk("CPU %u refused to die!\n", cpu);
900                         break;
901                 }
902                 msleep(1);
903         }
904         cpu_dead[cpu] = 0;
905 }
906
907 #endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */
908
909 /* Core99 Macs (dual G4s and G5s) */
910 struct smp_ops_t core99_smp_ops = {
911         .message_pass   = smp_mpic_message_pass,
912         .probe          = smp_core99_probe,
913         .kick_cpu       = smp_core99_kick_cpu,
914         .setup_cpu      = smp_core99_setup_cpu,
915         .give_timebase  = smp_core99_give_timebase,
916         .take_timebase  = smp_core99_take_timebase,
917 #if defined(CONFIG_HOTPLUG_CPU)
918 # if defined(CONFIG_PPC32)
919         .cpu_disable    = smp_core99_cpu_disable,
920         .cpu_die        = smp_core99_cpu_die,
921 # endif
922 # if defined(CONFIG_PPC64)
923         .cpu_disable    = generic_cpu_disable,
924         .cpu_die        = generic_cpu_die,
925         /* intentionally do *NOT* assign cpu_enable,
926          * the generic code will use kick_cpu then! */
927 # endif
928 #endif
929 };
930
931 void __init pmac_setup_smp(void)
932 {
933         struct device_node *np;
934
935         /* Check for Core99 */
936         np = of_find_node_by_name(NULL, "uni-n");
937         if (!np)
938                 np = of_find_node_by_name(NULL, "u3");
939         if (!np)
940                 np = of_find_node_by_name(NULL, "u4");
941         if (np) {
942                 of_node_put(np);
943                 smp_ops = &core99_smp_ops;
944         }
945 #ifdef CONFIG_PPC32
946         else {
947                 /* We have to set bits in cpu_possible_map here since the
948                  * secondary CPU(s) aren't in the device tree. Various
949                  * things won't be initialized for CPUs not in the possible
950                  * map, so we really need to fix it up here.
951                  */
952                 int cpu;
953
954                 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
955                         set_cpu_possible(cpu, true);
956                 smp_ops = &psurge_smp_ops;
957         }
958 #endif /* CONFIG_PPC32 */
959 }
960