[POWERPC] Split out iSeries specific exception macros
[linux-2.6.git] / arch / powerpc / platforms / iseries / exception.S
1 /*
2  *  Low level routines for legacy iSeries support.
3  *
4  *  Extracted from head_64.S
5  *
6  *  PowerPC version
7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8  *
9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11  *  Adapted for Power Macintosh by Paul Mackerras.
12  *  Low-level exception handlers and MMU support
13  *  rewritten by Paul Mackerras.
14  *    Copyright (C) 1996 Paul Mackerras.
15  *
16  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18  *
19  *  This file contains the low-level support and setup for the
20  *  PowerPC-64 platform, including trap and interrupt dispatch.
21  *
22  *  This program is free software; you can redistribute it and/or
23  *  modify it under the terms of the GNU General Public License
24  *  as published by the Free Software Foundation; either version
25  *  2 of the License, or (at your option) any later version.
26  */
27
28 #include <asm/reg.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/thread_info.h>
32 #include <asm/ptrace.h>
33 #include <asm/cputable.h>
34
35 #include "exception.h"
36
37         .text
38
39         .globl system_reset_iSeries
40 system_reset_iSeries:
41         mfspr   r13,SPRN_SPRG3          /* Get paca address */
42         mfmsr   r24
43         ori     r24,r24,MSR_RI
44         mtmsrd  r24                     /* RI on */
45         lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
46         cmpwi   0,r24,0                 /* Are we processor 0? */
47         bne     1f
48         b       .__start_initialization_iSeries /* Start up the first processor */
49 1:      mfspr   r4,SPRN_CTRLF
50         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
51         andc    r4,r4,r5
52         mtspr   SPRN_CTRLT,r4
53
54 1:
55         HMT_LOW
56 #ifdef CONFIG_SMP
57         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
58                                          * should start */
59         sync
60         LOAD_REG_IMMEDIATE(r3,current_set)
61         sldi    r28,r24,3               /* get current_set[cpu#] */
62         ldx     r3,r3,r28
63         addi    r1,r3,THREAD_SIZE
64         subi    r1,r1,STACK_FRAME_OVERHEAD
65
66         cmpwi   0,r23,0
67         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
68         b       __secondary_start               /* Loop until told to go */
69 iSeries_secondary_smp_loop:
70         /* Let the Hypervisor know we are alive */
71         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
72         lis     r3,0x8002
73         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
74 #else /* CONFIG_SMP */
75         /* Yield the processor.  This is required for non-SMP kernels
76                 which are running on multi-threaded machines. */
77         lis     r3,0x8000
78         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
79         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
80         li      r4,0                    /* "yield timed" */
81         li      r5,-1                   /* "yield forever" */
82 #endif /* CONFIG_SMP */
83         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
84         sc                              /* Invoke the hypervisor via a system call */
85         mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
86         b       1b                      /* If SMP not configured, secondaries
87                                          * loop forever */
88
89 /***  ISeries-LPAR interrupt handlers ***/
90
91         STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
92
93         .globl data_access_iSeries
94 data_access_iSeries:
95         mtspr   SPRN_SPRG1,r13
96 BEGIN_FTR_SECTION
97         mtspr   SPRN_SPRG2,r12
98         mfspr   r13,SPRN_DAR
99         mfspr   r12,SPRN_DSISR
100         srdi    r13,r13,60
101         rlwimi  r13,r12,16,0x20
102         mfcr    r12
103         cmpwi   r13,0x2c
104         beq     .do_stab_bolted_iSeries
105         mtcrf   0x80,r12
106         mfspr   r12,SPRN_SPRG2
107 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
108         EXCEPTION_PROLOG_1(PACA_EXGEN)
109         EXCEPTION_PROLOG_ISERIES_1
110         b       data_access_common
111
112 .do_stab_bolted_iSeries:
113         mtcrf   0x80,r12
114         mfspr   r12,SPRN_SPRG2
115         EXCEPTION_PROLOG_1(PACA_EXSLB)
116         EXCEPTION_PROLOG_ISERIES_1
117         b       .do_stab_bolted
118
119         .globl  data_access_slb_iSeries
120 data_access_slb_iSeries:
121         mtspr   SPRN_SPRG1,r13          /* save r13 */
122         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
123         std     r3,PACA_EXSLB+EX_R3(r13)
124         mfspr   r3,SPRN_DAR
125         std     r9,PACA_EXSLB+EX_R9(r13)
126         mfcr    r9
127 #ifdef __DISABLED__
128         cmpdi   r3,0
129         bge     slb_miss_user_iseries
130 #endif
131         std     r10,PACA_EXSLB+EX_R10(r13)
132         std     r11,PACA_EXSLB+EX_R11(r13)
133         std     r12,PACA_EXSLB+EX_R12(r13)
134         mfspr   r10,SPRN_SPRG1
135         std     r10,PACA_EXSLB+EX_R13(r13)
136         ld      r12,PACALPPACAPTR(r13)
137         ld      r12,LPPACASRR1(r12)
138         b       .slb_miss_realmode
139
140         STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
141
142         .globl  instruction_access_slb_iSeries
143 instruction_access_slb_iSeries:
144         mtspr   SPRN_SPRG1,r13          /* save r13 */
145         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
146         std     r3,PACA_EXSLB+EX_R3(r13)
147         ld      r3,PACALPPACAPTR(r13)
148         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
149         std     r9,PACA_EXSLB+EX_R9(r13)
150         mfcr    r9
151 #ifdef __DISABLED__
152         cmpdi   r3,0
153         bge     slb_miss_user_iseries
154 #endif
155         std     r10,PACA_EXSLB+EX_R10(r13)
156         std     r11,PACA_EXSLB+EX_R11(r13)
157         std     r12,PACA_EXSLB+EX_R12(r13)
158         mfspr   r10,SPRN_SPRG1
159         std     r10,PACA_EXSLB+EX_R13(r13)
160         ld      r12,PACALPPACAPTR(r13)
161         ld      r12,LPPACASRR1(r12)
162         b       .slb_miss_realmode
163
164 #ifdef __DISABLED__
165 slb_miss_user_iseries:
166         std     r10,PACA_EXGEN+EX_R10(r13)
167         std     r11,PACA_EXGEN+EX_R11(r13)
168         std     r12,PACA_EXGEN+EX_R12(r13)
169         mfspr   r10,SPRG1
170         ld      r11,PACA_EXSLB+EX_R9(r13)
171         ld      r12,PACA_EXSLB+EX_R3(r13)
172         std     r10,PACA_EXGEN+EX_R13(r13)
173         std     r11,PACA_EXGEN+EX_R9(r13)
174         std     r12,PACA_EXGEN+EX_R3(r13)
175         EXCEPTION_PROLOG_ISERIES_1
176         b       slb_miss_user_common
177 #endif
178
179         MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
180         STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
181         STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
182         STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
183         MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
184         STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
185         STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
186
187         .globl  system_call_iSeries
188 system_call_iSeries:
189         mr      r9,r13
190         mfspr   r13,SPRN_SPRG3
191         EXCEPTION_PROLOG_ISERIES_1
192         b       system_call_common
193
194         STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
195         STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
196         STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
197
198 decrementer_iSeries_masked:
199         /* We may not have a valid TOC pointer in here. */
200         li      r11,1
201         ld      r12,PACALPPACAPTR(r13)
202         stb     r11,LPPACADECRINT(r12)
203         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
204         lwz     r12,0(r12)
205         mtspr   SPRN_DEC,r12
206         /* fall through */
207
208 hardware_interrupt_iSeries_masked:
209         mtcrf   0x80,r9         /* Restore regs */
210         ld      r12,PACALPPACAPTR(r13)
211         ld      r11,LPPACASRR0(r12)
212         ld      r12,LPPACASRR1(r12)
213         mtspr   SPRN_SRR0,r11
214         mtspr   SPRN_SRR1,r12
215         ld      r9,PACA_EXGEN+EX_R9(r13)
216         ld      r10,PACA_EXGEN+EX_R10(r13)
217         ld      r11,PACA_EXGEN+EX_R11(r13)
218         ld      r12,PACA_EXGEN+EX_R12(r13)
219         ld      r13,PACA_EXGEN+EX_R13(r13)
220         rfid
221         b       .       /* prevent speculative execution */
222
223 _INIT_STATIC(__start_initialization_iSeries)
224         /* Clear out the BSS */
225         LOAD_REG_IMMEDIATE(r11,__bss_stop)
226         LOAD_REG_IMMEDIATE(r8,__bss_start)
227         sub     r11,r11,r8              /* bss size                     */
228         addi    r11,r11,7               /* round up to an even double word */
229         rldicl. r11,r11,61,3            /* shift right by 3             */
230         beq     4f
231         addi    r8,r8,-8
232         li      r0,0
233         mtctr   r11                     /* zero this many doublewords   */
234 3:      stdu    r0,8(r8)
235         bdnz    3b
236 4:
237         LOAD_REG_IMMEDIATE(r1,init_thread_union)
238         addi    r1,r1,THREAD_SIZE
239         li      r0,0
240         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
241
242         LOAD_REG_IMMEDIATE(r2,__toc_start)
243         addi    r2,r2,0x4000
244         addi    r2,r2,0x4000
245
246         bl      .iSeries_early_setup
247         bl      .early_setup
248
249         /* relocation is on at this point */
250
251         b       .start_here_common