[POWERPC] cell: handle SPE kernel mappings that cross segment boundaries
[linux-2.6.git] / arch / powerpc / platforms / cell / spufs / switch.c
1 /*
2  * spu_switch.c
3  *
4  * (C) Copyright IBM Corp. 2005
5  *
6  * Author: Mark Nutter <mnutter@us.ibm.com>
7  *
8  * Host-side part of SPU context switch sequence outlined in
9  * Synergistic Processor Element, Book IV.
10  *
11  * A fully premptive switch of an SPE is very expensive in terms
12  * of time and system resources.  SPE Book IV indicates that SPE
13  * allocation should follow a "serially reusable device" model,
14  * in which the SPE is assigned a task until it completes.  When
15  * this is not possible, this sequence may be used to premptively
16  * save, and then later (optionally) restore the context of a
17  * program executing on an SPE.
18  *
19  *
20  * This program is free software; you can redistribute it and/or modify
21  * it under the terms of the GNU General Public License as published by
22  * the Free Software Foundation; either version 2, or (at your option)
23  * any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28  * GNU General Public License for more details.
29  *
30  * You should have received a copy of the GNU General Public License
31  * along with this program; if not, write to the Free Software
32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33  */
34
35 #include <linux/module.h>
36 #include <linux/errno.h>
37 #include <linux/sched.h>
38 #include <linux/kernel.h>
39 #include <linux/mm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/smp.h>
42 #include <linux/stddef.h>
43 #include <linux/unistd.h>
44
45 #include <asm/io.h>
46 #include <asm/spu.h>
47 #include <asm/spu_priv1.h>
48 #include <asm/spu_csa.h>
49 #include <asm/mmu_context.h>
50
51 #include "spu_save_dump.h"
52 #include "spu_restore_dump.h"
53
54 #if 0
55 #define POLL_WHILE_TRUE(_c) {                           \
56     do {                                                \
57     } while (_c);                                       \
58   }
59 #else
60 #define RELAX_SPIN_COUNT                                1000
61 #define POLL_WHILE_TRUE(_c) {                           \
62     do {                                                \
63         int _i;                                         \
64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
65             cpu_relax();                                \
66         }                                               \
67         if (unlikely(_c)) yield();                      \
68         else break;                                     \
69     } while (_c);                                       \
70   }
71 #endif                          /* debug */
72
73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
74
75 static inline void acquire_spu_lock(struct spu *spu)
76 {
77         /* Save, Step 1:
78          * Restore, Step 1:
79          *    Acquire SPU-specific mutual exclusion lock.
80          *    TBD.
81          */
82 }
83
84 static inline void release_spu_lock(struct spu *spu)
85 {
86         /* Restore, Step 76:
87          *    Release SPU-specific mutual exclusion lock.
88          *    TBD.
89          */
90 }
91
92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
93 {
94         struct spu_problem __iomem *prob = spu->problem;
95         u32 isolate_state;
96
97         /* Save, Step 2:
98          * Save, Step 6:
99          *     If SPU_Status[E,L,IS] any field is '1', this
100          *     SPU is in isolate state and cannot be context
101          *     saved at this time.
102          */
103         isolate_state = SPU_STATUS_ISOLATED_STATE |
104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
106 }
107
108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
109 {
110         /* Save, Step 3:
111          * Restore, Step 2:
112          *     Save INT_Mask_class0 in CSA.
113          *     Write INT_MASK_class0 with value of 0.
114          *     Save INT_Mask_class1 in CSA.
115          *     Write INT_MASK_class1 with value of 0.
116          *     Save INT_Mask_class2 in CSA.
117          *     Write INT_MASK_class2 with value of 0.
118          */
119         spin_lock_irq(&spu->register_lock);
120         if (csa) {
121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
124         }
125         spu_int_mask_set(spu, 0, 0ul);
126         spu_int_mask_set(spu, 1, 0ul);
127         spu_int_mask_set(spu, 2, 0ul);
128         eieio();
129         spin_unlock_irq(&spu->register_lock);
130 }
131
132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
133 {
134         /* Save, Step 4:
135          * Restore, Step 25.
136          *    Set a software watchdog timer, which specifies the
137          *    maximum allowable time for a context save sequence.
138          *
139          *    For present, this implementation will not set a global
140          *    watchdog timer, as virtualization & variable system load
141          *    may cause unpredictable execution times.
142          */
143 }
144
145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
146 {
147         /* Save, Step 5:
148          * Restore, Step 3:
149          *     Inhibit user-space access (if provided) to this
150          *     SPU by unmapping the virtual pages assigned to
151          *     the SPU memory-mapped I/O (MMIO) for problem
152          *     state. TBD.
153          */
154 }
155
156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
157 {
158         /* Save, Step 7:
159          * Restore, Step 5:
160          *     Set a software context switch pending flag.
161          */
162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
163         mb();
164 }
165
166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
167 {
168         struct spu_priv2 __iomem *priv2 = spu->priv2;
169
170         /* Save, Step 8:
171          *     Suspend DMA and save MFC_CNTL.
172          */
173         switch (in_be64(&priv2->mfc_control_RW) &
174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
178                                  MFC_CNTL_SUSPEND_COMPLETE);
179                 /* fall through */
180         case MFC_CNTL_SUSPEND_COMPLETE:
181                 if (csa) {
182                         csa->priv2.mfc_control_RW =
183                                 MFC_CNTL_SUSPEND_MASK |
184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
185                 }
186                 break;
187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
191                                  MFC_CNTL_SUSPEND_COMPLETE);
192                 if (csa) {
193                         csa->priv2.mfc_control_RW = 0;
194                 }
195                 break;
196         }
197 }
198
199 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
200 {
201         struct spu_problem __iomem *prob = spu->problem;
202
203         /* Save, Step 9:
204          *     Save SPU_Runcntl in the CSA.  This value contains
205          *     the "Application Desired State".
206          */
207         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
208 }
209
210 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
211 {
212         /* Save, Step 10:
213          *     Save MFC_SR1 in the CSA.
214          */
215         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
216 }
217
218 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
219 {
220         struct spu_problem __iomem *prob = spu->problem;
221
222         /* Save, Step 11:
223          *     Read SPU_Status[R], and save to CSA.
224          */
225         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
226                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
227         } else {
228                 u32 stopped;
229
230                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
231                 eieio();
232                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
233                                 SPU_STATUS_RUNNING);
234                 stopped =
235                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
236                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
237                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
238                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
239                 else
240                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
241         }
242 }
243
244 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
245 {
246         struct spu_priv2 __iomem *priv2 = spu->priv2;
247
248         /* Save, Step 12:
249          *     Read MFC_CNTL[Ds].  Update saved copy of
250          *     CSA.MFC_CNTL[Ds].
251          */
252         csa->priv2.mfc_control_RW |=
253                 in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING;
254 }
255
256 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
257 {
258         struct spu_priv2 __iomem *priv2 = spu->priv2;
259
260         /* Save, Step 13:
261          *     Write MFC_CNTL[Dh] set to a '1' to halt
262          *     the decrementer.
263          */
264         out_be64(&priv2->mfc_control_RW,
265                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
266         eieio();
267 }
268
269 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
270 {
271         /* Save, Step 14:
272          *    Read PPE Timebase High and Timebase low registers
273          *    and save in CSA.  TBD.
274          */
275         csa->suspend_time = get_cycles();
276 }
277
278 static inline void remove_other_spu_access(struct spu_state *csa,
279                                            struct spu *spu)
280 {
281         /* Save, Step 15:
282          *     Remove other SPU access to this SPU by unmapping
283          *     this SPU's pages from their address space.  TBD.
284          */
285 }
286
287 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
288 {
289         struct spu_problem __iomem *prob = spu->problem;
290
291         /* Save, Step 16:
292          * Restore, Step 11.
293          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
294          *     for a value of 0.
295          */
296         out_be64(&prob->spc_mssync_RW, 1UL);
297         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
298 }
299
300 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
301 {
302         /* Save, Step 17:
303          * Restore, Step 12.
304          * Restore, Step 48.
305          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
306          *     Then issue a PPE sync instruction.
307          */
308         spu_tlb_invalidate(spu);
309         mb();
310 }
311
312 static inline void handle_pending_interrupts(struct spu_state *csa,
313                                              struct spu *spu)
314 {
315         /* Save, Step 18:
316          *     Handle any pending interrupts from this SPU
317          *     here.  This is OS or hypervisor specific.  One
318          *     option is to re-enable interrupts to handle any
319          *     pending interrupts, with the interrupt handlers
320          *     recognizing the software Context Switch Pending
321          *     flag, to ensure the SPU execution or MFC command
322          *     queue is not restarted.  TBD.
323          */
324 }
325
326 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
327 {
328         struct spu_priv2 __iomem *priv2 = spu->priv2;
329         int i;
330
331         /* Save, Step 19:
332          *     If MFC_Cntl[Se]=0 then save
333          *     MFC command queues.
334          */
335         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
336                 for (i = 0; i < 8; i++) {
337                         csa->priv2.puq[i].mfc_cq_data0_RW =
338                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
339                         csa->priv2.puq[i].mfc_cq_data1_RW =
340                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
341                         csa->priv2.puq[i].mfc_cq_data2_RW =
342                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
343                         csa->priv2.puq[i].mfc_cq_data3_RW =
344                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
345                 }
346                 for (i = 0; i < 16; i++) {
347                         csa->priv2.spuq[i].mfc_cq_data0_RW =
348                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
349                         csa->priv2.spuq[i].mfc_cq_data1_RW =
350                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
351                         csa->priv2.spuq[i].mfc_cq_data2_RW =
352                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
353                         csa->priv2.spuq[i].mfc_cq_data3_RW =
354                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
355                 }
356         }
357 }
358
359 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
360 {
361         struct spu_problem __iomem *prob = spu->problem;
362
363         /* Save, Step 20:
364          *     Save the PPU_QueryMask register
365          *     in the CSA.
366          */
367         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
368 }
369
370 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
371 {
372         struct spu_problem __iomem *prob = spu->problem;
373
374         /* Save, Step 21:
375          *     Save the PPU_QueryType register
376          *     in the CSA.
377          */
378         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
379 }
380
381 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
382 {
383         struct spu_problem __iomem *prob = spu->problem;
384
385         /* Save the Prxy_TagStatus register in the CSA.
386          *
387          * It is unnecessary to restore dma_tagstatus_R, however,
388          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
389          * we must save it.
390          */
391         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
392 }
393
394 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
395 {
396         struct spu_priv2 __iomem *priv2 = spu->priv2;
397
398         /* Save, Step 22:
399          *     Save the MFC_CSR_TSQ register
400          *     in the LSCSA.
401          */
402         csa->priv2.spu_tag_status_query_RW =
403             in_be64(&priv2->spu_tag_status_query_RW);
404 }
405
406 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
407 {
408         struct spu_priv2 __iomem *priv2 = spu->priv2;
409
410         /* Save, Step 23:
411          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
412          *     registers in the CSA.
413          */
414         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
415         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
416 }
417
418 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
419 {
420         struct spu_priv2 __iomem *priv2 = spu->priv2;
421
422         /* Save, Step 24:
423          *     Save the MFC_CSR_ATO register in
424          *     the CSA.
425          */
426         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
427 }
428
429 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
430 {
431         /* Save, Step 25:
432          *     Save the MFC_TCLASS_ID register in
433          *     the CSA.
434          */
435         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
436 }
437
438 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
439 {
440         /* Save, Step 26:
441          * Restore, Step 23.
442          *     Write the MFC_TCLASS_ID register with
443          *     the value 0x10000000.
444          */
445         spu_mfc_tclass_id_set(spu, 0x10000000);
446         eieio();
447 }
448
449 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
450 {
451         struct spu_priv2 __iomem *priv2 = spu->priv2;
452
453         /* Save, Step 27:
454          * Restore, Step 14.
455          *     Write MFC_CNTL[Pc]=1 (purge queue).
456          */
457         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
458         eieio();
459 }
460
461 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
462 {
463         struct spu_priv2 __iomem *priv2 = spu->priv2;
464
465         /* Save, Step 28:
466          *     Poll MFC_CNTL[Ps] until value '11' is read
467          *     (purge complete).
468          */
469         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
470                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
471                          MFC_CNTL_PURGE_DMA_COMPLETE);
472 }
473
474 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
475 {
476         /* Save, Step 30:
477          * Restore, Step 18:
478          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
479          *     MFC_SR1[TL,R,Pr,T] set correctly for the
480          *     OS specific environment.
481          *
482          *     Implementation note: The SPU-side code
483          *     for save/restore is privileged, so the
484          *     MFC_SR1[Pr] bit is not set.
485          *
486          */
487         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
488                               MFC_STATE1_RELOCATE_MASK |
489                               MFC_STATE1_BUS_TLBIE_MASK));
490 }
491
492 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
493 {
494         struct spu_problem __iomem *prob = spu->problem;
495
496         /* Save, Step 31:
497          *     Save SPU_NPC in the CSA.
498          */
499         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
500 }
501
502 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
503 {
504         struct spu_priv2 __iomem *priv2 = spu->priv2;
505
506         /* Save, Step 32:
507          *     Save SPU_PrivCntl in the CSA.
508          */
509         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
510 }
511
512 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
513 {
514         struct spu_priv2 __iomem *priv2 = spu->priv2;
515
516         /* Save, Step 33:
517          * Restore, Step 16:
518          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
519          */
520         out_be64(&priv2->spu_privcntl_RW, 0UL);
521         eieio();
522 }
523
524 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
525 {
526         struct spu_priv2 __iomem *priv2 = spu->priv2;
527
528         /* Save, Step 34:
529          *     Save SPU_LSLR in the CSA.
530          */
531         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
532 }
533
534 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
535 {
536         struct spu_priv2 __iomem *priv2 = spu->priv2;
537
538         /* Save, Step 35:
539          * Restore, Step 17.
540          *     Reset SPU_LSLR.
541          */
542         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
543         eieio();
544 }
545
546 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
547 {
548         struct spu_priv2 __iomem *priv2 = spu->priv2;
549
550         /* Save, Step 36:
551          *     Save SPU_Cfg in the CSA.
552          */
553         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
554 }
555
556 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
557 {
558         /* Save, Step 37:
559          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
560          *     Not performed by this implementation.
561          */
562 }
563
564 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
565 {
566         /* Save, Step 38:
567          *     Save RA_GROUP_ID register and the
568          *     RA_ENABLE reigster in the CSA.
569          */
570         csa->priv1.resource_allocation_groupID_RW =
571                 spu_resource_allocation_groupID_get(spu);
572         csa->priv1.resource_allocation_enable_RW =
573                 spu_resource_allocation_enable_get(spu);
574 }
575
576 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
577 {
578         struct spu_problem __iomem *prob = spu->problem;
579
580         /* Save, Step 39:
581          *     Save MB_Stat register in the CSA.
582          */
583         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
584 }
585
586 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
587 {
588         struct spu_problem __iomem *prob = spu->problem;
589
590         /* Save, Step 40:
591          *     Save the PPU_MB register in the CSA.
592          */
593         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
594 }
595
596 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
597 {
598         struct spu_priv2 __iomem *priv2 = spu->priv2;
599
600         /* Save, Step 41:
601          *     Save the PPUINT_MB register in the CSA.
602          */
603         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
604 }
605
606 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
607 {
608         struct spu_priv2 __iomem *priv2 = spu->priv2;
609         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
610         int i;
611
612         /* Save, Step 42:
613          */
614
615         /* Save CH 1, without channel count */
616         out_be64(&priv2->spu_chnlcntptr_RW, 1);
617         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
618
619         /* Save the following CH: [0,3,4,24,25,27] */
620         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
621                 idx = ch_indices[i];
622                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
623                 eieio();
624                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
625                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
626                 out_be64(&priv2->spu_chnldata_RW, 0UL);
627                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
628                 eieio();
629         }
630 }
631
632 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
633 {
634         struct spu_priv2 __iomem *priv2 = spu->priv2;
635         int i;
636
637         /* Save, Step 43:
638          *     Save SPU Read Mailbox Channel.
639          */
640         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
641         eieio();
642         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
643         for (i = 0; i < 4; i++) {
644                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
645         }
646         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
647         eieio();
648 }
649
650 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
651 {
652         struct spu_priv2 __iomem *priv2 = spu->priv2;
653
654         /* Save, Step 44:
655          *     Save MFC_CMD Channel.
656          */
657         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
658         eieio();
659         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
660         eieio();
661 }
662
663 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
664 {
665         struct spu_priv2 __iomem *priv2 = spu->priv2;
666         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
667         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
668         u64 idx;
669         int i;
670
671         /* Save, Step 45:
672          *     Reset the following CH: [21, 23, 28, 30]
673          */
674         for (i = 0; i < 4; i++) {
675                 idx = ch_indices[i];
676                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
677                 eieio();
678                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
679                 eieio();
680         }
681 }
682
683 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
684 {
685         struct spu_priv2 __iomem *priv2 = spu->priv2;
686
687         /* Save, Step 46:
688          * Restore, Step 25.
689          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
690          */
691         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
692 }
693
694 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
695                 unsigned int *code, int code_size)
696 {
697         /* Save, Step 47:
698          * Restore, Step 30.
699          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
700          *     register, then initialize SLB_VSID and SLB_ESID
701          *     to provide access to SPU context save code and
702          *     LSCSA.
703          *
704          *     This implementation places both the context
705          *     switch code and LSCSA in kernel address space.
706          *
707          *     Further this implementation assumes that the
708          *     MFC_SR1[R]=1 (in other words, assume that
709          *     translation is desired by OS environment).
710          */
711         spu_invalidate_slbs(spu);
712         spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
713 }
714
715 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
716 {
717         /* Save, Step 48:
718          * Restore, Step 23.
719          *     Change the software context switch pending flag
720          *     to context switch active.
721          */
722         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
723         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
724         mb();
725 }
726
727 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
728 {
729         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
730             CLASS1_ENABLE_STORAGE_FAULT_INTR;
731
732         /* Save, Step 49:
733          * Restore, Step 22:
734          *     Reset and then enable interrupts, as
735          *     needed by OS.
736          *
737          *     This implementation enables only class1
738          *     (translation) interrupts.
739          */
740         spin_lock_irq(&spu->register_lock);
741         spu_int_stat_clear(spu, 0, ~0ul);
742         spu_int_stat_clear(spu, 1, ~0ul);
743         spu_int_stat_clear(spu, 2, ~0ul);
744         spu_int_mask_set(spu, 0, 0ul);
745         spu_int_mask_set(spu, 1, class1_mask);
746         spu_int_mask_set(spu, 2, 0ul);
747         spin_unlock_irq(&spu->register_lock);
748 }
749
750 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
751                                unsigned int ls_offset, unsigned int size,
752                                unsigned int tag, unsigned int rclass,
753                                unsigned int cmd)
754 {
755         struct spu_problem __iomem *prob = spu->problem;
756         union mfc_tag_size_class_cmd command;
757         unsigned int transfer_size;
758         volatile unsigned int status = 0x0;
759
760         while (size > 0) {
761                 transfer_size =
762                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
763                 command.u.mfc_size = transfer_size;
764                 command.u.mfc_tag = tag;
765                 command.u.mfc_rclassid = rclass;
766                 command.u.mfc_cmd = cmd;
767                 do {
768                         out_be32(&prob->mfc_lsa_W, ls_offset);
769                         out_be64(&prob->mfc_ea_W, ea);
770                         out_be64(&prob->mfc_union_W.all64, command.all64);
771                         status =
772                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
773                         if (unlikely(status & 0x2)) {
774                                 cpu_relax();
775                         }
776                 } while (status & 0x3);
777                 size -= transfer_size;
778                 ea += transfer_size;
779                 ls_offset += transfer_size;
780         }
781         return 0;
782 }
783
784 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
785 {
786         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
787         unsigned int ls_offset = 0x0;
788         unsigned int size = 16384;
789         unsigned int tag = 0;
790         unsigned int rclass = 0;
791         unsigned int cmd = MFC_PUT_CMD;
792
793         /* Save, Step 50:
794          *     Issue a DMA command to copy the first 16K bytes
795          *     of local storage to the CSA.
796          */
797         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
798 }
799
800 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
801 {
802         struct spu_problem __iomem *prob = spu->problem;
803
804         /* Save, Step 51:
805          * Restore, Step 31.
806          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
807          *     point address of context save code in local
808          *     storage.
809          *
810          *     This implementation uses SPU-side save/restore
811          *     programs with entry points at LSA of 0.
812          */
813         out_be32(&prob->spu_npc_RW, 0);
814         eieio();
815 }
816
817 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
818 {
819         struct spu_problem __iomem *prob = spu->problem;
820         union {
821                 u64 ull;
822                 u32 ui[2];
823         } addr64;
824
825         /* Save, Step 52:
826          * Restore, Step 32:
827          *    Write SPU_Sig_Notify_1 register with upper 32-bits
828          *    of the CSA.LSCSA effective address.
829          */
830         addr64.ull = (u64) csa->lscsa;
831         out_be32(&prob->signal_notify1, addr64.ui[0]);
832         eieio();
833 }
834
835 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
836 {
837         struct spu_problem __iomem *prob = spu->problem;
838         union {
839                 u64 ull;
840                 u32 ui[2];
841         } addr64;
842
843         /* Save, Step 53:
844          * Restore, Step 33:
845          *    Write SPU_Sig_Notify_2 register with lower 32-bits
846          *    of the CSA.LSCSA effective address.
847          */
848         addr64.ull = (u64) csa->lscsa;
849         out_be32(&prob->signal_notify2, addr64.ui[1]);
850         eieio();
851 }
852
853 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
854 {
855         unsigned long addr = (unsigned long)&spu_save_code[0];
856         unsigned int ls_offset = 0x0;
857         unsigned int size = sizeof(spu_save_code);
858         unsigned int tag = 0;
859         unsigned int rclass = 0;
860         unsigned int cmd = MFC_GETFS_CMD;
861
862         /* Save, Step 54:
863          *     Issue a DMA command to copy context save code
864          *     to local storage and start SPU.
865          */
866         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
867 }
868
869 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
870 {
871         struct spu_problem __iomem *prob = spu->problem;
872
873         /* Save, Step 55:
874          * Restore, Step 38.
875          *     Write PPU_QueryMask=1 (enable Tag Group 0)
876          *     and issue eieio instruction.
877          */
878         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
879         eieio();
880 }
881
882 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
883 {
884         struct spu_problem __iomem *prob = spu->problem;
885         u32 mask = MFC_TAGID_TO_TAGMASK(0);
886         unsigned long flags;
887
888         /* Save, Step 56:
889          * Restore, Step 39.
890          * Restore, Step 39.
891          * Restore, Step 46.
892          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
893          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
894          *     Complete Interrupt.  Write INT_Stat_Class0 or
895          *     INT_Stat_Class2 with value of 'handled'.
896          */
897         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
898
899         local_irq_save(flags);
900         spu_int_stat_clear(spu, 0, ~(0ul));
901         spu_int_stat_clear(spu, 2, ~(0ul));
902         local_irq_restore(flags);
903 }
904
905 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
906 {
907         struct spu_problem __iomem *prob = spu->problem;
908         unsigned long flags;
909
910         /* Save, Step 57:
911          * Restore, Step 40.
912          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
913          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
914          *     or INT_Stat_class2 with value of handled.
915          */
916         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
917
918         local_irq_save(flags);
919         spu_int_stat_clear(spu, 0, ~(0ul));
920         spu_int_stat_clear(spu, 2, ~(0ul));
921         local_irq_restore(flags);
922 }
923
924 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
925 {
926         struct spu_problem __iomem *prob = spu->problem;
927         u32 complete;
928
929         /* Save, Step 54:
930          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
931          *     context save succeeded, otherwise context save
932          *     failed.
933          */
934         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
935                     SPU_STATUS_STOPPED_BY_STOP);
936         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
937 }
938
939 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
940 {
941         /* Restore, Step 4:
942          *    If required, notify the "using application" that
943          *    the SPU task has been terminated.  TBD.
944          */
945 }
946
947 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
948                 struct spu *spu)
949 {
950         struct spu_priv2 __iomem *priv2 = spu->priv2;
951
952         /* Restore, Step 7:
953          *     Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
954          *     the queue and halt the decrementer.
955          */
956         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
957                  MFC_CNTL_DECREMENTER_HALTED);
958         eieio();
959 }
960
961 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
962                                              struct spu *spu)
963 {
964         struct spu_priv2 __iomem *priv2 = spu->priv2;
965
966         /* Restore, Step 8:
967          * Restore, Step 47.
968          *     Poll MFC_CNTL[Ss] until 11 is returned.
969          */
970         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
971                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
972                          MFC_CNTL_SUSPEND_COMPLETE);
973 }
974
975 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
976 {
977         struct spu_problem __iomem *prob = spu->problem;
978
979         /* Restore, Step 9:
980          *    If SPU_Status[R]=1, stop SPU execution
981          *    and wait for stop to complete.
982          *
983          *    Returns       1 if SPU_Status[R]=1 on entry.
984          *                  0 otherwise
985          */
986         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
987                 if (in_be32(&prob->spu_status_R) &
988                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
989                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
990                                         SPU_STATUS_RUNNING);
991                 }
992                 if ((in_be32(&prob->spu_status_R) &
993                      SPU_STATUS_ISOLATED_LOAD_STATUS)
994                     || (in_be32(&prob->spu_status_R) &
995                         SPU_STATUS_ISOLATED_STATE)) {
996                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
997                         eieio();
998                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
999                                         SPU_STATUS_RUNNING);
1000                         out_be32(&prob->spu_runcntl_RW, 0x2);
1001                         eieio();
1002                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1003                                         SPU_STATUS_RUNNING);
1004                 }
1005                 if (in_be32(&prob->spu_status_R) &
1006                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1007                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1008                         eieio();
1009                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1010                                         SPU_STATUS_RUNNING);
1011                 }
1012                 return 1;
1013         }
1014         return 0;
1015 }
1016
1017 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1018 {
1019         struct spu_problem __iomem *prob = spu->problem;
1020
1021         /* Restore, Step 10:
1022          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1023          *    release SPU from isolate state.
1024          */
1025         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1026                 if (in_be32(&prob->spu_status_R) &
1027                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1028                         spu_mfc_sr1_set(spu,
1029                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1030                         eieio();
1031                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1032                         eieio();
1033                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1034                                         SPU_STATUS_RUNNING);
1035                 }
1036                 if ((in_be32(&prob->spu_status_R) &
1037                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1038                     || (in_be32(&prob->spu_status_R) &
1039                         SPU_STATUS_ISOLATED_STATE)) {
1040                         spu_mfc_sr1_set(spu,
1041                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1042                         eieio();
1043                         out_be32(&prob->spu_runcntl_RW, 0x2);
1044                         eieio();
1045                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1046                                         SPU_STATUS_RUNNING);
1047                 }
1048         }
1049 }
1050
1051 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1052 {
1053         struct spu_priv2 __iomem *priv2 = spu->priv2;
1054         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1055         u64 idx;
1056         int i;
1057
1058         /* Restore, Step 20:
1059          */
1060
1061         /* Reset CH 1 */
1062         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1063         out_be64(&priv2->spu_chnldata_RW, 0UL);
1064
1065         /* Reset the following CH: [0,3,4,24,25,27] */
1066         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1067                 idx = ch_indices[i];
1068                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1069                 eieio();
1070                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1071                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1072                 eieio();
1073         }
1074 }
1075
1076 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1077 {
1078         struct spu_priv2 __iomem *priv2 = spu->priv2;
1079         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1080         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1081         u64 idx;
1082         int i;
1083
1084         /* Restore, Step 21:
1085          *     Reset the following CH: [21, 23, 28, 29, 30]
1086          */
1087         for (i = 0; i < 5; i++) {
1088                 idx = ch_indices[i];
1089                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1090                 eieio();
1091                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1092                 eieio();
1093         }
1094 }
1095
1096 static inline void setup_spu_status_part1(struct spu_state *csa,
1097                                           struct spu *spu)
1098 {
1099         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1100         u32 status_I = SPU_STATUS_INVALID_INSTR;
1101         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1102         u32 status_S = SPU_STATUS_SINGLE_STEP;
1103         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1104         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1105         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1106         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1107         u32 status_code;
1108
1109         /* Restore, Step 27:
1110          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1111          *     instruction sequence to the end of the SPU based restore
1112          *     code (after the "context restored" stop and signal) to
1113          *     restore the correct SPU status.
1114          *
1115          *     NOTE: Rather than modifying the SPU executable, we
1116          *     instead add a new 'stopped_status' field to the
1117          *     LSCSA.  The SPU-side restore reads this field and
1118          *     takes the appropriate action when exiting.
1119          */
1120
1121         status_code =
1122             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1123         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1124
1125                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1126                  * by Stop and Signal instruction, followed by 'br -4'.
1127                  *
1128                  */
1129                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1130                 csa->lscsa->stopped_status.slot[1] = status_code;
1131
1132         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1133
1134                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1135                  * by Stop and Signal instruction, followed by
1136                  * 'br -4'.
1137                  */
1138                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1139                 csa->lscsa->stopped_status.slot[1] = status_code;
1140
1141         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1142
1143                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1144                  * followed by 'br -4'.
1145                  */
1146                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1147                 csa->lscsa->stopped_status.slot[1] = status_code;
1148
1149         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1150
1151                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1152                  * by 'br -4'.
1153                  */
1154                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1155                 csa->lscsa->stopped_status.slot[1] = status_code;
1156
1157         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1158
1159                 /* SPU_Status[P]=1 - Stop and Signal instruction
1160                  * followed by 'br -4'.
1161                  */
1162                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1163                 csa->lscsa->stopped_status.slot[1] = status_code;
1164
1165         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1166
1167                 /* SPU_Status[H]=1 - Halt Conditional, followed
1168                  * by 'br -4'.
1169                  */
1170                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1171
1172         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1173
1174                 /* SPU_Status[S]=1 - Two nop instructions.
1175                  */
1176                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1177
1178         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1179
1180                 /* SPU_Status[I]=1 - Illegal instruction followed
1181                  * by 'br -4'.
1182                  */
1183                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1184
1185         }
1186 }
1187
1188 static inline void setup_spu_status_part2(struct spu_state *csa,
1189                                           struct spu *spu)
1190 {
1191         u32 mask;
1192
1193         /* Restore, Step 28:
1194          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1195          *     add a 'br *' instruction to the end of
1196          *     the SPU based restore code.
1197          *
1198          *     NOTE: Rather than modifying the SPU executable, we
1199          *     instead add a new 'stopped_status' field to the
1200          *     LSCSA.  The SPU-side restore reads this field and
1201          *     takes the appropriate action when exiting.
1202          */
1203         mask = SPU_STATUS_INVALID_INSTR |
1204             SPU_STATUS_SINGLE_STEP |
1205             SPU_STATUS_STOPPED_BY_HALT |
1206             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1207         if (!(csa->prob.spu_status_R & mask)) {
1208                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1209         }
1210 }
1211
1212 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1213 {
1214         /* Restore, Step 29:
1215          *     Restore RA_GROUP_ID register and the
1216          *     RA_ENABLE reigster from the CSA.
1217          */
1218         spu_resource_allocation_groupID_set(spu,
1219                         csa->priv1.resource_allocation_groupID_RW);
1220         spu_resource_allocation_enable_set(spu,
1221                         csa->priv1.resource_allocation_enable_RW);
1222 }
1223
1224 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1225 {
1226         unsigned long addr = (unsigned long)&spu_restore_code[0];
1227         unsigned int ls_offset = 0x0;
1228         unsigned int size = sizeof(spu_restore_code);
1229         unsigned int tag = 0;
1230         unsigned int rclass = 0;
1231         unsigned int cmd = MFC_GETFS_CMD;
1232
1233         /* Restore, Step 37:
1234          *     Issue MFC DMA command to copy context
1235          *     restore code to local storage.
1236          */
1237         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1238 }
1239
1240 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1241 {
1242         /* Restore, Step 34:
1243          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1244          *     running) then adjust decrementer, set
1245          *     decrementer running status in LSCSA,
1246          *     and set decrementer "wrapped" status
1247          *     in LSCSA.
1248          */
1249         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1250                 cycles_t resume_time = get_cycles();
1251                 cycles_t delta_time = resume_time - csa->suspend_time;
1252
1253                 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1254                 if (csa->lscsa->decr.slot[0] < delta_time) {
1255                         csa->lscsa->decr_status.slot[0] |=
1256                                  SPU_DECR_STATUS_WRAPPED;
1257                 }
1258
1259                 csa->lscsa->decr.slot[0] -= delta_time;
1260         } else {
1261                 csa->lscsa->decr_status.slot[0] = 0;
1262         }
1263 }
1264
1265 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1266 {
1267         /* Restore, Step 35:
1268          *     Copy the CSA.PU_MB data into the LSCSA.
1269          */
1270         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1271 }
1272
1273 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1274 {
1275         /* Restore, Step 36:
1276          *     Copy the CSA.PUINT_MB data into the LSCSA.
1277          */
1278         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1279 }
1280
1281 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1282 {
1283         struct spu_problem __iomem *prob = spu->problem;
1284         u32 complete;
1285
1286         /* Restore, Step 40:
1287          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1288          *     context restore succeeded, otherwise context restore
1289          *     failed.
1290          */
1291         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1292                     SPU_STATUS_STOPPED_BY_STOP);
1293         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1294 }
1295
1296 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1297 {
1298         struct spu_priv2 __iomem *priv2 = spu->priv2;
1299
1300         /* Restore, Step 41:
1301          *     Restore SPU_PrivCntl from the CSA.
1302          */
1303         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1304         eieio();
1305 }
1306
1307 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1308 {
1309         struct spu_problem __iomem *prob = spu->problem;
1310         u32 mask;
1311
1312         /* Restore, Step 42:
1313          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1314          *     restore the error or single step state.
1315          */
1316         mask = SPU_STATUS_INVALID_INSTR |
1317             SPU_STATUS_SINGLE_STEP |
1318             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1319         if (csa->prob.spu_status_R & mask) {
1320                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1321                 eieio();
1322                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1323                                 SPU_STATUS_RUNNING);
1324         }
1325 }
1326
1327 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1328 {
1329         struct spu_problem __iomem *prob = spu->problem;
1330         u32 mask;
1331
1332         /* Restore, Step 43:
1333          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1334          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1335          *     then write '00' to SPU_RunCntl[R0R1] and wait
1336          *     for SPU_Status[R]=0.
1337          */
1338         mask = SPU_STATUS_INVALID_INSTR |
1339             SPU_STATUS_SINGLE_STEP |
1340             SPU_STATUS_STOPPED_BY_HALT |
1341             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1342         if (!(csa->prob.spu_status_R & mask)) {
1343                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1344                 eieio();
1345                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1346                                  SPU_STATUS_RUNNING);
1347                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1348                 eieio();
1349                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1350                                 SPU_STATUS_RUNNING);
1351         }
1352 }
1353
1354 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1355 {
1356         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1357         unsigned int ls_offset = 0x0;
1358         unsigned int size = 16384;
1359         unsigned int tag = 0;
1360         unsigned int rclass = 0;
1361         unsigned int cmd = MFC_GET_CMD;
1362
1363         /* Restore, Step 44:
1364          *     Issue a DMA command to restore the first
1365          *     16kb of local storage from CSA.
1366          */
1367         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1368 }
1369
1370 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1371 {
1372         struct spu_priv2 __iomem *priv2 = spu->priv2;
1373
1374         /* Restore, Step 47.
1375          *     Write MFC_Cntl[Sc,Sm]='1','0' to suspend
1376          *     the queue.
1377          */
1378         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1379         eieio();
1380 }
1381
1382 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1383 {
1384         /* Restore, Step 49:
1385          *     Write INT_MASK_class0 with value of 0.
1386          *     Write INT_MASK_class1 with value of 0.
1387          *     Write INT_MASK_class2 with value of 0.
1388          *     Write INT_STAT_class0 with value of -1.
1389          *     Write INT_STAT_class1 with value of -1.
1390          *     Write INT_STAT_class2 with value of -1.
1391          */
1392         spin_lock_irq(&spu->register_lock);
1393         spu_int_mask_set(spu, 0, 0ul);
1394         spu_int_mask_set(spu, 1, 0ul);
1395         spu_int_mask_set(spu, 2, 0ul);
1396         spu_int_stat_clear(spu, 0, ~0ul);
1397         spu_int_stat_clear(spu, 1, ~0ul);
1398         spu_int_stat_clear(spu, 2, ~0ul);
1399         spin_unlock_irq(&spu->register_lock);
1400 }
1401
1402 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1403 {
1404         struct spu_priv2 __iomem *priv2 = spu->priv2;
1405         int i;
1406
1407         /* Restore, Step 50:
1408          *     If MFC_Cntl[Se]!=0 then restore
1409          *     MFC command queues.
1410          */
1411         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1412                 for (i = 0; i < 8; i++) {
1413                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1414                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1415                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1416                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1417                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1418                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1419                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1420                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1421                 }
1422                 for (i = 0; i < 16; i++) {
1423                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1424                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1425                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1426                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1427                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1428                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1429                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1430                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1431                 }
1432         }
1433         eieio();
1434 }
1435
1436 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1437 {
1438         struct spu_problem __iomem *prob = spu->problem;
1439
1440         /* Restore, Step 51:
1441          *     Restore the PPU_QueryMask register from CSA.
1442          */
1443         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1444         eieio();
1445 }
1446
1447 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1448 {
1449         struct spu_problem __iomem *prob = spu->problem;
1450
1451         /* Restore, Step 52:
1452          *     Restore the PPU_QueryType register from CSA.
1453          */
1454         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1455         eieio();
1456 }
1457
1458 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1459 {
1460         struct spu_priv2 __iomem *priv2 = spu->priv2;
1461
1462         /* Restore, Step 53:
1463          *     Restore the MFC_CSR_TSQ register from CSA.
1464          */
1465         out_be64(&priv2->spu_tag_status_query_RW,
1466                  csa->priv2.spu_tag_status_query_RW);
1467         eieio();
1468 }
1469
1470 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1471 {
1472         struct spu_priv2 __iomem *priv2 = spu->priv2;
1473
1474         /* Restore, Step 54:
1475          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1476          *     registers from CSA.
1477          */
1478         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1479         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1480         eieio();
1481 }
1482
1483 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1484 {
1485         struct spu_priv2 __iomem *priv2 = spu->priv2;
1486
1487         /* Restore, Step 55:
1488          *     Restore the MFC_CSR_ATO register from CSA.
1489          */
1490         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1491 }
1492
1493 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1494 {
1495         /* Restore, Step 56:
1496          *     Restore the MFC_TCLASS_ID register from CSA.
1497          */
1498         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1499         eieio();
1500 }
1501
1502 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1503 {
1504         u64 ch0_cnt, ch0_data;
1505         u64 ch1_data;
1506
1507         /* Restore, Step 57:
1508          *    Set the Lock Line Reservation Lost Event by:
1509          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1510          *      2. If CSA.SPU_Channel_0_Count=0 and
1511          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1512          *         CSA.SPU_Event_Status[Lr]=0 then set
1513          *         CSA.SPU_Event_Status_Count=1.
1514          */
1515         ch0_cnt = csa->spu_chnlcnt_RW[0];
1516         ch0_data = csa->spu_chnldata_RW[0];
1517         ch1_data = csa->spu_chnldata_RW[1];
1518         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1519         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1520             (ch1_data & MFC_LLR_LOST_EVENT)) {
1521                 csa->spu_chnlcnt_RW[0] = 1;
1522         }
1523 }
1524
1525 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1526 {
1527         /* Restore, Step 58:
1528          *     If the status of the CSA software decrementer
1529          *     "wrapped" flag is set, OR in a '1' to
1530          *     CSA.SPU_Event_Status[Tm].
1531          */
1532         if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1533                 return;
1534
1535         if ((csa->spu_chnlcnt_RW[0] == 0) &&
1536             (csa->spu_chnldata_RW[1] & 0x20) &&
1537             !(csa->spu_chnldata_RW[0] & 0x20))
1538                 csa->spu_chnlcnt_RW[0] = 1;
1539
1540         csa->spu_chnldata_RW[0] |= 0x20;
1541 }
1542
1543 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1544 {
1545         struct spu_priv2 __iomem *priv2 = spu->priv2;
1546         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1547         int i;
1548
1549         /* Restore, Step 59:
1550          *      Restore the following CH: [0,3,4,24,25,27]
1551          */
1552         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1553                 idx = ch_indices[i];
1554                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1555                 eieio();
1556                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1557                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1558                 eieio();
1559         }
1560 }
1561
1562 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1563 {
1564         struct spu_priv2 __iomem *priv2 = spu->priv2;
1565         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1566         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1567         u64 idx;
1568         int i;
1569
1570         /* Restore, Step 60:
1571          *     Restore the following CH: [9,21,23].
1572          */
1573         ch_counts[0] = 1UL;
1574         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1575         ch_counts[2] = 1UL;
1576         for (i = 0; i < 3; i++) {
1577                 idx = ch_indices[i];
1578                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1579                 eieio();
1580                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1581                 eieio();
1582         }
1583 }
1584
1585 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1586 {
1587         struct spu_priv2 __iomem *priv2 = spu->priv2;
1588
1589         /* Restore, Step 61:
1590          *     Restore the SPU_LSLR register from CSA.
1591          */
1592         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1593         eieio();
1594 }
1595
1596 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1597 {
1598         struct spu_priv2 __iomem *priv2 = spu->priv2;
1599
1600         /* Restore, Step 62:
1601          *     Restore the SPU_Cfg register from CSA.
1602          */
1603         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1604         eieio();
1605 }
1606
1607 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1608 {
1609         /* Restore, Step 63:
1610          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1611          *     Not performed by this implementation.
1612          */
1613 }
1614
1615 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1616 {
1617         struct spu_problem __iomem *prob = spu->problem;
1618
1619         /* Restore, Step 64:
1620          *     Restore SPU_NPC from CSA.
1621          */
1622         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1623         eieio();
1624 }
1625
1626 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1627 {
1628         struct spu_priv2 __iomem *priv2 = spu->priv2;
1629         int i;
1630
1631         /* Restore, Step 65:
1632          *     Restore MFC_RdSPU_MB from CSA.
1633          */
1634         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1635         eieio();
1636         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1637         for (i = 0; i < 4; i++) {
1638                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1639         }
1640         eieio();
1641 }
1642
1643 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1644 {
1645         struct spu_problem __iomem *prob = spu->problem;
1646         u32 dummy = 0;
1647
1648         /* Restore, Step 66:
1649          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1650          *     read from the PPU_MB register.
1651          */
1652         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1653                 dummy = in_be32(&prob->pu_mb_R);
1654                 eieio();
1655         }
1656 }
1657
1658 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1659 {
1660         struct spu_priv2 __iomem *priv2 = spu->priv2;
1661         u64 dummy = 0UL;
1662
1663         /* Restore, Step 66:
1664          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1665          *     read from the PPUINT_MB register.
1666          */
1667         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1668                 dummy = in_be64(&priv2->puint_mb_R);
1669                 eieio();
1670                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1671                 eieio();
1672         }
1673 }
1674
1675 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1676 {
1677         /* Restore, Step 69:
1678          *     Restore the MFC_SR1 register from CSA.
1679          */
1680         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1681         eieio();
1682 }
1683
1684 static inline void restore_other_spu_access(struct spu_state *csa,
1685                                             struct spu *spu)
1686 {
1687         /* Restore, Step 70:
1688          *     Restore other SPU mappings to this SPU. TBD.
1689          */
1690 }
1691
1692 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1693 {
1694         struct spu_problem __iomem *prob = spu->problem;
1695
1696         /* Restore, Step 71:
1697          *     If CSA.SPU_Status[R]=1 then write
1698          *     SPU_RunCntl[R0R1]='01'.
1699          */
1700         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1701                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1702                 eieio();
1703         }
1704 }
1705
1706 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1707 {
1708         struct spu_priv2 __iomem *priv2 = spu->priv2;
1709
1710         /* Restore, Step 72:
1711          *    Restore the MFC_CNTL register for the CSA.
1712          */
1713         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1714         eieio();
1715         /*
1716          * FIXME: this is to restart a DMA that we were processing
1717          *        before the save. better remember the fault information
1718          *        in the csa instead.
1719          */
1720         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1721                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1722                 eieio();
1723         }
1724 }
1725
1726 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1727 {
1728         /* Restore, Step 73:
1729          *     Enable user-space access (if provided) to this
1730          *     SPU by mapping the virtual pages assigned to
1731          *     the SPU memory-mapped I/O (MMIO) for problem
1732          *     state. TBD.
1733          */
1734 }
1735
1736 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1737 {
1738         /* Restore, Step 74:
1739          *     Reset the "context switch active" flag.
1740          */
1741         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1742         mb();
1743 }
1744
1745 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1746 {
1747         /* Restore, Step 75:
1748          *     Re-enable SPU interrupts.
1749          */
1750         spin_lock_irq(&spu->register_lock);
1751         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1752         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1753         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1754         spin_unlock_irq(&spu->register_lock);
1755 }
1756
1757 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1758 {
1759         /*
1760          * Combined steps 2-18 of SPU context save sequence, which
1761          * quiesce the SPU state (disable SPU execution, MFC command
1762          * queues, decrementer, SPU interrupts, etc.).
1763          *
1764          * Returns      0 on success.
1765          *              2 if failed step 2.
1766          *              6 if failed step 6.
1767          */
1768
1769         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1770                 return 2;
1771         }
1772         disable_interrupts(prev, spu);          /* Step 3. */
1773         set_watchdog_timer(prev, spu);          /* Step 4. */
1774         inhibit_user_access(prev, spu);         /* Step 5. */
1775         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1776                 return 6;
1777         }
1778         set_switch_pending(prev, spu);          /* Step 7. */
1779         save_mfc_cntl(prev, spu);               /* Step 8. */
1780         save_spu_runcntl(prev, spu);            /* Step 9. */
1781         save_mfc_sr1(prev, spu);                /* Step 10. */
1782         save_spu_status(prev, spu);             /* Step 11. */
1783         save_mfc_decr(prev, spu);               /* Step 12. */
1784         halt_mfc_decr(prev, spu);               /* Step 13. */
1785         save_timebase(prev, spu);               /* Step 14. */
1786         remove_other_spu_access(prev, spu);     /* Step 15. */
1787         do_mfc_mssync(prev, spu);               /* Step 16. */
1788         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1789         handle_pending_interrupts(prev, spu);   /* Step 18. */
1790
1791         return 0;
1792 }
1793
1794 static void save_csa(struct spu_state *prev, struct spu *spu)
1795 {
1796         /*
1797          * Combine steps 19-44 of SPU context save sequence, which
1798          * save regions of the privileged & problem state areas.
1799          */
1800
1801         save_mfc_queues(prev, spu);     /* Step 19. */
1802         save_ppu_querymask(prev, spu);  /* Step 20. */
1803         save_ppu_querytype(prev, spu);  /* Step 21. */
1804         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1805         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1806         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1807         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1808         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1809         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1810         purge_mfc_queue(prev, spu);     /* Step 27. */
1811         wait_purge_complete(prev, spu); /* Step 28. */
1812         setup_mfc_sr1(prev, spu);       /* Step 30. */
1813         save_spu_npc(prev, spu);        /* Step 31. */
1814         save_spu_privcntl(prev, spu);   /* Step 32. */
1815         reset_spu_privcntl(prev, spu);  /* Step 33. */
1816         save_spu_lslr(prev, spu);       /* Step 34. */
1817         reset_spu_lslr(prev, spu);      /* Step 35. */
1818         save_spu_cfg(prev, spu);        /* Step 36. */
1819         save_pm_trace(prev, spu);       /* Step 37. */
1820         save_mfc_rag(prev, spu);        /* Step 38. */
1821         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1822         save_ppu_mb(prev, spu);         /* Step 40. */
1823         save_ppuint_mb(prev, spu);      /* Step 41. */
1824         save_ch_part1(prev, spu);       /* Step 42. */
1825         save_spu_mb(prev, spu);         /* Step 43. */
1826         save_mfc_cmd(prev, spu);        /* Step 44. */
1827         reset_ch(prev, spu);            /* Step 45. */
1828 }
1829
1830 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1831 {
1832         /*
1833          * Perform steps 46-57 of SPU context save sequence,
1834          * which save regions of the local store and register
1835          * file.
1836          */
1837
1838         resume_mfc_queue(prev, spu);    /* Step 46. */
1839         /* Step 47. */
1840         setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));
1841         set_switch_active(prev, spu);   /* Step 48. */
1842         enable_interrupts(prev, spu);   /* Step 49. */
1843         save_ls_16kb(prev, spu);        /* Step 50. */
1844         set_spu_npc(prev, spu);         /* Step 51. */
1845         set_signot1(prev, spu);         /* Step 52. */
1846         set_signot2(prev, spu);         /* Step 53. */
1847         send_save_code(prev, spu);      /* Step 54. */
1848         set_ppu_querymask(prev, spu);   /* Step 55. */
1849         wait_tag_complete(prev, spu);   /* Step 56. */
1850         wait_spu_stopped(prev, spu);    /* Step 57. */
1851 }
1852
1853 static void force_spu_isolate_exit(struct spu *spu)
1854 {
1855         struct spu_problem __iomem *prob = spu->problem;
1856         struct spu_priv2 __iomem *priv2 = spu->priv2;
1857
1858         /* Stop SPE execution and wait for completion. */
1859         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1860         iobarrier_rw();
1861         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1862
1863         /* Restart SPE master runcntl. */
1864         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1865         iobarrier_w();
1866
1867         /* Initiate isolate exit request and wait for completion. */
1868         out_be64(&priv2->spu_privcntl_RW, 4LL);
1869         iobarrier_w();
1870         out_be32(&prob->spu_runcntl_RW, 2);
1871         iobarrier_rw();
1872         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1873                                 & SPU_STATUS_STOPPED_BY_STOP));
1874
1875         /* Reset load request to normal. */
1876         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1877         iobarrier_w();
1878 }
1879
1880 /**
1881  * stop_spu_isolate
1882  *      Check SPU run-control state and force isolated
1883  *      exit function as necessary.
1884  */
1885 static void stop_spu_isolate(struct spu *spu)
1886 {
1887         struct spu_problem __iomem *prob = spu->problem;
1888
1889         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1890                 /* The SPU is in isolated state; the only way
1891                  * to get it out is to perform an isolated
1892                  * exit (clean) operation.
1893                  */
1894                 force_spu_isolate_exit(spu);
1895         }
1896 }
1897
1898 static void harvest(struct spu_state *prev, struct spu *spu)
1899 {
1900         /*
1901          * Perform steps 2-25 of SPU context restore sequence,
1902          * which resets an SPU either after a failed save, or
1903          * when using SPU for first time.
1904          */
1905
1906         disable_interrupts(prev, spu);          /* Step 2.  */
1907         inhibit_user_access(prev, spu);         /* Step 3.  */
1908         terminate_spu_app(prev, spu);           /* Step 4.  */
1909         set_switch_pending(prev, spu);          /* Step 5.  */
1910         stop_spu_isolate(spu);                  /* NEW.     */
1911         remove_other_spu_access(prev, spu);     /* Step 6.  */
1912         suspend_mfc_and_halt_decr(prev, spu);   /* Step 7.  */
1913         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1914         if (!suspend_spe(prev, spu))            /* Step 9.  */
1915                 clear_spu_status(prev, spu);    /* Step 10. */
1916         do_mfc_mssync(prev, spu);               /* Step 11. */
1917         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1918         handle_pending_interrupts(prev, spu);   /* Step 13. */
1919         purge_mfc_queue(prev, spu);             /* Step 14. */
1920         wait_purge_complete(prev, spu);         /* Step 15. */
1921         reset_spu_privcntl(prev, spu);          /* Step 16. */
1922         reset_spu_lslr(prev, spu);              /* Step 17. */
1923         setup_mfc_sr1(prev, spu);               /* Step 18. */
1924         spu_invalidate_slbs(spu);               /* Step 19. */
1925         reset_ch_part1(prev, spu);              /* Step 20. */
1926         reset_ch_part2(prev, spu);              /* Step 21. */
1927         enable_interrupts(prev, spu);           /* Step 22. */
1928         set_switch_active(prev, spu);           /* Step 23. */
1929         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1930         resume_mfc_queue(prev, spu);            /* Step 25. */
1931 }
1932
1933 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1934 {
1935         /*
1936          * Perform steps 26-40 of SPU context restore sequence,
1937          * which restores regions of the local store and register
1938          * file.
1939          */
1940
1941         set_watchdog_timer(next, spu);          /* Step 26. */
1942         setup_spu_status_part1(next, spu);      /* Step 27. */
1943         setup_spu_status_part2(next, spu);      /* Step 28. */
1944         restore_mfc_rag(next, spu);             /* Step 29. */
1945         /* Step 30. */
1946         setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));
1947         set_spu_npc(next, spu);                 /* Step 31. */
1948         set_signot1(next, spu);                 /* Step 32. */
1949         set_signot2(next, spu);                 /* Step 33. */
1950         setup_decr(next, spu);                  /* Step 34. */
1951         setup_ppu_mb(next, spu);                /* Step 35. */
1952         setup_ppuint_mb(next, spu);             /* Step 36. */
1953         send_restore_code(next, spu);           /* Step 37. */
1954         set_ppu_querymask(next, spu);           /* Step 38. */
1955         wait_tag_complete(next, spu);           /* Step 39. */
1956         wait_spu_stopped(next, spu);            /* Step 40. */
1957 }
1958
1959 static void restore_csa(struct spu_state *next, struct spu *spu)
1960 {
1961         /*
1962          * Combine steps 41-76 of SPU context restore sequence, which
1963          * restore regions of the privileged & problem state areas.
1964          */
1965
1966         restore_spu_privcntl(next, spu);        /* Step 41. */
1967         restore_status_part1(next, spu);        /* Step 42. */
1968         restore_status_part2(next, spu);        /* Step 43. */
1969         restore_ls_16kb(next, spu);             /* Step 44. */
1970         wait_tag_complete(next, spu);           /* Step 45. */
1971         suspend_mfc(next, spu);                 /* Step 46. */
1972         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1973         issue_mfc_tlbie(next, spu);             /* Step 48. */
1974         clear_interrupts(next, spu);            /* Step 49. */
1975         restore_mfc_queues(next, spu);          /* Step 50. */
1976         restore_ppu_querymask(next, spu);       /* Step 51. */
1977         restore_ppu_querytype(next, spu);       /* Step 52. */
1978         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1979         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1980         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1981         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1982         set_llr_event(next, spu);               /* Step 57. */
1983         restore_decr_wrapped(next, spu);        /* Step 58. */
1984         restore_ch_part1(next, spu);            /* Step 59. */
1985         restore_ch_part2(next, spu);            /* Step 60. */
1986         restore_spu_lslr(next, spu);            /* Step 61. */
1987         restore_spu_cfg(next, spu);             /* Step 62. */
1988         restore_pm_trace(next, spu);            /* Step 63. */
1989         restore_spu_npc(next, spu);             /* Step 64. */
1990         restore_spu_mb(next, spu);              /* Step 65. */
1991         check_ppu_mb_stat(next, spu);           /* Step 66. */
1992         check_ppuint_mb_stat(next, spu);        /* Step 67. */
1993         spu_invalidate_slbs(spu);               /* Modified Step 68. */
1994         restore_mfc_sr1(next, spu);             /* Step 69. */
1995         restore_other_spu_access(next, spu);    /* Step 70. */
1996         restore_spu_runcntl(next, spu);         /* Step 71. */
1997         restore_mfc_cntl(next, spu);            /* Step 72. */
1998         enable_user_access(next, spu);          /* Step 73. */
1999         reset_switch_active(next, spu);         /* Step 74. */
2000         reenable_interrupts(next, spu);         /* Step 75. */
2001 }
2002
2003 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2004 {
2005         int rc;
2006
2007         /*
2008          * SPU context save can be broken into three phases:
2009          *
2010          *     (a) quiesce [steps 2-16].
2011          *     (b) save of CSA, performed by PPE [steps 17-42]
2012          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2013          *
2014          * Returns      0 on success.
2015          *              2,6 if failed to quiece SPU
2016          *              53 if SPU-side of save failed.
2017          */
2018
2019         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2020         switch (rc) {
2021         default:
2022         case 2:
2023         case 6:
2024                 harvest(prev, spu);
2025                 return rc;
2026                 break;
2027         case 0:
2028                 break;
2029         }
2030         save_csa(prev, spu);                    /* Steps 17-43. */
2031         save_lscsa(prev, spu);                  /* Steps 44-53. */
2032         return check_save_status(prev, spu);    /* Step 54.     */
2033 }
2034
2035 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2036 {
2037         int rc;
2038
2039         /*
2040          * SPU context restore can be broken into three phases:
2041          *
2042          *    (a) harvest (or reset) SPU [steps 2-24].
2043          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2044          *    (c) restore CSA [steps 41-76], performed by PPE.
2045          *
2046          * The 'harvest' step is not performed here, but rather
2047          * as needed below.
2048          */
2049
2050         restore_lscsa(next, spu);               /* Steps 24-39. */
2051         rc = check_restore_status(next, spu);   /* Step 40.     */
2052         switch (rc) {
2053         default:
2054                 /* Failed. Return now. */
2055                 return rc;
2056                 break;
2057         case 0:
2058                 /* Fall through to next step. */
2059                 break;
2060         }
2061         restore_csa(next, spu);
2062
2063         return 0;
2064 }
2065
2066 /**
2067  * spu_save - SPU context save, with locking.
2068  * @prev: pointer to SPU context save area, to be saved.
2069  * @spu: pointer to SPU iomem structure.
2070  *
2071  * Acquire locks, perform the save operation then return.
2072  */
2073 int spu_save(struct spu_state *prev, struct spu *spu)
2074 {
2075         int rc;
2076
2077         acquire_spu_lock(spu);          /* Step 1.     */
2078         prev->dar = spu->dar;
2079         prev->dsisr = spu->dsisr;
2080         spu->dar = 0;
2081         spu->dsisr = 0;
2082         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2083         release_spu_lock(spu);
2084         if (rc != 0 && rc != 2 && rc != 6) {
2085                 panic("%s failed on SPU[%d], rc=%d.\n",
2086                       __func__, spu->number, rc);
2087         }
2088         return 0;
2089 }
2090 EXPORT_SYMBOL_GPL(spu_save);
2091
2092 /**
2093  * spu_restore - SPU context restore, with harvest and locking.
2094  * @new: pointer to SPU context save area, to be restored.
2095  * @spu: pointer to SPU iomem structure.
2096  *
2097  * Perform harvest + restore, as we may not be coming
2098  * from a previous successful save operation, and the
2099  * hardware state is unknown.
2100  */
2101 int spu_restore(struct spu_state *new, struct spu *spu)
2102 {
2103         int rc;
2104
2105         acquire_spu_lock(spu);
2106         harvest(NULL, spu);
2107         spu->slb_replace = 0;
2108         new->dar = 0;
2109         new->dsisr = 0;
2110         spu->class_0_pending = 0;
2111         rc = __do_spu_restore(new, spu);
2112         release_spu_lock(spu);
2113         if (rc) {
2114                 panic("%s failed on SPU[%d] rc=%d.\n",
2115                        __func__, spu->number, rc);
2116         }
2117         return rc;
2118 }
2119 EXPORT_SYMBOL_GPL(spu_restore);
2120
2121 static void init_prob(struct spu_state *csa)
2122 {
2123         csa->spu_chnlcnt_RW[9] = 1;
2124         csa->spu_chnlcnt_RW[21] = 16;
2125         csa->spu_chnlcnt_RW[23] = 1;
2126         csa->spu_chnlcnt_RW[28] = 1;
2127         csa->spu_chnlcnt_RW[30] = 1;
2128         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2129         csa->prob.mb_stat_R = 0x000400;
2130 }
2131
2132 static void init_priv1(struct spu_state *csa)
2133 {
2134         /* Enable decode, relocate, tlbie response, master runcntl. */
2135         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2136             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2137             MFC_STATE1_PROBLEM_STATE_MASK |
2138             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2139
2140         /* Enable OS-specific set of interrupts. */
2141         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2142             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2143             CLASS0_ENABLE_SPU_ERROR_INTR;
2144         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2145             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2146         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2147             CLASS2_ENABLE_SPU_HALT_INTR |
2148             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2149 }
2150
2151 static void init_priv2(struct spu_state *csa)
2152 {
2153         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2154         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2155             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2156             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2157 }
2158
2159 /**
2160  * spu_alloc_csa - allocate and initialize an SPU context save area.
2161  *
2162  * Allocate and initialize the contents of an SPU context save area.
2163  * This includes enabling address translation, interrupt masks, etc.,
2164  * as appropriate for the given OS environment.
2165  *
2166  * Note that storage for the 'lscsa' is allocated separately,
2167  * as it is by far the largest of the context save regions,
2168  * and may need to be pinned or otherwise specially aligned.
2169  */
2170 int spu_init_csa(struct spu_state *csa)
2171 {
2172         int rc;
2173
2174         if (!csa)
2175                 return -EINVAL;
2176         memset(csa, 0, sizeof(struct spu_state));
2177
2178         rc = spu_alloc_lscsa(csa);
2179         if (rc)
2180                 return rc;
2181
2182         spin_lock_init(&csa->register_lock);
2183
2184         init_prob(csa);
2185         init_priv1(csa);
2186         init_priv2(csa);
2187
2188         return 0;
2189 }
2190 EXPORT_SYMBOL_GPL(spu_init_csa);
2191
2192 void spu_fini_csa(struct spu_state *csa)
2193 {
2194         spu_free_lscsa(csa);
2195 }
2196 EXPORT_SYMBOL_GPL(spu_fini_csa);