[PATCH] irq-flags: POWERPC: Use the new IRQF_ constants
[linux-2.6.git] / arch / powerpc / platforms / cell / interrupt.c
1 /*
2  * Cell Internal Interrupt Controller
3  *
4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *
6  * Author: Arnd Bergmann <arndb@de.ibm.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/percpu.h>
27 #include <linux/types.h>
28
29 #include <asm/io.h>
30 #include <asm/pgtable.h>
31 #include <asm/prom.h>
32 #include <asm/ptrace.h>
33
34 #include "interrupt.h"
35 #include "cbe_regs.h"
36
37 struct iic {
38         struct cbe_iic_thread_regs __iomem *regs;
39         u8 target_id;
40 };
41
42 static DEFINE_PER_CPU(struct iic, iic);
43
44 void iic_local_enable(void)
45 {
46         struct iic *iic = &__get_cpu_var(iic);
47         u64 tmp;
48
49         /*
50          * There seems to be a bug that is present in DD2.x CPUs
51          * and still only partially fixed in DD3.1.
52          * This bug causes a value written to the priority register
53          * not to make it there, resulting in a system hang unless we
54          * write it again.
55          * Masking with 0xf0 is done because the Cell BE does not
56          * implement the lower four bits of the interrupt priority,
57          * they always read back as zeroes, although future CPUs
58          * might implement different bits.
59          */
60         do {
61                 out_be64(&iic->regs->prio, 0xff);
62                 tmp = in_be64(&iic->regs->prio);
63         } while ((tmp & 0xf0) != 0xf0);
64 }
65
66 void iic_local_disable(void)
67 {
68         out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
69 }
70
71 static unsigned int iic_startup(unsigned int irq)
72 {
73         return 0;
74 }
75
76 static void iic_enable(unsigned int irq)
77 {
78         iic_local_enable();
79 }
80
81 static void iic_disable(unsigned int irq)
82 {
83 }
84
85 static void iic_end(unsigned int irq)
86 {
87         iic_local_enable();
88 }
89
90 static struct hw_interrupt_type iic_pic = {
91         .typename = " CELL-IIC ",
92         .startup = iic_startup,
93         .enable = iic_enable,
94         .disable = iic_disable,
95         .end = iic_end,
96 };
97
98 static int iic_external_get_irq(struct cbe_iic_pending_bits pending)
99 {
100         int irq;
101         unsigned char node, unit;
102
103         node = pending.source >> 4;
104         unit = pending.source & 0xf;
105         irq = -1;
106
107         /*
108          * This mapping is specific to the Cell Broadband
109          * Engine. We might need to get the numbers
110          * from the device tree to support future CPUs.
111          */
112         switch (unit) {
113         case 0x00:
114         case 0x0b:
115                 /*
116                  * One of these units can be connected
117                  * to an external interrupt controller.
118                  */
119                 if (pending.class != 2)
120                         break;
121                 irq = IIC_EXT_OFFSET
122                         + spider_get_irq(node)
123                         + node * IIC_NODE_STRIDE;
124                 break;
125         case 0x01 ... 0x04:
126         case 0x07 ... 0x0a:
127                 /*
128                  * These units are connected to the SPEs
129                  */
130                 if (pending.class > 2)
131                         break;
132                 irq = IIC_SPE_OFFSET
133                         + pending.class * IIC_CLASS_STRIDE
134                         + node * IIC_NODE_STRIDE
135                         + unit;
136                 break;
137         }
138         if (irq == -1)
139                 printk(KERN_WARNING "Unexpected interrupt class %02x, "
140                         "source %02x, prio %02x, cpu %02x\n", pending.class,
141                         pending.source, pending.prio, smp_processor_id());
142         return irq;
143 }
144
145 /* Get an IRQ number from the pending state register of the IIC */
146 int iic_get_irq(struct pt_regs *regs)
147 {
148         struct iic *iic;
149         int irq;
150         struct cbe_iic_pending_bits pending;
151
152         iic = &__get_cpu_var(iic);
153         *(unsigned long *) &pending = 
154                 in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
155
156         irq = -1;
157         if (pending.flags & CBE_IIC_IRQ_VALID) {
158                 if (pending.flags & CBE_IIC_IRQ_IPI) {
159                         irq = IIC_IPI_OFFSET + (pending.prio >> 4);
160 /*
161                         if (irq > 0x80)
162                                 printk(KERN_WARNING "Unexpected IPI prio %02x"
163                                         "on CPU %02x\n", pending.prio,
164                                                         smp_processor_id());
165 */
166                 } else {
167                         irq = iic_external_get_irq(pending);
168                 }
169         }
170         return irq;
171 }
172
173 /* hardcoded part to be compatible with older firmware */
174
175 static int setup_iic_hardcoded(void)
176 {
177         struct device_node *np;
178         int nodeid, cpu;
179         unsigned long regs;
180         struct iic *iic;
181
182         for_each_possible_cpu(cpu) {
183                 iic = &per_cpu(iic, cpu);
184                 nodeid = cpu/2;
185
186                 for (np = of_find_node_by_type(NULL, "cpu");
187                      np;
188                      np = of_find_node_by_type(np, "cpu")) {
189                         if (nodeid == *(int *)get_property(np, "node-id", NULL))
190                                 break;
191                         }
192
193                 if (!np) {
194                         printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
195                         iic->regs = NULL;
196                         iic->target_id = 0xff;
197                         return -ENODEV;
198                         }
199
200                 regs = *(long *)get_property(np, "iic", NULL);
201
202                 /* hack until we have decided on the devtree info */
203                 regs += 0x400;
204                 if (cpu & 1)
205                         regs += 0x20;
206
207                 printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
208                 iic->regs = ioremap(regs, sizeof(struct cbe_iic_thread_regs));
209                 iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
210         }
211
212         return 0;
213 }
214
215 static int setup_iic(void)
216 {
217         struct device_node *dn;
218         unsigned long *regs;
219         char *compatible;
220         unsigned *np, found = 0;
221         struct iic *iic = NULL;
222
223         for (dn = NULL; (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
224                 compatible = (char *)get_property(dn, "compatible", NULL);
225
226                 if (!compatible) {
227                         printk(KERN_WARNING "no compatible property found !\n");
228                         continue;
229                 }
230
231                 if (strstr(compatible, "IBM,CBEA-Internal-Interrupt-Controller"))
232                         regs = (unsigned long *)get_property(dn,"reg", NULL);
233                 else
234                         continue;
235
236                 if (!regs)
237                         printk(KERN_WARNING "IIC: no reg property\n");
238
239                 np = (unsigned int *)get_property(dn, "ibm,interrupt-server-ranges", NULL);
240
241                 if (!np) {
242                         printk(KERN_WARNING "IIC: CPU association not found\n");
243                         iic->regs = NULL;
244                         iic->target_id = 0xff;
245                         return -ENODEV;
246                 }
247
248                 iic = &per_cpu(iic, np[0]);
249                 iic->regs = ioremap(regs[0], sizeof(struct cbe_iic_thread_regs));
250                 iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
251                 printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
252
253                 iic = &per_cpu(iic, np[1]);
254                 iic->regs = ioremap(regs[2], sizeof(struct cbe_iic_thread_regs));
255                 iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
256                 printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
257
258                 found++;
259         }
260
261         if (found)
262                 return 0;
263         else
264                 return -ENODEV;
265 }
266
267 #ifdef CONFIG_SMP
268
269 /* Use the highest interrupt priorities for IPI */
270 static inline int iic_ipi_to_irq(int ipi)
271 {
272         return IIC_IPI_OFFSET + IIC_NUM_IPIS - 1 - ipi;
273 }
274
275 static inline int iic_irq_to_ipi(int irq)
276 {
277         return IIC_NUM_IPIS - 1 - (irq - IIC_IPI_OFFSET);
278 }
279
280 void iic_setup_cpu(void)
281 {
282         out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
283 }
284
285 void iic_cause_IPI(int cpu, int mesg)
286 {
287         out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
288 }
289
290 u8 iic_get_target_id(int cpu)
291 {
292         return per_cpu(iic, cpu).target_id;
293 }
294 EXPORT_SYMBOL_GPL(iic_get_target_id);
295
296 static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
297 {
298         smp_message_recv(iic_irq_to_ipi(irq), regs);
299         return IRQ_HANDLED;
300 }
301
302 static void iic_request_ipi(int ipi, const char *name)
303 {
304         int irq;
305
306         irq = iic_ipi_to_irq(ipi);
307         /* IPIs are marked IRQF_DISABLED as they must run with irqs
308          * disabled */
309         get_irq_desc(irq)->chip = &iic_pic;
310         get_irq_desc(irq)->status |= IRQ_PER_CPU;
311         request_irq(irq, iic_ipi_action, IRQF_DISABLED, name, NULL);
312 }
313
314 void iic_request_IPIs(void)
315 {
316         iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
317         iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
318 #ifdef CONFIG_DEBUGGER
319         iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
320 #endif /* CONFIG_DEBUGGER */
321 }
322 #endif /* CONFIG_SMP */
323
324 static void iic_setup_spe_handlers(void)
325 {
326         int be, isrc;
327
328         /* Assume two threads per BE are present */
329         for (be=0; be < num_present_cpus() / 2; be++) {
330                 for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
331                         int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
332                         get_irq_desc(irq)->chip = &iic_pic;
333                 }
334         }
335 }
336
337 void iic_init_IRQ(void)
338 {
339         int cpu, irq_offset;
340         struct iic *iic;
341
342         if (setup_iic() < 0)
343                 setup_iic_hardcoded();
344
345         irq_offset = 0;
346         for_each_possible_cpu(cpu) {
347                 iic = &per_cpu(iic, cpu);
348                 if (iic->regs)
349                         out_be64(&iic->regs->prio, 0xff);
350         }
351         iic_setup_spe_handlers();
352 }