powerpc/mm: Bring hugepage PTE accessor functions back into sync with normal accessors
[linux-2.6.git] / arch / powerpc / mm / hash_utils_64.c
1 /*
2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3  *   {mikejc|engebret}@us.ibm.com
4  *
5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6  *
7  * SMP scalability work:
8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9  * 
10  *    Module name: htab.c
11  *
12  *    Description:
13  *      PowerPC Hashed Page Table functions
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License
17  * as published by the Free Software Foundation; either version
18  * 2 of the License, or (at your option) any later version.
19  */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
35
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/mmu.h>
39 #include <asm/mmu_context.h>
40 #include <asm/page.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
45 #include <asm/prom.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
48 #include <asm/io.h>
49 #include <asm/eeh.h>
50 #include <asm/tlb.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/spu.h>
55 #include <asm/udbg.h>
56
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62
63 #ifdef DEBUG_LOW
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #else
66 #define DBG_LOW(fmt...)
67 #endif
68
69 #define KB (1024)
70 #define MB (1024*KB)
71 #define GB (1024L*MB)
72
73 /*
74  * Note:  pte   --> Linux PTE
75  *        HPTE  --> PowerPC Hashed Page Table Entry
76  *
77  * Execution context:
78  *   htab_initialize is called with the MMU off (of course), but
79  *   the kernel has been copied down to zero so it can directly
80  *   reference global data.  At this point it is very difficult
81  *   to print debug info.
82  *
83  */
84
85 #ifdef CONFIG_U3_DART
86 extern unsigned long dart_tablebase;
87 #endif /* CONFIG_U3_DART */
88
89 static unsigned long _SDR1;
90 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91
92 struct hash_pte *htab_address;
93 unsigned long htab_size_bytes;
94 unsigned long htab_hash_mask;
95 int mmu_linear_psize = MMU_PAGE_4K;
96 int mmu_virtual_psize = MMU_PAGE_4K;
97 int mmu_vmalloc_psize = MMU_PAGE_4K;
98 #ifdef CONFIG_SPARSEMEM_VMEMMAP
99 int mmu_vmemmap_psize = MMU_PAGE_4K;
100 #endif
101 int mmu_io_psize = MMU_PAGE_4K;
102 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
104 u16 mmu_slb_size = 64;
105 #ifdef CONFIG_HUGETLB_PAGE
106 unsigned int HPAGE_SHIFT;
107 #endif
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions;
110 #endif
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8 *linear_map_hash_slots;
113 static unsigned long linear_map_hash_count;
114 static DEFINE_SPINLOCK(linear_map_hash_lock);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
116
117 /* There are definitions of page sizes arrays to be used when none
118  * is provided by the firmware.
119  */
120
121 /* Pre-POWER4 CPUs (4k pages only)
122  */
123 static struct mmu_psize_def mmu_psize_defaults_old[] = {
124         [MMU_PAGE_4K] = {
125                 .shift  = 12,
126                 .sllp   = 0,
127                 .penc   = 0,
128                 .avpnm  = 0,
129                 .tlbiel = 0,
130         },
131 };
132
133 /* POWER4, GPUL, POWER5
134  *
135  * Support for 16Mb large pages
136  */
137 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
138         [MMU_PAGE_4K] = {
139                 .shift  = 12,
140                 .sllp   = 0,
141                 .penc   = 0,
142                 .avpnm  = 0,
143                 .tlbiel = 1,
144         },
145         [MMU_PAGE_16M] = {
146                 .shift  = 24,
147                 .sllp   = SLB_VSID_L,
148                 .penc   = 0,
149                 .avpnm  = 0x1UL,
150                 .tlbiel = 0,
151         },
152 };
153
154 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
155 {
156         unsigned long rflags = pteflags & 0x1fa;
157
158         /* _PAGE_EXEC -> NOEXEC */
159         if ((pteflags & _PAGE_EXEC) == 0)
160                 rflags |= HPTE_R_N;
161
162         /* PP bits. PAGE_USER is already PP bit 0x2, so we only
163          * need to add in 0x1 if it's a read-only user page
164          */
165         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
166                                          (pteflags & _PAGE_DIRTY)))
167                 rflags |= 1;
168
169         /* Always add C */
170         return rflags | HPTE_R_C;
171 }
172
173 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
174                       unsigned long pstart, unsigned long prot,
175                       int psize, int ssize)
176 {
177         unsigned long vaddr, paddr;
178         unsigned int step, shift;
179         int ret = 0;
180
181         shift = mmu_psize_defs[psize].shift;
182         step = 1 << shift;
183
184         prot = htab_convert_pte_flags(prot);
185
186         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
187             vstart, vend, pstart, prot, psize, ssize);
188
189         for (vaddr = vstart, paddr = pstart; vaddr < vend;
190              vaddr += step, paddr += step) {
191                 unsigned long hash, hpteg;
192                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
193                 unsigned long va = hpt_va(vaddr, vsid, ssize);
194                 unsigned long tprot = prot;
195
196                 /* Make kernel text executable */
197                 if (overlaps_kernel_text(vaddr, vaddr + step))
198                         tprot &= ~HPTE_R_N;
199
200                 hash = hpt_hash(va, shift, ssize);
201                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
202
203                 BUG_ON(!ppc_md.hpte_insert);
204                 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
205                                          HPTE_V_BOLTED, psize, ssize);
206
207                 if (ret < 0)
208                         break;
209 #ifdef CONFIG_DEBUG_PAGEALLOC
210                 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
211                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
212 #endif /* CONFIG_DEBUG_PAGEALLOC */
213         }
214         return ret < 0 ? ret : 0;
215 }
216
217 #ifdef CONFIG_MEMORY_HOTPLUG
218 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
219                       int psize, int ssize)
220 {
221         unsigned long vaddr;
222         unsigned int step, shift;
223
224         shift = mmu_psize_defs[psize].shift;
225         step = 1 << shift;
226
227         if (!ppc_md.hpte_removebolted) {
228                 printk(KERN_WARNING "Platform doesn't implement "
229                                 "hpte_removebolted\n");
230                 return -EINVAL;
231         }
232
233         for (vaddr = vstart; vaddr < vend; vaddr += step)
234                 ppc_md.hpte_removebolted(vaddr, psize, ssize);
235
236         return 0;
237 }
238 #endif /* CONFIG_MEMORY_HOTPLUG */
239
240 static int __init htab_dt_scan_seg_sizes(unsigned long node,
241                                          const char *uname, int depth,
242                                          void *data)
243 {
244         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
245         u32 *prop;
246         unsigned long size = 0;
247
248         /* We are scanning "cpu" nodes only */
249         if (type == NULL || strcmp(type, "cpu") != 0)
250                 return 0;
251
252         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
253                                           &size);
254         if (prop == NULL)
255                 return 0;
256         for (; size >= 4; size -= 4, ++prop) {
257                 if (prop[0] == 40) {
258                         DBG("1T segment support detected\n");
259                         cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
260                         return 1;
261                 }
262         }
263         cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
264         return 0;
265 }
266
267 static void __init htab_init_seg_sizes(void)
268 {
269         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
270 }
271
272 static int __init htab_dt_scan_page_sizes(unsigned long node,
273                                           const char *uname, int depth,
274                                           void *data)
275 {
276         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
277         u32 *prop;
278         unsigned long size = 0;
279
280         /* We are scanning "cpu" nodes only */
281         if (type == NULL || strcmp(type, "cpu") != 0)
282                 return 0;
283
284         prop = (u32 *)of_get_flat_dt_prop(node,
285                                           "ibm,segment-page-sizes", &size);
286         if (prop != NULL) {
287                 DBG("Page sizes from device-tree:\n");
288                 size /= 4;
289                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
290                 while(size > 0) {
291                         unsigned int shift = prop[0];
292                         unsigned int slbenc = prop[1];
293                         unsigned int lpnum = prop[2];
294                         unsigned int lpenc = 0;
295                         struct mmu_psize_def *def;
296                         int idx = -1;
297
298                         size -= 3; prop += 3;
299                         while(size > 0 && lpnum) {
300                                 if (prop[0] == shift)
301                                         lpenc = prop[1];
302                                 prop += 2; size -= 2;
303                                 lpnum--;
304                         }
305                         switch(shift) {
306                         case 0xc:
307                                 idx = MMU_PAGE_4K;
308                                 break;
309                         case 0x10:
310                                 idx = MMU_PAGE_64K;
311                                 break;
312                         case 0x14:
313                                 idx = MMU_PAGE_1M;
314                                 break;
315                         case 0x18:
316                                 idx = MMU_PAGE_16M;
317                                 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
318                                 break;
319                         case 0x22:
320                                 idx = MMU_PAGE_16G;
321                                 break;
322                         }
323                         if (idx < 0)
324                                 continue;
325                         def = &mmu_psize_defs[idx];
326                         def->shift = shift;
327                         if (shift <= 23)
328                                 def->avpnm = 0;
329                         else
330                                 def->avpnm = (1 << (shift - 23)) - 1;
331                         def->sllp = slbenc;
332                         def->penc = lpenc;
333                         /* We don't know for sure what's up with tlbiel, so
334                          * for now we only set it for 4K and 64K pages
335                          */
336                         if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
337                                 def->tlbiel = 1;
338                         else
339                                 def->tlbiel = 0;
340
341                         DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
342                             "tlbiel=%d, penc=%d\n",
343                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
344                             def->penc);
345                 }
346                 return 1;
347         }
348         return 0;
349 }
350
351 #ifdef CONFIG_HUGETLB_PAGE
352 /* Scan for 16G memory blocks that have been set aside for huge pages
353  * and reserve those blocks for 16G huge pages.
354  */
355 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
356                                         const char *uname, int depth,
357                                         void *data) {
358         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
359         unsigned long *addr_prop;
360         u32 *page_count_prop;
361         unsigned int expected_pages;
362         long unsigned int phys_addr;
363         long unsigned int block_size;
364
365         /* We are scanning "memory" nodes only */
366         if (type == NULL || strcmp(type, "memory") != 0)
367                 return 0;
368
369         /* This property is the log base 2 of the number of virtual pages that
370          * will represent this memory block. */
371         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
372         if (page_count_prop == NULL)
373                 return 0;
374         expected_pages = (1 << page_count_prop[0]);
375         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
376         if (addr_prop == NULL)
377                 return 0;
378         phys_addr = addr_prop[0];
379         block_size = addr_prop[1];
380         if (block_size != (16 * GB))
381                 return 0;
382         printk(KERN_INFO "Huge page(16GB) memory: "
383                         "addr = 0x%lX size = 0x%lX pages = %d\n",
384                         phys_addr, block_size, expected_pages);
385         if (phys_addr + (16 * GB) <= lmb_end_of_DRAM()) {
386                 lmb_reserve(phys_addr, block_size * expected_pages);
387                 add_gpage(phys_addr, block_size, expected_pages);
388         }
389         return 0;
390 }
391 #endif /* CONFIG_HUGETLB_PAGE */
392
393 static void __init htab_init_page_sizes(void)
394 {
395         int rc;
396
397         /* Default to 4K pages only */
398         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
399                sizeof(mmu_psize_defaults_old));
400
401         /*
402          * Try to find the available page sizes in the device-tree
403          */
404         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
405         if (rc != 0)  /* Found */
406                 goto found;
407
408         /*
409          * Not in the device-tree, let's fallback on known size
410          * list for 16M capable GP & GR
411          */
412         if (cpu_has_feature(CPU_FTR_16M_PAGE))
413                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
414                        sizeof(mmu_psize_defaults_gp));
415  found:
416 #ifndef CONFIG_DEBUG_PAGEALLOC
417         /*
418          * Pick a size for the linear mapping. Currently, we only support
419          * 16M, 1M and 4K which is the default
420          */
421         if (mmu_psize_defs[MMU_PAGE_16M].shift)
422                 mmu_linear_psize = MMU_PAGE_16M;
423         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
424                 mmu_linear_psize = MMU_PAGE_1M;
425 #endif /* CONFIG_DEBUG_PAGEALLOC */
426
427 #ifdef CONFIG_PPC_64K_PAGES
428         /*
429          * Pick a size for the ordinary pages. Default is 4K, we support
430          * 64K for user mappings and vmalloc if supported by the processor.
431          * We only use 64k for ioremap if the processor
432          * (and firmware) support cache-inhibited large pages.
433          * If not, we use 4k and set mmu_ci_restrictions so that
434          * hash_page knows to switch processes that use cache-inhibited
435          * mappings to 4k pages.
436          */
437         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
438                 mmu_virtual_psize = MMU_PAGE_64K;
439                 mmu_vmalloc_psize = MMU_PAGE_64K;
440                 if (mmu_linear_psize == MMU_PAGE_4K)
441                         mmu_linear_psize = MMU_PAGE_64K;
442                 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
443                         /*
444                          * Don't use 64k pages for ioremap on pSeries, since
445                          * that would stop us accessing the HEA ethernet.
446                          */
447                         if (!machine_is(pseries))
448                                 mmu_io_psize = MMU_PAGE_64K;
449                 } else
450                         mmu_ci_restrictions = 1;
451         }
452 #endif /* CONFIG_PPC_64K_PAGES */
453
454 #ifdef CONFIG_SPARSEMEM_VMEMMAP
455         /* We try to use 16M pages for vmemmap if that is supported
456          * and we have at least 1G of RAM at boot
457          */
458         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
459             lmb_phys_mem_size() >= 0x40000000)
460                 mmu_vmemmap_psize = MMU_PAGE_16M;
461         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
462                 mmu_vmemmap_psize = MMU_PAGE_64K;
463         else
464                 mmu_vmemmap_psize = MMU_PAGE_4K;
465 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
466
467         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
468                "virtual = %d, io = %d"
469 #ifdef CONFIG_SPARSEMEM_VMEMMAP
470                ", vmemmap = %d"
471 #endif
472                "\n",
473                mmu_psize_defs[mmu_linear_psize].shift,
474                mmu_psize_defs[mmu_virtual_psize].shift,
475                mmu_psize_defs[mmu_io_psize].shift
476 #ifdef CONFIG_SPARSEMEM_VMEMMAP
477                ,mmu_psize_defs[mmu_vmemmap_psize].shift
478 #endif
479                );
480
481 #ifdef CONFIG_HUGETLB_PAGE
482         /* Reserve 16G huge page memory sections for huge pages */
483         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
484 #endif /* CONFIG_HUGETLB_PAGE */
485 }
486
487 static int __init htab_dt_scan_pftsize(unsigned long node,
488                                        const char *uname, int depth,
489                                        void *data)
490 {
491         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
492         u32 *prop;
493
494         /* We are scanning "cpu" nodes only */
495         if (type == NULL || strcmp(type, "cpu") != 0)
496                 return 0;
497
498         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
499         if (prop != NULL) {
500                 /* pft_size[0] is the NUMA CEC cookie */
501                 ppc64_pft_size = prop[1];
502                 return 1;
503         }
504         return 0;
505 }
506
507 static unsigned long __init htab_get_table_size(void)
508 {
509         unsigned long mem_size, rnd_mem_size, pteg_count, psize;
510
511         /* If hash size isn't already provided by the platform, we try to
512          * retrieve it from the device-tree. If it's not there neither, we
513          * calculate it now based on the total RAM size
514          */
515         if (ppc64_pft_size == 0)
516                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
517         if (ppc64_pft_size)
518                 return 1UL << ppc64_pft_size;
519
520         /* round mem_size up to next power of 2 */
521         mem_size = lmb_phys_mem_size();
522         rnd_mem_size = 1UL << __ilog2(mem_size);
523         if (rnd_mem_size < mem_size)
524                 rnd_mem_size <<= 1;
525
526         /* # pages / 2 */
527         psize = mmu_psize_defs[mmu_virtual_psize].shift;
528         pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
529
530         return pteg_count << 7;
531 }
532
533 #ifdef CONFIG_MEMORY_HOTPLUG
534 void create_section_mapping(unsigned long start, unsigned long end)
535 {
536         BUG_ON(htab_bolt_mapping(start, end, __pa(start),
537                                  pgprot_val(PAGE_KERNEL), mmu_linear_psize,
538                                  mmu_kernel_ssize));
539 }
540
541 int remove_section_mapping(unsigned long start, unsigned long end)
542 {
543         return htab_remove_mapping(start, end, mmu_linear_psize,
544                         mmu_kernel_ssize);
545 }
546 #endif /* CONFIG_MEMORY_HOTPLUG */
547
548 static inline void make_bl(unsigned int *insn_addr, void *func)
549 {
550         unsigned long funcp = *((unsigned long *)func);
551         int offset = funcp - (unsigned long)insn_addr;
552
553         *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
554         flush_icache_range((unsigned long)insn_addr, 4+
555                            (unsigned long)insn_addr);
556 }
557
558 static void __init htab_finish_init(void)
559 {
560         extern unsigned int *htab_call_hpte_insert1;
561         extern unsigned int *htab_call_hpte_insert2;
562         extern unsigned int *htab_call_hpte_remove;
563         extern unsigned int *htab_call_hpte_updatepp;
564
565 #ifdef CONFIG_PPC_HAS_HASH_64K
566         extern unsigned int *ht64_call_hpte_insert1;
567         extern unsigned int *ht64_call_hpte_insert2;
568         extern unsigned int *ht64_call_hpte_remove;
569         extern unsigned int *ht64_call_hpte_updatepp;
570
571         make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
572         make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
573         make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
574         make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
575 #endif /* CONFIG_PPC_HAS_HASH_64K */
576
577         make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
578         make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
579         make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
580         make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
581 }
582
583 static void __init htab_initialize(void)
584 {
585         unsigned long table;
586         unsigned long pteg_count;
587         unsigned long prot;
588         unsigned long base = 0, size = 0, limit;
589         int i;
590
591         DBG(" -> htab_initialize()\n");
592
593         /* Initialize segment sizes */
594         htab_init_seg_sizes();
595
596         /* Initialize page sizes */
597         htab_init_page_sizes();
598
599         if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
600                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
601                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
602                 printk(KERN_INFO "Using 1TB segments\n");
603         }
604
605         /*
606          * Calculate the required size of the htab.  We want the number of
607          * PTEGs to equal one half the number of real pages.
608          */ 
609         htab_size_bytes = htab_get_table_size();
610         pteg_count = htab_size_bytes >> 7;
611
612         htab_hash_mask = pteg_count - 1;
613
614         if (firmware_has_feature(FW_FEATURE_LPAR)) {
615                 /* Using a hypervisor which owns the htab */
616                 htab_address = NULL;
617                 _SDR1 = 0; 
618         } else {
619                 /* Find storage for the HPT.  Must be contiguous in
620                  * the absolute address space. On cell we want it to be
621                  * in the first 2 Gig so we can use it for IOMMU hacks.
622                  */
623                 if (machine_is(cell))
624                         limit = 0x80000000;
625                 else
626                         limit = 0;
627
628                 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
629
630                 DBG("Hash table allocated at %lx, size: %lx\n", table,
631                     htab_size_bytes);
632
633                 htab_address = abs_to_virt(table);
634
635                 /* htab absolute addr + encoded htabsize */
636                 _SDR1 = table + __ilog2(pteg_count) - 11;
637
638                 /* Initialize the HPT with no entries */
639                 memset((void *)table, 0, htab_size_bytes);
640
641                 /* Set SDR1 */
642                 mtspr(SPRN_SDR1, _SDR1);
643         }
644
645         prot = pgprot_val(PAGE_KERNEL);
646
647 #ifdef CONFIG_DEBUG_PAGEALLOC
648         linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
649         linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
650                                                     1, lmb.rmo_size));
651         memset(linear_map_hash_slots, 0, linear_map_hash_count);
652 #endif /* CONFIG_DEBUG_PAGEALLOC */
653
654         /* On U3 based machines, we need to reserve the DART area and
655          * _NOT_ map it to avoid cache paradoxes as it's remapped non
656          * cacheable later on
657          */
658
659         /* create bolted the linear mapping in the hash table */
660         for (i=0; i < lmb.memory.cnt; i++) {
661                 base = (unsigned long)__va(lmb.memory.region[i].base);
662                 size = lmb.memory.region[i].size;
663
664                 DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
665                     base, size, prot);
666
667 #ifdef CONFIG_U3_DART
668                 /* Do not map the DART space. Fortunately, it will be aligned
669                  * in such a way that it will not cross two lmb regions and
670                  * will fit within a single 16Mb page.
671                  * The DART space is assumed to be a full 16Mb region even if
672                  * we only use 2Mb of that space. We will use more of it later
673                  * for AGP GART. We have to use a full 16Mb large page.
674                  */
675                 DBG("DART base: %lx\n", dart_tablebase);
676
677                 if (dart_tablebase != 0 && dart_tablebase >= base
678                     && dart_tablebase < (base + size)) {
679                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
680                         if (base != dart_tablebase)
681                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
682                                                         __pa(base), prot,
683                                                         mmu_linear_psize,
684                                                         mmu_kernel_ssize));
685                         if ((base + size) > dart_table_end)
686                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
687                                                         base + size,
688                                                         __pa(dart_table_end),
689                                                          prot,
690                                                          mmu_linear_psize,
691                                                          mmu_kernel_ssize));
692                         continue;
693                 }
694 #endif /* CONFIG_U3_DART */
695                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
696                                 prot, mmu_linear_psize, mmu_kernel_ssize));
697        }
698
699         /*
700          * If we have a memory_limit and we've allocated TCEs then we need to
701          * explicitly map the TCE area at the top of RAM. We also cope with the
702          * case that the TCEs start below memory_limit.
703          * tce_alloc_start/end are 16MB aligned so the mapping should work
704          * for either 4K or 16MB pages.
705          */
706         if (tce_alloc_start) {
707                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
708                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
709
710                 if (base + size >= tce_alloc_start)
711                         tce_alloc_start = base + size + 1;
712
713                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
714                                          __pa(tce_alloc_start), prot,
715                                          mmu_linear_psize, mmu_kernel_ssize));
716         }
717
718         htab_finish_init();
719
720         DBG(" <- htab_initialize()\n");
721 }
722 #undef KB
723 #undef MB
724
725 void __init early_init_mmu(void)
726 {
727         /* Setup initial STAB address in the PACA */
728         get_paca()->stab_real = __pa((u64)&initial_stab);
729         get_paca()->stab_addr = (u64)&initial_stab;
730
731         /* Initialize the MMU Hash table and create the linear mapping
732          * of memory. Has to be done before stab/slb initialization as
733          * this is currently where the page size encoding is obtained
734          */
735         htab_initialize();
736
737         /* Initialize stab / SLB management except on iSeries
738          */
739         if (cpu_has_feature(CPU_FTR_SLB))
740                 slb_initialize();
741         else if (!firmware_has_feature(FW_FEATURE_ISERIES))
742                 stab_initialize(get_paca()->stab_real);
743 }
744
745 #ifdef CONFIG_SMP
746 void __cpuinit early_init_mmu_secondary(void)
747 {
748         /* Initialize hash table for that CPU */
749         if (!firmware_has_feature(FW_FEATURE_LPAR))
750                 mtspr(SPRN_SDR1, _SDR1);
751
752         /* Initialize STAB/SLB. We use a virtual address as it works
753          * in real mode on pSeries and we want a virutal address on
754          * iSeries anyway
755          */
756         if (cpu_has_feature(CPU_FTR_SLB))
757                 slb_initialize();
758         else
759                 stab_initialize(get_paca()->stab_addr);
760 }
761 #endif /* CONFIG_SMP */
762
763 /*
764  * Called by asm hashtable.S for doing lazy icache flush
765  */
766 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
767 {
768         struct page *page;
769
770         if (!pfn_valid(pte_pfn(pte)))
771                 return pp;
772
773         page = pte_page(pte);
774
775         /* page is dirty */
776         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
777                 if (trap == 0x400) {
778                         flush_dcache_icache_page(page);
779                         set_bit(PG_arch_1, &page->flags);
780                 } else
781                         pp |= HPTE_R_N;
782         }
783         return pp;
784 }
785
786 #ifdef CONFIG_PPC_MM_SLICES
787 unsigned int get_paca_psize(unsigned long addr)
788 {
789         unsigned long index, slices;
790
791         if (addr < SLICE_LOW_TOP) {
792                 slices = get_paca()->context.low_slices_psize;
793                 index = GET_LOW_SLICE_INDEX(addr);
794         } else {
795                 slices = get_paca()->context.high_slices_psize;
796                 index = GET_HIGH_SLICE_INDEX(addr);
797         }
798         return (slices >> (index * 4)) & 0xF;
799 }
800
801 #else
802 unsigned int get_paca_psize(unsigned long addr)
803 {
804         return get_paca()->context.user_psize;
805 }
806 #endif
807
808 /*
809  * Demote a segment to using 4k pages.
810  * For now this makes the whole process use 4k pages.
811  */
812 #ifdef CONFIG_PPC_64K_PAGES
813 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
814 {
815         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
816                 return;
817         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
818 #ifdef CONFIG_SPU_BASE
819         spu_flush_all_slbs(mm);
820 #endif
821         if (get_paca_psize(addr) != MMU_PAGE_4K) {
822                 get_paca()->context = mm->context;
823                 slb_flush_and_rebolt();
824         }
825 }
826 #endif /* CONFIG_PPC_64K_PAGES */
827
828 #ifdef CONFIG_PPC_SUBPAGE_PROT
829 /*
830  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
831  * Userspace sets the subpage permissions using the subpage_prot system call.
832  *
833  * Result is 0: full permissions, _PAGE_RW: read-only,
834  * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
835  */
836 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
837 {
838         struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
839         u32 spp = 0;
840         u32 **sbpm, *sbpp;
841
842         if (ea >= spt->maxaddr)
843                 return 0;
844         if (ea < 0x100000000) {
845                 /* addresses below 4GB use spt->low_prot */
846                 sbpm = spt->low_prot;
847         } else {
848                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
849                 if (!sbpm)
850                         return 0;
851         }
852         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
853         if (!sbpp)
854                 return 0;
855         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
856
857         /* extract 2-bit bitfield for this 4k subpage */
858         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
859
860         /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
861         spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
862         return spp;
863 }
864
865 #else /* CONFIG_PPC_SUBPAGE_PROT */
866 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
867 {
868         return 0;
869 }
870 #endif
871
872 /* Result code is:
873  *  0 - handled
874  *  1 - normal page fault
875  * -1 - critical hash insertion error
876  * -2 - access not permitted by subpage protection mechanism
877  */
878 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
879 {
880         void *pgdir;
881         unsigned long vsid;
882         struct mm_struct *mm;
883         pte_t *ptep;
884         unsigned hugeshift;
885         const struct cpumask *tmp;
886         int rc, user_region = 0, local = 0;
887         int psize, ssize;
888
889         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
890                 ea, access, trap);
891
892         if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
893                 DBG_LOW(" out of pgtable range !\n");
894                 return 1;
895         }
896
897         /* Get region & vsid */
898         switch (REGION_ID(ea)) {
899         case USER_REGION_ID:
900                 user_region = 1;
901                 mm = current->mm;
902                 if (! mm) {
903                         DBG_LOW(" user region with no mm !\n");
904                         return 1;
905                 }
906                 psize = get_slice_psize(mm, ea);
907                 ssize = user_segment_size(ea);
908                 vsid = get_vsid(mm->context.id, ea, ssize);
909                 break;
910         case VMALLOC_REGION_ID:
911                 mm = &init_mm;
912                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
913                 if (ea < VMALLOC_END)
914                         psize = mmu_vmalloc_psize;
915                 else
916                         psize = mmu_io_psize;
917                 ssize = mmu_kernel_ssize;
918                 break;
919         default:
920                 /* Not a valid range
921                  * Send the problem up to do_page_fault 
922                  */
923                 return 1;
924         }
925         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
926
927         /* Get pgdir */
928         pgdir = mm->pgd;
929         if (pgdir == NULL)
930                 return 1;
931
932         /* Check CPU locality */
933         tmp = cpumask_of(smp_processor_id());
934         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
935                 local = 1;
936
937 #ifndef CONFIG_PPC_64K_PAGES
938         /* If we use 4K pages and our psize is not 4K, then we might
939          * be hitting a special driver mapping, and need to align the
940          * address before we fetch the PTE.
941          *
942          * It could also be a hugepage mapping, in which case this is
943          * not necessary, but it's not harmful, either.
944          */
945         if (psize != MMU_PAGE_4K)
946                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
947 #endif /* CONFIG_PPC_64K_PAGES */
948
949         /* Get PTE and page size from page tables */
950         ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
951         if (ptep == NULL || !pte_present(*ptep)) {
952                 DBG_LOW(" no PTE !\n");
953                 return 1;
954         }
955
956 #ifdef CONFIG_HUGETLB_PAGE
957         if (hugeshift)
958                 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
959                                         ssize, hugeshift, psize);
960 #endif /* CONFIG_HUGETLB_PAGE */
961
962 #ifndef CONFIG_PPC_64K_PAGES
963         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
964 #else
965         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
966                 pte_val(*(ptep + PTRS_PER_PTE)));
967 #endif
968         /* Pre-check access permissions (will be re-checked atomically
969          * in __hash_page_XX but this pre-check is a fast path
970          */
971         if (access & ~pte_val(*ptep)) {
972                 DBG_LOW(" no access !\n");
973                 return 1;
974         }
975
976         /* Do actual hashing */
977 #ifdef CONFIG_PPC_64K_PAGES
978         /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
979         if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
980                 demote_segment_4k(mm, ea);
981                 psize = MMU_PAGE_4K;
982         }
983
984         /* If this PTE is non-cacheable and we have restrictions on
985          * using non cacheable large pages, then we switch to 4k
986          */
987         if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
988             (pte_val(*ptep) & _PAGE_NO_CACHE)) {
989                 if (user_region) {
990                         demote_segment_4k(mm, ea);
991                         psize = MMU_PAGE_4K;
992                 } else if (ea < VMALLOC_END) {
993                         /*
994                          * some driver did a non-cacheable mapping
995                          * in vmalloc space, so switch vmalloc
996                          * to 4k pages
997                          */
998                         printk(KERN_ALERT "Reducing vmalloc segment "
999                                "to 4kB pages because of "
1000                                "non-cacheable mapping\n");
1001                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1002 #ifdef CONFIG_SPU_BASE
1003                         spu_flush_all_slbs(mm);
1004 #endif
1005                 }
1006         }
1007         if (user_region) {
1008                 if (psize != get_paca_psize(ea)) {
1009                         get_paca()->context = mm->context;
1010                         slb_flush_and_rebolt();
1011                 }
1012         } else if (get_paca()->vmalloc_sllp !=
1013                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1014                 get_paca()->vmalloc_sllp =
1015                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1016                 slb_vmalloc_update();
1017         }
1018 #endif /* CONFIG_PPC_64K_PAGES */
1019
1020 #ifdef CONFIG_PPC_HAS_HASH_64K
1021         if (psize == MMU_PAGE_64K)
1022                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1023         else
1024 #endif /* CONFIG_PPC_HAS_HASH_64K */
1025         {
1026                 int spp = subpage_protection(pgdir, ea);
1027                 if (access & spp)
1028                         rc = -2;
1029                 else
1030                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1031                                             local, ssize, spp);
1032         }
1033
1034 #ifndef CONFIG_PPC_64K_PAGES
1035         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1036 #else
1037         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1038                 pte_val(*(ptep + PTRS_PER_PTE)));
1039 #endif
1040         DBG_LOW(" -> rc=%d\n", rc);
1041         return rc;
1042 }
1043 EXPORT_SYMBOL_GPL(hash_page);
1044
1045 void hash_preload(struct mm_struct *mm, unsigned long ea,
1046                   unsigned long access, unsigned long trap)
1047 {
1048         unsigned long vsid;
1049         void *pgdir;
1050         pte_t *ptep;
1051         unsigned long flags;
1052         int local = 0;
1053         int ssize;
1054
1055         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1056
1057 #ifdef CONFIG_PPC_MM_SLICES
1058         /* We only prefault standard pages for now */
1059         if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1060                 return;
1061 #endif
1062
1063         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1064                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1065
1066         /* Get Linux PTE if available */
1067         pgdir = mm->pgd;
1068         if (pgdir == NULL)
1069                 return;
1070         ptep = find_linux_pte(pgdir, ea);
1071         if (!ptep)
1072                 return;
1073
1074 #ifdef CONFIG_PPC_64K_PAGES
1075         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1076          * a 64K kernel), then we don't preload, hash_page() will take
1077          * care of it once we actually try to access the page.
1078          * That way we don't have to duplicate all of the logic for segment
1079          * page size demotion here
1080          */
1081         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1082                 return;
1083 #endif /* CONFIG_PPC_64K_PAGES */
1084
1085         /* Get VSID */
1086         ssize = user_segment_size(ea);
1087         vsid = get_vsid(mm->context.id, ea, ssize);
1088
1089         /* Hash doesn't like irqs */
1090         local_irq_save(flags);
1091
1092         /* Is that local to this CPU ? */
1093         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1094                 local = 1;
1095
1096         /* Hash it in */
1097 #ifdef CONFIG_PPC_HAS_HASH_64K
1098         if (mm->context.user_psize == MMU_PAGE_64K)
1099                 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1100         else
1101 #endif /* CONFIG_PPC_HAS_HASH_64K */
1102                 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1103                                subpage_protection(pgdir, ea));
1104
1105         local_irq_restore(flags);
1106 }
1107
1108 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1109  *          do not forget to update the assembly call site !
1110  */
1111 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1112                      int local)
1113 {
1114         unsigned long hash, index, shift, hidx, slot;
1115
1116         DBG_LOW("flush_hash_page(va=%016x)\n", va);
1117         pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1118                 hash = hpt_hash(va, shift, ssize);
1119                 hidx = __rpte_to_hidx(pte, index);
1120                 if (hidx & _PTEIDX_SECONDARY)
1121                         hash = ~hash;
1122                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1123                 slot += hidx & _PTEIDX_GROUP_IX;
1124                 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1125                 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1126         } pte_iterate_hashed_end();
1127 }
1128
1129 void flush_hash_range(unsigned long number, int local)
1130 {
1131         if (ppc_md.flush_hash_range)
1132                 ppc_md.flush_hash_range(number, local);
1133         else {
1134                 int i;
1135                 struct ppc64_tlb_batch *batch =
1136                         &__get_cpu_var(ppc64_tlb_batch);
1137
1138                 for (i = 0; i < number; i++)
1139                         flush_hash_page(batch->vaddr[i], batch->pte[i],
1140                                         batch->psize, batch->ssize, local);
1141         }
1142 }
1143
1144 /*
1145  * low_hash_fault is called when we the low level hash code failed
1146  * to instert a PTE due to an hypervisor error
1147  */
1148 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1149 {
1150         if (user_mode(regs)) {
1151 #ifdef CONFIG_PPC_SUBPAGE_PROT
1152                 if (rc == -2)
1153                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1154                 else
1155 #endif
1156                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1157         } else
1158                 bad_page_fault(regs, address, SIGBUS);
1159 }
1160
1161 #ifdef CONFIG_DEBUG_PAGEALLOC
1162 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1163 {
1164         unsigned long hash, hpteg;
1165         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1166         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1167         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1168         int ret;
1169
1170         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1171         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1172
1173         ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1174                                  mode, HPTE_V_BOLTED,
1175                                  mmu_linear_psize, mmu_kernel_ssize);
1176         BUG_ON (ret < 0);
1177         spin_lock(&linear_map_hash_lock);
1178         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1179         linear_map_hash_slots[lmi] = ret | 0x80;
1180         spin_unlock(&linear_map_hash_lock);
1181 }
1182
1183 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1184 {
1185         unsigned long hash, hidx, slot;
1186         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1187         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1188
1189         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1190         spin_lock(&linear_map_hash_lock);
1191         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1192         hidx = linear_map_hash_slots[lmi] & 0x7f;
1193         linear_map_hash_slots[lmi] = 0;
1194         spin_unlock(&linear_map_hash_lock);
1195         if (hidx & _PTEIDX_SECONDARY)
1196                 hash = ~hash;
1197         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1198         slot += hidx & _PTEIDX_GROUP_IX;
1199         ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1200 }
1201
1202 void kernel_map_pages(struct page *page, int numpages, int enable)
1203 {
1204         unsigned long flags, vaddr, lmi;
1205         int i;
1206
1207         local_irq_save(flags);
1208         for (i = 0; i < numpages; i++, page++) {
1209                 vaddr = (unsigned long)page_address(page);
1210                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1211                 if (lmi >= linear_map_hash_count)
1212                         continue;
1213                 if (enable)
1214                         kernel_map_linear_page(vaddr, lmi);
1215                 else
1216                         kernel_unmap_linear_page(vaddr, lmi);
1217         }
1218         local_irq_restore(flags);
1219 }
1220 #endif /* CONFIG_DEBUG_PAGEALLOC */