32e10f588c1d40e316332bad0126d0a795b0af07
[linux-2.6.git] / arch / powerpc / boot / dts / mpc8315erdb.dts
1 /*
2  * MPC8315E RDB Device Tree Source
3  *
4  * Copyright 2007 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         compatible = "fsl,mpc8315erdb";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 serial0 = &serial0;
23                 serial1 = &serial1;
24                 pci0 = &pci0;
25                 pci1 = &pci1;
26                 pci2 = &pci2;
27         };
28
29         cpus {
30                 #address-cells = <1>;
31                 #size-cells = <0>;
32
33                 PowerPC,8315@0 {
34                         device_type = "cpu";
35                         reg = <0x0>;
36                         d-cache-line-size = <32>;
37                         i-cache-line-size = <32>;
38                         d-cache-size = <16384>;
39                         i-cache-size = <16384>;
40                         timebase-frequency = <0>;       // from bootloader
41                         bus-frequency = <0>;            // from bootloader
42                         clock-frequency = <0>;          // from bootloader
43                 };
44         };
45
46         memory {
47                 device_type = "memory";
48                 reg = <0x00000000 0x08000000>;  // 128MB at 0
49         };
50
51         localbus@e0005000 {
52                 #address-cells = <2>;
53                 #size-cells = <1>;
54                 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
55                 reg = <0xe0005000 0x1000>;
56                 interrupts = <77 0x8>;
57                 interrupt-parent = <&ipic>;
58
59                 // CS0 and CS1 are swapped when
60                 // booting from nand, but the
61                 // addresses are the same.
62                 ranges = <0x0 0x0 0xfe000000 0x00800000
63                           0x1 0x0 0xe0600000 0x00002000
64                           0x2 0x0 0xf0000000 0x00020000
65                           0x3 0x0 0xfa000000 0x00008000>;
66
67                 flash@0,0 {
68                         #address-cells = <1>;
69                         #size-cells = <1>;
70                         compatible = "cfi-flash";
71                         reg = <0x0 0x0 0x800000>;
72                         bank-width = <2>;
73                         device-width = <1>;
74                 };
75
76                 nand@1,0 {
77                         #address-cells = <1>;
78                         #size-cells = <1>;
79                         compatible = "fsl,mpc8315-fcm-nand",
80                                      "fsl,elbc-fcm-nand";
81                         reg = <0x1 0x0 0x2000>;
82
83                         u-boot@0 {
84                                 reg = <0x0 0x100000>;
85                                 read-only;
86                         };
87
88                         kernel@100000 {
89                                 reg = <0x100000 0x300000>;
90                         };
91                         fs@400000 {
92                                 reg = <0x400000 0x1c00000>;
93                         };
94                 };
95         };
96
97         immr@e0000000 {
98                 #address-cells = <1>;
99                 #size-cells = <1>;
100                 device_type = "soc";
101                 compatible = "fsl,mpc8315-immr", "simple-bus";
102                 ranges = <0 0xe0000000 0x00100000>;
103                 reg = <0xe0000000 0x00000200>;
104                 bus-frequency = <0>;
105
106                 wdt@200 {
107                         device_type = "watchdog";
108                         compatible = "mpc83xx_wdt";
109                         reg = <0x200 0x100>;
110                 };
111
112                 i2c@3000 {
113                         #address-cells = <1>;
114                         #size-cells = <0>;
115                         cell-index = <0>;
116                         compatible = "fsl-i2c";
117                         reg = <0x3000 0x100>;
118                         interrupts = <14 0x8>;
119                         interrupt-parent = <&ipic>;
120                         dfsrr;
121                         rtc@68 {
122                                 compatible = "dallas,ds1339";
123                                 reg = <0x68>;
124                         };
125
126                         mcu_pio: mcu@a {
127                                 #gpio-cells = <2>;
128                                 compatible = "fsl,mc9s08qg8-mpc8315erdb",
129                                              "fsl,mcu-mpc8349emitx";
130                                 reg = <0x0a>;
131                                 gpio-controller;
132                         };
133                 };
134
135                 spi@7000 {
136                         cell-index = <0>;
137                         compatible = "fsl,spi";
138                         reg = <0x7000 0x1000>;
139                         interrupts = <16 0x8>;
140                         interrupt-parent = <&ipic>;
141                         mode = "cpu";
142                 };
143
144                 dma@82a8 {
145                         #address-cells = <1>;
146                         #size-cells = <1>;
147                         compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
148                         reg = <0x82a8 4>;
149                         ranges = <0 0x8100 0x1a8>;
150                         interrupt-parent = <&ipic>;
151                         interrupts = <71 8>;
152                         cell-index = <0>;
153                         dma-channel@0 {
154                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
155                                 reg = <0 0x80>;
156                                 cell-index = <0>;
157                                 interrupt-parent = <&ipic>;
158                                 interrupts = <71 8>;
159                         };
160                         dma-channel@80 {
161                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
162                                 reg = <0x80 0x80>;
163                                 cell-index = <1>;
164                                 interrupt-parent = <&ipic>;
165                                 interrupts = <71 8>;
166                         };
167                         dma-channel@100 {
168                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
169                                 reg = <0x100 0x80>;
170                                 cell-index = <2>;
171                                 interrupt-parent = <&ipic>;
172                                 interrupts = <71 8>;
173                         };
174                         dma-channel@180 {
175                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
176                                 reg = <0x180 0x28>;
177                                 cell-index = <3>;
178                                 interrupt-parent = <&ipic>;
179                                 interrupts = <71 8>;
180                         };
181                 };
182
183                 usb@23000 {
184                         compatible = "fsl-usb2-dr";
185                         reg = <0x23000 0x1000>;
186                         #address-cells = <1>;
187                         #size-cells = <0>;
188                         interrupt-parent = <&ipic>;
189                         interrupts = <38 0x8>;
190                         phy_type = "utmi";
191                 };
192
193                 enet0: ethernet@24000 {
194                         #address-cells = <1>;
195                         #size-cells = <1>;
196                         cell-index = <0>;
197                         device_type = "network";
198                         model = "eTSEC";
199                         compatible = "gianfar";
200                         reg = <0x24000 0x1000>;
201                         ranges = <0x0 0x24000 0x1000>;
202                         local-mac-address = [ 00 00 00 00 00 00 ];
203                         interrupts = <32 0x8 33 0x8 34 0x8>;
204                         interrupt-parent = <&ipic>;
205                         tbi-handle = <&tbi0>;
206                         phy-handle = < &phy0 >;
207
208                         mdio@520 {
209                                 #address-cells = <1>;
210                                 #size-cells = <0>;
211                                 compatible = "fsl,gianfar-mdio";
212                                 reg = <0x520 0x20>;
213
214                                 phy0: ethernet-phy@0 {
215                                         interrupt-parent = <&ipic>;
216                                         interrupts = <20 0x8>;
217                                         reg = <0x0>;
218                                         device_type = "ethernet-phy";
219                                 };
220
221                                 phy1: ethernet-phy@1 {
222                                         interrupt-parent = <&ipic>;
223                                         interrupts = <19 0x8>;
224                                         reg = <0x1>;
225                                         device_type = "ethernet-phy";
226                                 };
227
228                                 tbi0: tbi-phy@11 {
229                                         reg = <0x11>;
230                                         device_type = "tbi-phy";
231                                 };
232                         };
233                 };
234
235                 enet1: ethernet@25000 {
236                         #address-cells = <1>;
237                         #size-cells = <1>;
238                         cell-index = <1>;
239                         device_type = "network";
240                         model = "eTSEC";
241                         compatible = "gianfar";
242                         reg = <0x25000 0x1000>;
243                         ranges = <0x0 0x25000 0x1000>;
244                         local-mac-address = [ 00 00 00 00 00 00 ];
245                         interrupts = <35 0x8 36 0x8 37 0x8>;
246                         interrupt-parent = <&ipic>;
247                         tbi-handle = <&tbi1>;
248                         phy-handle = < &phy1 >;
249
250                         mdio@520 {
251                                 #address-cells = <1>;
252                                 #size-cells = <0>;
253                                 compatible = "fsl,gianfar-tbi";
254                                 reg = <0x520 0x20>;
255
256                                 tbi1: tbi-phy@11 {
257                                         reg = <0x11>;
258                                         device_type = "tbi-phy";
259                                 };
260                         };
261                 };
262
263                 serial0: serial@4500 {
264                         cell-index = <0>;
265                         device_type = "serial";
266                         compatible = "ns16550";
267                         reg = <0x4500 0x100>;
268                         clock-frequency = <133333333>;
269                         interrupts = <9 0x8>;
270                         interrupt-parent = <&ipic>;
271                 };
272
273                 serial1: serial@4600 {
274                         cell-index = <1>;
275                         device_type = "serial";
276                         compatible = "ns16550";
277                         reg = <0x4600 0x100>;
278                         clock-frequency = <133333333>;
279                         interrupts = <10 0x8>;
280                         interrupt-parent = <&ipic>;
281                 };
282
283                 crypto@30000 {
284                         compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
285                                      "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
286                                      "fsl,sec2.0";
287                         reg = <0x30000 0x10000>;
288                         interrupts = <11 0x8>;
289                         interrupt-parent = <&ipic>;
290                         fsl,num-channels = <4>;
291                         fsl,channel-fifo-len = <24>;
292                         fsl,exec-units-mask = <0x97c>;
293                         fsl,descriptor-types-mask = <0x3ab0abf>;
294                 };
295
296                 sata@18000 {
297                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
298                         reg = <0x18000 0x1000>;
299                         cell-index = <1>;
300                         interrupts = <44 0x8>;
301                         interrupt-parent = <&ipic>;
302                 };
303
304                 sata@19000 {
305                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
306                         reg = <0x19000 0x1000>;
307                         cell-index = <2>;
308                         interrupts = <45 0x8>;
309                         interrupt-parent = <&ipic>;
310                 };
311
312                 /* IPIC
313                  * interrupts cell = <intr #, sense>
314                  * sense values match linux IORESOURCE_IRQ_* defines:
315                  * sense == 8: Level, low assertion
316                  * sense == 2: Edge, high-to-low change
317                  */
318                 ipic: interrupt-controller@700 {
319                         interrupt-controller;
320                         #address-cells = <0>;
321                         #interrupt-cells = <2>;
322                         reg = <0x700 0x100>;
323                         device_type = "ipic";
324                 };
325
326                 ipic-msi@7c0 {
327                         compatible = "fsl,ipic-msi";
328                         reg = <0x7c0 0x40>;
329                         msi-available-ranges = <0 0x100>;
330                         interrupts = <0x43 0x8
331                                       0x4  0x8
332                                       0x51 0x8
333                                       0x52 0x8
334                                       0x56 0x8
335                                       0x57 0x8
336                                       0x58 0x8
337                                       0x59 0x8>;
338                         interrupt-parent = < &ipic >;
339                 };
340         };
341
342         pci0: pci@e0008500 {
343                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
344                 interrupt-map = <
345                                 /* IDSEL 0x0E -mini PCI */
346                                  0x7000 0x0 0x0 0x1 &ipic 18 0x8
347                                  0x7000 0x0 0x0 0x2 &ipic 18 0x8
348                                  0x7000 0x0 0x0 0x3 &ipic 18 0x8
349                                  0x7000 0x0 0x0 0x4 &ipic 18 0x8
350
351                                 /* IDSEL 0x0F -mini PCI */
352                                  0x7800 0x0 0x0 0x1 &ipic 17 0x8
353                                  0x7800 0x0 0x0 0x2 &ipic 17 0x8
354                                  0x7800 0x0 0x0 0x3 &ipic 17 0x8
355                                  0x7800 0x0 0x0 0x4 &ipic 17 0x8
356
357                                 /* IDSEL 0x10 - PCI slot */
358                                  0x8000 0x0 0x0 0x1 &ipic 48 0x8
359                                  0x8000 0x0 0x0 0x2 &ipic 17 0x8
360                                  0x8000 0x0 0x0 0x3 &ipic 48 0x8
361                                  0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
362                 interrupt-parent = <&ipic>;
363                 interrupts = <66 0x8>;
364                 bus-range = <0x0 0x0>;
365                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
366                           0x42000000 0 0x80000000 0x80000000 0 0x10000000
367                           0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
368                 clock-frequency = <66666666>;
369                 #interrupt-cells = <1>;
370                 #size-cells = <2>;
371                 #address-cells = <3>;
372                 reg = <0xe0008500 0x100         /* internal registers */
373                        0xe0008300 0x8>;         /* config space access registers */
374                 compatible = "fsl,mpc8349-pci";
375                 device_type = "pci";
376         };
377
378         pci1: pcie@e0009000 {
379                 #address-cells = <3>;
380                 #size-cells = <2>;
381                 #interrupt-cells = <1>;
382                 device_type = "pci";
383                 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
384                 reg = <0xe0009000 0x00001000>;
385                 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
386                           0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
387                 bus-range = <0 255>;
388                 interrupt-map-mask = <0xf800 0 0 7>;
389                 interrupt-map = <0 0 0 1 &ipic 1 8
390                                  0 0 0 2 &ipic 1 8
391                                  0 0 0 3 &ipic 1 8
392                                  0 0 0 4 &ipic 1 8>;
393                 clock-frequency = <0>;
394
395                 pcie@0 {
396                         #address-cells = <3>;
397                         #size-cells = <2>;
398                         device_type = "pci";
399                         reg = <0 0 0 0 0>;
400                         ranges = <0x02000000 0 0xa0000000
401                                   0x02000000 0 0xa0000000
402                                   0 0x10000000
403                                   0x01000000 0 0x00000000
404                                   0x01000000 0 0x00000000
405                                   0 0x00800000>;
406                 };
407         };
408
409         pci2: pcie@e000a000 {
410                 #address-cells = <3>;
411                 #size-cells = <2>;
412                 #interrupt-cells = <1>;
413                 device_type = "pci";
414                 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
415                 reg = <0xe000a000 0x00001000>;
416                 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
417                           0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
418                 bus-range = <0 255>;
419                 interrupt-map-mask = <0xf800 0 0 7>;
420                 interrupt-map = <0 0 0 1 &ipic 2 8
421                                  0 0 0 2 &ipic 2 8
422                                  0 0 0 3 &ipic 2 8
423                                  0 0 0 4 &ipic 2 8>;
424                 clock-frequency = <0>;
425
426                 pcie@0 {
427                         #address-cells = <3>;
428                         #size-cells = <2>;
429                         device_type = "pci";
430                         reg = <0 0 0 0 0>;
431                         ranges = <0x02000000 0 0xc0000000
432                                   0x02000000 0 0xc0000000
433                                   0 0x10000000
434                                   0x01000000 0 0x00000000
435                                   0x01000000 0 0x00000000
436                                   0 0x00800000>;
437                 };
438         };
439 };