c2b8dbfab79e6dc1e4fa5f4b365a06d6f103776f
[linux-2.6.git] / arch / powerpc / boot / dts / mpc5121ads.dts
1 /*
2  * MPC5121E ADS Device Tree Source
3  *
4  * Copyright 2007,2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "mpc5121ads";
16         compatible = "fsl,mpc5121ads";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 pci = &pci;
22         };
23
24         cpus {
25                 #address-cells = <1>;
26                 #size-cells = <0>;
27
28                 PowerPC,5121@0 {
29                         device_type = "cpu";
30                         reg = <0>;
31                         d-cache-line-size = <0x20>;     // 32 bytes
32                         i-cache-line-size = <0x20>;     // 32 bytes
33                         d-cache-size = <0x8000>;        // L1, 32K
34                         i-cache-size = <0x8000>;        // L1, 32K
35                         timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
36                         bus-frequency = <198000000>;    // 198 MHz csb bus
37                         clock-frequency = <396000000>;  // 396 MHz ppc core
38                 };
39         };
40
41         memory {
42                 device_type = "memory";
43                 reg = <0x00000000 0x10000000>;  // 256MB at 0
44         };
45
46         mbx@20000000 {
47                 compatible = "fsl,mpc5121-mbx";
48                 reg = <0x20000000 0x4000>;
49                 interrupts = <66 0x8>;
50                 interrupt-parent = < &ipic >;
51         };
52
53         sram@30000000 {
54                 compatible = "fsl,mpc5121-sram";
55                 reg = <0x30000000 0x20000>;             // 128K at 0x30000000
56         };
57
58         nfc@40000000 {
59                 compatible = "fsl,mpc5121-nfc";
60                 reg = <0x40000000 0x100000>;    // 1M at 0x40000000
61                 interrupts = <6 8>;
62                 interrupt-parent = < &ipic >;
63                 #address-cells = <1>;
64                 #size-cells = <1>;
65                 bank-width = <1>;
66                 // ADS has two Hynix 512MB Nand flash chips in a single
67                 // stacked package .
68                 chips = <2>;
69                 nand0@0 {
70                         label = "nand0";
71                         reg = <0x00000000 0x02000000>;  // first 32 MB of chip 0
72                 };
73                 nand1@20000000 {
74                         label = "nand1";
75                         reg = <0x20000000 0x02000000>;  // first 32 MB of chip 1
76                 };
77         };
78
79         localbus@80000020 {
80                 compatible = "fsl,mpc5121-localbus";
81                 #address-cells = <2>;
82                 #size-cells = <1>;
83                 reg = <0x80000020 0x40>;
84
85                 ranges = <0x0 0x0 0xfc000000 0x04000000
86                           0x2 0x0 0x82000000 0x00008000>;
87
88                 flash@0,0 {
89                         compatible = "cfi-flash";
90                         reg = <0 0x0 0x4000000>;
91                         #address-cells = <1>;
92                         #size-cells = <1>;
93                         bank-width = <4>;
94                         device-width = <2>;
95                         protected@0 {
96                                 label = "protected";
97                                 reg = <0x00000000 0x00040000>;  // first sector is protected
98                                 read-only;
99                         };
100                         filesystem@40000 {
101                                 label = "filesystem";
102                                 reg = <0x00040000 0x03c00000>;  // 60M for filesystem
103                         };
104                         kernel@3c40000 {
105                                 label = "kernel";
106                                 reg = <0x03c40000 0x00280000>;  // 2.5M for kernel
107                         };
108                         device-tree@3ec0000 {
109                                 label = "device-tree";
110                                 reg = <0x03ec0000 0x00040000>;  // one sector for device tree
111                         };
112                         u-boot@3f00000 {
113                                 label = "u-boot";
114                                 reg = <0x03f00000 0x00100000>;  // 1M for u-boot
115                                 read-only;
116                         };
117                 };
118
119                 board-control@2,0 {
120                         compatible = "fsl,mpc5121ads-cpld";
121                         reg = <0x2 0x0 0x8000>;
122                 };
123
124                 cpld_pic: pic@2,a {
125                         compatible = "fsl,mpc5121ads-cpld-pic";
126                         interrupt-controller;
127                         #interrupt-cells = <2>;
128                         reg = <0x2 0xa 0x5>;
129                         interrupt-parent = < &ipic >;
130                         // irq routing
131                         //      all irqs but touch screen are routed to irq0 (ipic 48)
132                         //      touch screen is statically routed to irq1 (ipic 17)
133                         //      so don't use it here
134                         interrupts = <48 0x8>;
135                 };
136         };
137
138         soc@80000000 {
139                 compatible = "fsl,mpc5121-immr";
140                 #address-cells = <1>;
141                 #size-cells = <1>;
142                 #interrupt-cells = <2>;
143                 ranges = <0x0 0x80000000 0x400000>;
144                 reg = <0x80000000 0x400000>;
145                 bus-frequency = <66000000>;     // 66 MHz ips bus
146
147
148                 // IPIC
149                 // interrupts cell = <intr #, sense>
150                 // sense values match linux IORESOURCE_IRQ_* defines:
151                 // sense == 8: Level, low assertion
152                 // sense == 2: Edge, high-to-low change
153                 //
154                 ipic: interrupt-controller@c00 {
155                         compatible = "fsl,mpc5121-ipic", "fsl,ipic";
156                         interrupt-controller;
157                         #address-cells = <0>;
158                         #interrupt-cells = <2>;
159                         reg = <0xc00 0x100>;
160                 };
161
162                 rtc@a00 {       // Real time clock
163                         compatible = "fsl,mpc5121-rtc";
164                         reg = <0xa00 0x100>;
165                         interrupts = <79 0x8 80 0x8>;
166                         interrupt-parent = < &ipic >;
167                 };
168
169                 clock@f00 {     // Clock control
170                         compatible = "fsl,mpc5121-clock";
171                         reg = <0xf00 0x100>;
172                 };
173
174                 pmc@1000{  //Power Management Controller
175                         compatible = "fsl,mpc5121-pmc";
176                         reg = <0x1000 0x100>;
177                         interrupts = <83 0x2>;
178                         interrupt-parent = < &ipic >;
179                 };
180
181                 gpio@1100 {
182                         compatible = "fsl,mpc5121-gpio";
183                         reg = <0x1100 0x100>;
184                         interrupts = <78 0x8>;
185                         interrupt-parent = < &ipic >;
186                 };
187
188                 mscan@1300 {
189                         compatible = "fsl,mpc5121-mscan";
190                         cell-index = <0>;
191                         interrupts = <12 0x8>;
192                         interrupt-parent = < &ipic >;
193                         reg = <0x1300 0x80>;
194                 };
195
196                 mscan@1380 {
197                         compatible = "fsl,mpc5121-mscan";
198                         cell-index = <1>;
199                         interrupts = <13 0x8>;
200                         interrupt-parent = < &ipic >;
201                         reg = <0x1380 0x80>;
202                 };
203
204                 i2c@1700 {
205                         #address-cells = <1>;
206                         #size-cells = <0>;
207                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
208                         cell-index = <0>;
209                         reg = <0x1700 0x20>;
210                         interrupts = <9 0x8>;
211                         interrupt-parent = < &ipic >;
212                         fsl5200-clocking;
213                 };
214
215                 i2c@1720 {
216                         #address-cells = <1>;
217                         #size-cells = <0>;
218                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
219                         cell-index = <1>;
220                         reg = <0x1720 0x20>;
221                         interrupts = <10 0x8>;
222                         interrupt-parent = < &ipic >;
223                         fsl5200-clocking;
224                 };
225
226                 i2c@1740 {
227                         #address-cells = <1>;
228                         #size-cells = <0>;
229                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
230                         cell-index = <2>;
231                         reg = <0x1740 0x20>;
232                         interrupts = <11 0x8>;
233                         interrupt-parent = < &ipic >;
234                         fsl5200-clocking;
235                 };
236
237                 i2ccontrol@1760 {
238                         compatible = "fsl,mpc5121-i2c-ctrl";
239                         reg = <0x1760 0x8>;
240                 };
241
242                 axe@2000 {
243                         compatible = "fsl,mpc5121-axe";
244                         reg = <0x2000 0x100>;
245                         interrupts = <42 0x8>;
246                         interrupt-parent = < &ipic >;
247                 };
248
249                 display@2100 {
250                         compatible = "fsl,mpc5121-diu", "fsl-diu";
251                         reg = <0x2100 0x100>;
252                         interrupts = <64 0x8>;
253                         interrupt-parent = < &ipic >;
254                 };
255
256                 mdio@2800 {
257                         compatible = "fsl,mpc5121-fec-mdio";
258                         reg = <0x2800 0x800>;
259                         #address-cells = <1>;
260                         #size-cells = <0>;
261                         phy: ethernet-phy@0 {
262                                 reg = <1>;
263                                 device_type = "ethernet-phy";
264                         };
265                 };
266
267                 ethernet@2800 {
268                         device_type = "network";
269                         compatible = "fsl,mpc5121-fec";
270                         reg = <0x2800 0x800>;
271                         local-mac-address = [ 00 00 00 00 00 00 ];
272                         interrupts = <4 0x8>;
273                         interrupt-parent = < &ipic >;
274                         phy-handle = < &phy >;
275                         fsl,align-tx-packets = <4>;
276                 };
277
278                 // 5121e has two dr usb modules
279                 // mpc5121_ads only uses USB0
280
281                 // USB1 using external ULPI PHY
282                 //usb@3000 {
283                 //      compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
284                 //      reg = <0x3000 0x1000>;
285                 //      #address-cells = <1>;
286                 //      #size-cells = <0>;
287                 //      interrupt-parent = < &ipic >;
288                 //      interrupts = <43 0x8>;
289                 //      dr_mode = "otg";
290                 //      phy_type = "ulpi";
291                 //      port1;
292                 //};
293
294                 // USB0 using internal UTMI PHY
295                 usb@4000 {
296                         compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
297                         reg = <0x4000 0x1000>;
298                         #address-cells = <1>;
299                         #size-cells = <0>;
300                         interrupt-parent = < &ipic >;
301                         interrupts = <44 0x8>;
302                         dr_mode = "otg";
303                         phy_type = "utmi_wide";
304                         port0;
305                 };
306
307                 // IO control
308                 ioctl@a000 {
309                         compatible = "fsl,mpc5121-ioctl";
310                         reg = <0xA000 0x1000>;
311                 };
312
313                 pata@10200 {
314                         compatible = "fsl,mpc5121-pata";
315                         reg = <0x10200 0x100>;
316                         interrupts = <5 0x8>;
317                         interrupt-parent = < &ipic >;
318                 };
319
320                 // 512x PSCs are not 52xx PSC compatible
321                 // PSC3 serial port A aka ttyPSC0
322                 serial@11300 {
323                         device_type = "serial";
324                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
325                         // Logical port assignment needed until driver
326                         // learns to use aliases
327                         port-number = <0>;
328                         cell-index = <3>;
329                         reg = <0x11300 0x100>;
330                         interrupts = <40 0x8>;
331                         interrupt-parent = < &ipic >;
332                         rx-fifo-size = <16>;
333                         tx-fifo-size = <16>;
334                 };
335
336                 // PSC4 serial port B aka ttyPSC1
337                 serial@11400 {
338                         device_type = "serial";
339                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
340                         // Logical port assignment needed until driver
341                         // learns to use aliases
342                         port-number = <1>;
343                         cell-index = <4>;
344                         reg = <0x11400 0x100>;
345                         interrupts = <40 0x8>;
346                         interrupt-parent = < &ipic >;
347                         rx-fifo-size = <16>;
348                         tx-fifo-size = <16>;
349                 };
350
351                 // PSC5 in ac97 mode
352                 ac97@11500 {
353                         compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
354                         cell-index = <5>;
355                         reg = <0x11500 0x100>;
356                         interrupts = <40 0x8>;
357                         interrupt-parent = < &ipic >;
358                         fsl,mode = "ac97-slave";
359                         rx-fifo-size = <384>;
360                         tx-fifo-size = <384>;
361                 };
362
363                 pscfifo@11f00 {
364                         compatible = "fsl,mpc5121-psc-fifo";
365                         reg = <0x11f00 0x100>;
366                         interrupts = <40 0x8>;
367                         interrupt-parent = < &ipic >;
368                 };
369
370                 dma@14000 {
371                         compatible = "fsl,mpc5121-dma2";
372                         reg = <0x14000 0x1800>;
373                         interrupts = <65 0x8>;
374                         interrupt-parent = < &ipic >;
375                 };
376
377         };
378
379         pci: pci@80008500 {
380                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
381                 interrupt-map = <
382                                 // IDSEL 0x15 - Slot 1 PCI
383                                  0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
384                                  0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
385                                  0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
386                                  0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
387
388                                 // IDSEL 0x16 - Slot 2 MiniPCI
389                                  0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
390                                  0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
391
392                                 // IDSEL 0x17 - Slot 3 MiniPCI
393                                  0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
394                                  0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
395                                 >;
396                 interrupt-parent = < &ipic >;
397                 interrupts = <1 0x8>;
398                 bus-range = <0 0>;
399                 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
400                           0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
401                           0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
402                 clock-frequency = <0>;
403                 #interrupt-cells = <1>;
404                 #size-cells = <2>;
405                 #address-cells = <3>;
406                 reg = <0x80008500 0x100         /* internal registers */
407                        0x80008300 0x8>;         /* config space access registers */
408                 compatible = "fsl,mpc5121-pci";
409                 device_type = "pci";
410         };
411 };