Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-next-2.6
[linux-2.6.git] / arch / powerpc / boot / dts / lite5200.dts
1 /*
2  * Lite5200 board Device Tree Source
3  *
4  * Copyright 2006-2007 Secret Lab Technologies Ltd.
5  * Grant Likely <grant.likely@secretlab.ca>
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  */
12
13 /dts-v1/;
14
15 / {
16         model = "fsl,lite5200";
17         compatible = "fsl,lite5200";
18         #address-cells = <1>;
19         #size-cells = <1>;
20         interrupt-parent = <&mpc5200_pic>;
21
22         cpus {
23                 #address-cells = <1>;
24                 #size-cells = <0>;
25
26                 PowerPC,5200@0 {
27                         device_type = "cpu";
28                         reg = <0>;
29                         d-cache-line-size = <32>;
30                         i-cache-line-size = <32>;
31                         d-cache-size = <0x4000>;        // L1, 16K
32                         i-cache-size = <0x4000>;        // L1, 16K
33                         timebase-frequency = <0>;       // from bootloader
34                         bus-frequency = <0>;            // from bootloader
35                         clock-frequency = <0>;          // from bootloader
36                 };
37         };
38
39         memory {
40                 device_type = "memory";
41                 reg = <0x00000000 0x04000000>;  // 64MB
42         };
43
44         soc5200@f0000000 {
45                 #address-cells = <1>;
46                 #size-cells = <1>;
47                 compatible = "fsl,mpc5200-immr";
48                 ranges = <0 0xf0000000 0x0000c000>;
49                 reg = <0xf0000000 0x00000100>;
50                 bus-frequency = <0>;            // from bootloader
51                 system-frequency = <0>;         // from bootloader
52
53                 cdm@200 {
54                         compatible = "fsl,mpc5200-cdm";
55                         reg = <0x200 0x38>;
56                 };
57
58                 mpc5200_pic: interrupt-controller@500 {
59                         // 5200 interrupts are encoded into two levels;
60                         interrupt-controller;
61                         #interrupt-cells = <3>;
62                         compatible = "fsl,mpc5200-pic";
63                         reg = <0x500 0x80>;
64                 };
65
66                 timer@600 {     // General Purpose Timer
67                         compatible = "fsl,mpc5200-gpt";
68                         reg = <0x600 0x10>;
69                         interrupts = <1 9 0>;
70                         fsl,has-wdt;
71                 };
72
73                 timer@610 {     // General Purpose Timer
74                         compatible = "fsl,mpc5200-gpt";
75                         reg = <0x610 0x10>;
76                         interrupts = <1 10 0>;
77                 };
78
79                 timer@620 {     // General Purpose Timer
80                         compatible = "fsl,mpc5200-gpt";
81                         reg = <0x620 0x10>;
82                         interrupts = <1 11 0>;
83                 };
84
85                 timer@630 {     // General Purpose Timer
86                         compatible = "fsl,mpc5200-gpt";
87                         reg = <0x630 0x10>;
88                         interrupts = <1 12 0>;
89                 };
90
91                 timer@640 {     // General Purpose Timer
92                         compatible = "fsl,mpc5200-gpt";
93                         reg = <0x640 0x10>;
94                         interrupts = <1 13 0>;
95                 };
96
97                 timer@650 {     // General Purpose Timer
98                         compatible = "fsl,mpc5200-gpt";
99                         reg = <0x650 0x10>;
100                         interrupts = <1 14 0>;
101                 };
102
103                 timer@660 {     // General Purpose Timer
104                         compatible = "fsl,mpc5200-gpt";
105                         reg = <0x660 0x10>;
106                         interrupts = <1 15 0>;
107                 };
108
109                 timer@670 {     // General Purpose Timer
110                         compatible = "fsl,mpc5200-gpt";
111                         reg = <0x670 0x10>;
112                         interrupts = <1 16 0>;
113                 };
114
115                 rtc@800 {       // Real time clock
116                         compatible = "fsl,mpc5200-rtc";
117                         reg = <0x800 0x100>;
118                         interrupts = <1 5 0 1 6 0>;
119                 };
120
121                 can@900 {
122                         compatible = "fsl,mpc5200-mscan";
123                         interrupts = <2 17 0>;
124                         reg = <0x900 0x80>;
125                 };
126
127                 can@980 {
128                         compatible = "fsl,mpc5200-mscan";
129                         interrupts = <2 18 0>;
130                         reg = <0x980 0x80>;
131                 };
132
133                 gpio@b00 {
134                         compatible = "fsl,mpc5200-gpio";
135                         reg = <0xb00 0x40>;
136                         interrupts = <1 7 0>;
137                 };
138
139                 gpio@c00 {
140                         compatible = "fsl,mpc5200-gpio-wkup";
141                         reg = <0xc00 0x40>;
142                         interrupts = <1 8 0 0 3 0>;
143                 };
144
145                 spi@f00 {
146                         compatible = "fsl,mpc5200-spi";
147                         reg = <0xf00 0x20>;
148                         interrupts = <2 13 0 2 14 0>;
149                 };
150
151                 usb@1000 {
152                         compatible = "fsl,mpc5200-ohci","ohci-be";
153                         reg = <0x1000 0xff>;
154                         interrupts = <2 6 0>;
155                 };
156
157                 dma-controller@1200 {
158                         compatible = "fsl,mpc5200-bestcomm";
159                         reg = <0x1200 0x80>;
160                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
161                                       3 4 0  3 5 0  3 6 0  3 7 0
162                                       3 8 0  3 9 0  3 10 0  3 11 0
163                                       3 12 0  3 13 0  3 14 0  3 15 0>;
164                 };
165
166                 xlb@1f00 {
167                         compatible = "fsl,mpc5200-xlb";
168                         reg = <0x1f00 0x100>;
169                 };
170
171                 serial@2000 {           // PSC1
172                         compatible = "fsl,mpc5200-psc-uart";
173                         cell-index = <0>;
174                         reg = <0x2000 0x100>;
175                         interrupts = <2 1 0>;
176                 };
177
178                 // PSC2 in ac97 mode example
179                 //ac97@2200 {           // PSC2
180                 //      compatible = "fsl,mpc5200-psc-ac97";
181                 //      cell-index = <1>;
182                 //      reg = <0x2200 0x100>;
183                 //      interrupts = <2 2 0>;
184                 //};
185
186                 // PSC3 in CODEC mode example
187                 //i2s@2400 {            // PSC3
188                 //      compatible = "fsl,mpc5200-psc-i2s";
189                 //      cell-index = <2>;
190                 //      reg = <0x2400 0x100>;
191                 //      interrupts = <2 3 0>;
192                 //};
193
194                 // PSC4 in uart mode example
195                 //serial@2600 {         // PSC4
196                 //      compatible = "fsl,mpc5200-psc-uart";
197                 //      cell-index = <3>;
198                 //      reg = <0x2600 0x100>;
199                 //      interrupts = <2 11 0>;
200                 //};
201
202                 // PSC5 in uart mode example
203                 //serial@2800 {         // PSC5
204                 //      compatible = "fsl,mpc5200-psc-uart";
205                 //      cell-index = <4>;
206                 //      reg = <0x2800 0x100>;
207                 //      interrupts = <2 12 0>;
208                 //};
209
210                 // PSC6 in spi mode example
211                 //spi@2c00 {            // PSC6
212                 //      compatible = "fsl,mpc5200-psc-spi";
213                 //      cell-index = <5>;
214                 //      reg = <0x2c00 0x100>;
215                 //      interrupts = <2 4 0>;
216                 //};
217
218                 ethernet@3000 {
219                         compatible = "fsl,mpc5200-fec";
220                         reg = <0x3000 0x400>;
221                         local-mac-address = [ 00 00 00 00 00 00 ];
222                         interrupts = <2 5 0>;
223                         phy-handle = <&phy0>;
224                 };
225
226                 mdio@3000 {
227                         #address-cells = <1>;
228                         #size-cells = <0>;
229                         compatible = "fsl,mpc5200-mdio";
230                         reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
231                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
232
233                         phy0: ethernet-phy@1 {
234                                 reg = <1>;
235                         };
236                 };
237
238                 ata@3a00 {
239                         compatible = "fsl,mpc5200-ata";
240                         reg = <0x3a00 0x100>;
241                         interrupts = <2 7 0>;
242                 };
243
244                 i2c@3d00 {
245                         #address-cells = <1>;
246                         #size-cells = <0>;
247                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
248                         reg = <0x3d00 0x40>;
249                         interrupts = <2 15 0>;
250                 };
251
252                 i2c@3d40 {
253                         #address-cells = <1>;
254                         #size-cells = <0>;
255                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
256                         reg = <0x3d40 0x40>;
257                         interrupts = <2 16 0>;
258                 };
259                 sram@8000 {
260                         compatible = "fsl,mpc5200-sram";
261                         reg = <0x8000 0x4000>;
262                 };
263         };
264
265         pci@f0000d00 {
266                 #interrupt-cells = <1>;
267                 #size-cells = <2>;
268                 #address-cells = <3>;
269                 device_type = "pci";
270                 compatible = "fsl,mpc5200-pci";
271                 reg = <0xf0000d00 0x100>;
272                 interrupt-map-mask = <0xf800 0 0 7>;
273                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
274                                  0xc000 0 0 2 &mpc5200_pic 0 0 3
275                                  0xc000 0 0 3 &mpc5200_pic 0 0 3
276                                  0xc000 0 0 4 &mpc5200_pic 0 0 3>;
277                 clock-frequency = <0>; // From boot loader
278                 interrupts = <2 8 0 2 9 0 2 10 0>;
279                 bus-range = <0 0>;
280                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
281                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
282                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
283         };
284 };