cee8080aa2454871cae0f54e39f3c5afab2a2773
[linux-2.6.git] / arch / powerpc / boot / dts / cm5200.dts
1 /*
2  * CM5200 board Device Tree Source
3  *
4  * Copyright (C) 2007 Semihalf
5  * Marian Balakowicz <m8@semihalf.com>
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  */
12
13 /dts-v1/;
14
15 / {
16         model = "schindler,cm5200";
17         compatible = "schindler,cm5200";
18         #address-cells = <1>;
19         #size-cells = <1>;
20         interrupt-parent = <&mpc5200_pic>;
21
22         cpus {
23                 #address-cells = <1>;
24                 #size-cells = <0>;
25
26                 PowerPC,5200@0 {
27                         device_type = "cpu";
28                         reg = <0>;
29                         d-cache-line-size = <32>;
30                         i-cache-line-size = <32>;
31                         d-cache-size = <0x4000>;                // L1, 16K
32                         i-cache-size = <0x4000>;                // L1, 16K
33                         timebase-frequency = <0>;       // from bootloader
34                         bus-frequency = <0>;            // from bootloader
35                         clock-frequency = <0>;          // from bootloader
36                 };
37         };
38
39         memory {
40                 device_type = "memory";
41                 reg = <0x00000000 0x04000000>;  // 64MB
42         };
43
44         soc5200@f0000000 {
45                 #address-cells = <1>;
46                 #size-cells = <1>;
47                 compatible = "fsl,mpc5200b-immr";
48                 ranges = <0 0xf0000000 0x0000c000>;
49                 reg = <0xf0000000 0x00000100>;
50                 bus-frequency = <0>;            // from bootloader
51                 system-frequency = <0>;         // from bootloader
52
53                 cdm@200 {
54                         compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55                         reg = <0x200 0x38>;
56                 };
57
58                 mpc5200_pic: interrupt-controller@500 {
59                         // 5200 interrupts are encoded into two levels;
60                         interrupt-controller;
61                         #interrupt-cells = <3>;
62                         compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63                         reg = <0x500 0x80>;
64                 };
65
66                 timer@600 {     // General Purpose Timer
67                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68                         reg = <0x600 0x10>;
69                         interrupts = <1 9 0>;
70                         fsl,has-wdt;
71                 };
72
73                 timer@610 {     // General Purpose Timer
74                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75                         reg = <0x610 0x10>;
76                         interrupts = <1 10 0>;
77                 };
78
79                 timer@620 {     // General Purpose Timer
80                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81                         reg = <0x620 0x10>;
82                         interrupts = <1 11 0>;
83                 };
84
85                 timer@630 {     // General Purpose Timer
86                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87                         reg = <0x630 0x10>;
88                         interrupts = <1 12 0>;
89                 };
90
91                 timer@640 {     // General Purpose Timer
92                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93                         reg = <0x640 0x10>;
94                         interrupts = <1 13 0>;
95                 };
96
97                 timer@650 {     // General Purpose Timer
98                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99                         reg = <0x650 0x10>;
100                         interrupts = <1 14 0>;
101                 };
102
103                 timer@660 {     // General Purpose Timer
104                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105                         reg = <0x660 0x10>;
106                         interrupts = <1 15 0>;
107                 };
108
109                 timer@670 {     // General Purpose Timer
110                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111                         reg = <0x670 0x10>;
112                         interrupts = <1 16 0>;
113                 };
114
115                 rtc@800 {       // Real time clock
116                         compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117                         reg = <0x800 0x100>;
118                         interrupts = <1 5 0 1 6 0>;
119                 };
120
121                 gpio_simple: gpio@b00 {
122                         compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
123                         reg = <0xb00 0x40>;
124                         interrupts = <1 7 0>;
125                         gpio-controller;
126                         #gpio-cells = <2>;
127                 };
128
129                 gpio_wkup: gpio@c00 {
130                         compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
131                         reg = <0xc00 0x40>;
132                         interrupts = <1 8 0 0 3 0>;
133                         gpio-controller;
134                         #gpio-cells = <2>;
135                 };
136
137                 spi@f00 {
138                         compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
139                         reg = <0xf00 0x20>;
140                         interrupts = <2 13 0 2 14 0>;
141                 };
142
143                 usb@1000 {
144                         compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
145                         reg = <0x1000 0xff>;
146                         interrupts = <2 6 0>;
147                 };
148
149                 dma-controller@1200 {
150                         compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
151                         reg = <0x1200 0x80>;
152                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
153                                       3 4 0  3 5 0  3 6 0  3 7 0
154                                       3 8 0  3 9 0  3 10 0  3 11 0
155                                       3 12 0  3 13 0  3 14 0  3 15 0>;
156                 };
157
158                 xlb@1f00 {
159                         compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
160                         reg = <0x1f00 0x100>;
161                 };
162
163                 serial@2000 {           // PSC1
164                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
165                         reg = <0x2000 0x100>;
166                         interrupts = <2 1 0>;
167                 };
168
169                 serial@2200 {           // PSC2
170                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
171                         reg = <0x2200 0x100>;
172                         interrupts = <2 2 0>;
173                 };
174
175                 serial@2400 {           // PSC3
176                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
177                         reg = <0x2400 0x100>;
178                         interrupts = <2 3 0>;
179                 };
180
181                 serial@2c00 {           // PSC6
182                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183                         reg = <0x2c00 0x100>;
184                         interrupts = <2 4 0>;
185                 };
186
187                 ethernet@3000 {
188                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
189                         reg = <0x3000 0x400>;
190                         local-mac-address = [ 00 00 00 00 00 00 ];
191                         interrupts = <2 5 0>;
192                         phy-handle = <&phy0>;
193                 };
194
195                 mdio@3000 {
196                         #address-cells = <1>;
197                         #size-cells = <0>;
198                         compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
199                         reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
200                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
201
202                         phy0: ethernet-phy@0 {
203                                 reg = <0>;
204                         };
205                 };
206
207                 i2c@3d40 {
208                         #address-cells = <1>;
209                         #size-cells = <0>;
210                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
211                         reg = <0x3d40 0x40>;
212                         interrupts = <2 16 0>;
213                         fsl5200-clocking;
214                 };
215
216                 sram@8000 {
217                         compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
218                         reg = <0x8000 0x4000>;
219                 };
220         };
221
222         localbus {
223                 compatible = "fsl,mpc5200b-lpb","simple-bus";
224                 #address-cells = <2>;
225                 #size-cells = <1>;
226                 ranges = <0 0 0xfc000000 0x2000000>;
227
228                 // 16-bit flash device at LocalPlus Bus CS0
229                 flash@0,0 {
230                         compatible = "cfi-flash";
231                         reg = <0 0 0x2000000>;
232                         bank-width = <2>;
233                         device-width = <2>;
234                         #size-cells = <1>;
235                         #address-cells = <1>;
236                 };
237         };
238 };