c215c0d39fae930dfc74d7bfd3db2dd6b53312e1
[linux-2.6.git] / arch / mips / vr41xx / common / icu.c
1 /*
2  *  icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
3  *
4  *  Copyright (C) 2001-2002  MontaVista Software Inc.
5  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6  *  Copyright (C) 2003-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program; if not, write to the Free Software
20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  */
22 /*
23  * Changes:
24  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
25  *  - New creation, NEC VR4122 and VR4131 are supported.
26  *  - Added support for NEC VR4111 and VR4121.
27  *
28  *  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
29  *  - Coped with INTASSIGN of NEC VR4133.
30  */
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
34 #include <linux/irq.h>
35 #include <linux/module.h>
36 #include <linux/smp.h>
37 #include <linux/types.h>
38
39 #include <asm/cpu.h>
40 #include <asm/io.h>
41 #include <asm/vr41xx/irq.h>
42 #include <asm/vr41xx/vr41xx.h>
43
44 static void __iomem *icu1_base;
45 static void __iomem *icu2_base;
46
47 static unsigned char sysint1_assign[16] = {
48         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
49 static unsigned char sysint2_assign[16] = {
50         2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
51
52 #define ICU1_TYPE1_BASE 0x0b000080UL
53 #define ICU2_TYPE1_BASE 0x0b000200UL
54
55 #define ICU1_TYPE2_BASE 0x0f000080UL
56 #define ICU2_TYPE2_BASE 0x0f0000a0UL
57
58 #define ICU1_SIZE       0x20
59 #define ICU2_SIZE       0x1c
60
61 #define SYSINT1REG      0x00
62 #define PIUINTREG       0x02
63 #define INTASSIGN0      0x04
64 #define INTASSIGN1      0x06
65 #define GIUINTLREG      0x08
66 #define DSIUINTREG      0x0a
67 #define MSYSINT1REG     0x0c
68 #define MPIUINTREG      0x0e
69 #define MAIUINTREG      0x10
70 #define MKIUINTREG      0x12
71 #define MGIUINTLREG     0x14
72 #define MDSIUINTREG     0x16
73 #define NMIREG          0x18
74 #define SOFTREG         0x1a
75 #define INTASSIGN2      0x1c
76 #define INTASSIGN3      0x1e
77
78 #define SYSINT2REG      0x00
79 #define GIUINTHREG      0x02
80 #define FIRINTREG       0x04
81 #define MSYSINT2REG     0x06
82 #define MGIUINTHREG     0x08
83 #define MFIRINTREG      0x0a
84 #define PCIINTREG       0x0c
85  #define PCIINT0        0x0001
86 #define SCUINTREG       0x0e
87  #define SCUINT0        0x0001
88 #define CSIINTREG       0x10
89 #define MPCIINTREG      0x12
90 #define MSCUINTREG      0x14
91 #define MCSIINTREG      0x16
92 #define BCUINTREG       0x18
93  #define BCUINTR        0x0001
94 #define MBCUINTREG      0x1a
95
96 #define SYSINT1_IRQ_TO_PIN(x)   ((x) - SYSINT1_IRQ_BASE)        /* Pin 0-15 */
97 #define SYSINT2_IRQ_TO_PIN(x)   ((x) - SYSINT2_IRQ_BASE)        /* Pin 0-15 */
98
99 #define INT_TO_IRQ(x)           ((x) + 2)       /* Int0-4 -> IRQ2-6 */
100
101 #define icu1_read(offset)               readw(icu1_base + (offset))
102 #define icu1_write(offset, value)       writew((value), icu1_base + (offset))
103
104 #define icu2_read(offset)               readw(icu2_base + (offset))
105 #define icu2_write(offset, value)       writew((value), icu2_base + (offset))
106
107 #define INTASSIGN_MAX   4
108 #define INTASSIGN_MASK  0x0007
109
110 static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
111 {
112         uint16_t data;
113
114         data = icu1_read(offset);
115         data |= set;
116         icu1_write(offset, data);
117
118         return data;
119 }
120
121 static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
122 {
123         uint16_t data;
124
125         data = icu1_read(offset);
126         data &= ~clear;
127         icu1_write(offset, data);
128
129         return data;
130 }
131
132 static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
133 {
134         uint16_t data;
135
136         data = icu2_read(offset);
137         data |= set;
138         icu2_write(offset, data);
139
140         return data;
141 }
142
143 static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
144 {
145         uint16_t data;
146
147         data = icu2_read(offset);
148         data &= ~clear;
149         icu2_write(offset, data);
150
151         return data;
152 }
153
154 void vr41xx_enable_piuint(uint16_t mask)
155 {
156         struct irq_desc *desc = irq_desc + PIU_IRQ;
157         unsigned long flags;
158
159         if (current_cpu_data.cputype == CPU_VR4111 ||
160             current_cpu_data.cputype == CPU_VR4121) {
161                 spin_lock_irqsave(&desc->lock, flags);
162                 icu1_set(MPIUINTREG, mask);
163                 spin_unlock_irqrestore(&desc->lock, flags);
164         }
165 }
166
167 EXPORT_SYMBOL(vr41xx_enable_piuint);
168
169 void vr41xx_disable_piuint(uint16_t mask)
170 {
171         struct irq_desc *desc = irq_desc + PIU_IRQ;
172         unsigned long flags;
173
174         if (current_cpu_data.cputype == CPU_VR4111 ||
175             current_cpu_data.cputype == CPU_VR4121) {
176                 spin_lock_irqsave(&desc->lock, flags);
177                 icu1_clear(MPIUINTREG, mask);
178                 spin_unlock_irqrestore(&desc->lock, flags);
179         }
180 }
181
182 EXPORT_SYMBOL(vr41xx_disable_piuint);
183
184 void vr41xx_enable_aiuint(uint16_t mask)
185 {
186         struct irq_desc *desc = irq_desc + AIU_IRQ;
187         unsigned long flags;
188
189         if (current_cpu_data.cputype == CPU_VR4111 ||
190             current_cpu_data.cputype == CPU_VR4121) {
191                 spin_lock_irqsave(&desc->lock, flags);
192                 icu1_set(MAIUINTREG, mask);
193                 spin_unlock_irqrestore(&desc->lock, flags);
194         }
195 }
196
197 EXPORT_SYMBOL(vr41xx_enable_aiuint);
198
199 void vr41xx_disable_aiuint(uint16_t mask)
200 {
201         struct irq_desc *desc = irq_desc + AIU_IRQ;
202         unsigned long flags;
203
204         if (current_cpu_data.cputype == CPU_VR4111 ||
205             current_cpu_data.cputype == CPU_VR4121) {
206                 spin_lock_irqsave(&desc->lock, flags);
207                 icu1_clear(MAIUINTREG, mask);
208                 spin_unlock_irqrestore(&desc->lock, flags);
209         }
210 }
211
212 EXPORT_SYMBOL(vr41xx_disable_aiuint);
213
214 void vr41xx_enable_kiuint(uint16_t mask)
215 {
216         struct irq_desc *desc = irq_desc + KIU_IRQ;
217         unsigned long flags;
218
219         if (current_cpu_data.cputype == CPU_VR4111 ||
220             current_cpu_data.cputype == CPU_VR4121) {
221                 spin_lock_irqsave(&desc->lock, flags);
222                 icu1_set(MKIUINTREG, mask);
223                 spin_unlock_irqrestore(&desc->lock, flags);
224         }
225 }
226
227 EXPORT_SYMBOL(vr41xx_enable_kiuint);
228
229 void vr41xx_disable_kiuint(uint16_t mask)
230 {
231         struct irq_desc *desc = irq_desc + KIU_IRQ;
232         unsigned long flags;
233
234         if (current_cpu_data.cputype == CPU_VR4111 ||
235             current_cpu_data.cputype == CPU_VR4121) {
236                 spin_lock_irqsave(&desc->lock, flags);
237                 icu1_clear(MKIUINTREG, mask);
238                 spin_unlock_irqrestore(&desc->lock, flags);
239         }
240 }
241
242 EXPORT_SYMBOL(vr41xx_disable_kiuint);
243
244 void vr41xx_enable_dsiuint(uint16_t mask)
245 {
246         struct irq_desc *desc = irq_desc + DSIU_IRQ;
247         unsigned long flags;
248
249         spin_lock_irqsave(&desc->lock, flags);
250         icu1_set(MDSIUINTREG, mask);
251         spin_unlock_irqrestore(&desc->lock, flags);
252 }
253
254 EXPORT_SYMBOL(vr41xx_enable_dsiuint);
255
256 void vr41xx_disable_dsiuint(uint16_t mask)
257 {
258         struct irq_desc *desc = irq_desc + DSIU_IRQ;
259         unsigned long flags;
260
261         spin_lock_irqsave(&desc->lock, flags);
262         icu1_clear(MDSIUINTREG, mask);
263         spin_unlock_irqrestore(&desc->lock, flags);
264 }
265
266 EXPORT_SYMBOL(vr41xx_disable_dsiuint);
267
268 void vr41xx_enable_firint(uint16_t mask)
269 {
270         struct irq_desc *desc = irq_desc + FIR_IRQ;
271         unsigned long flags;
272
273         spin_lock_irqsave(&desc->lock, flags);
274         icu2_set(MFIRINTREG, mask);
275         spin_unlock_irqrestore(&desc->lock, flags);
276 }
277
278 EXPORT_SYMBOL(vr41xx_enable_firint);
279
280 void vr41xx_disable_firint(uint16_t mask)
281 {
282         struct irq_desc *desc = irq_desc + FIR_IRQ;
283         unsigned long flags;
284
285         spin_lock_irqsave(&desc->lock, flags);
286         icu2_clear(MFIRINTREG, mask);
287         spin_unlock_irqrestore(&desc->lock, flags);
288 }
289
290 EXPORT_SYMBOL(vr41xx_disable_firint);
291
292 void vr41xx_enable_pciint(void)
293 {
294         struct irq_desc *desc = irq_desc + PCI_IRQ;
295         unsigned long flags;
296
297         if (current_cpu_data.cputype == CPU_VR4122 ||
298             current_cpu_data.cputype == CPU_VR4131 ||
299             current_cpu_data.cputype == CPU_VR4133) {
300                 spin_lock_irqsave(&desc->lock, flags);
301                 icu2_write(MPCIINTREG, PCIINT0);
302                 spin_unlock_irqrestore(&desc->lock, flags);
303         }
304 }
305
306 EXPORT_SYMBOL(vr41xx_enable_pciint);
307
308 void vr41xx_disable_pciint(void)
309 {
310         struct irq_desc *desc = irq_desc + PCI_IRQ;
311         unsigned long flags;
312
313         if (current_cpu_data.cputype == CPU_VR4122 ||
314             current_cpu_data.cputype == CPU_VR4131 ||
315             current_cpu_data.cputype == CPU_VR4133) {
316                 spin_lock_irqsave(&desc->lock, flags);
317                 icu2_write(MPCIINTREG, 0);
318                 spin_unlock_irqrestore(&desc->lock, flags);
319         }
320 }
321
322 EXPORT_SYMBOL(vr41xx_disable_pciint);
323
324 void vr41xx_enable_scuint(void)
325 {
326         struct irq_desc *desc = irq_desc + SCU_IRQ;
327         unsigned long flags;
328
329         if (current_cpu_data.cputype == CPU_VR4122 ||
330             current_cpu_data.cputype == CPU_VR4131 ||
331             current_cpu_data.cputype == CPU_VR4133) {
332                 spin_lock_irqsave(&desc->lock, flags);
333                 icu2_write(MSCUINTREG, SCUINT0);
334                 spin_unlock_irqrestore(&desc->lock, flags);
335         }
336 }
337
338 EXPORT_SYMBOL(vr41xx_enable_scuint);
339
340 void vr41xx_disable_scuint(void)
341 {
342         struct irq_desc *desc = irq_desc + SCU_IRQ;
343         unsigned long flags;
344
345         if (current_cpu_data.cputype == CPU_VR4122 ||
346             current_cpu_data.cputype == CPU_VR4131 ||
347             current_cpu_data.cputype == CPU_VR4133) {
348                 spin_lock_irqsave(&desc->lock, flags);
349                 icu2_write(MSCUINTREG, 0);
350                 spin_unlock_irqrestore(&desc->lock, flags);
351         }
352 }
353
354 EXPORT_SYMBOL(vr41xx_disable_scuint);
355
356 void vr41xx_enable_csiint(uint16_t mask)
357 {
358         struct irq_desc *desc = irq_desc + CSI_IRQ;
359         unsigned long flags;
360
361         if (current_cpu_data.cputype == CPU_VR4122 ||
362             current_cpu_data.cputype == CPU_VR4131 ||
363             current_cpu_data.cputype == CPU_VR4133) {
364                 spin_lock_irqsave(&desc->lock, flags);
365                 icu2_set(MCSIINTREG, mask);
366                 spin_unlock_irqrestore(&desc->lock, flags);
367         }
368 }
369
370 EXPORT_SYMBOL(vr41xx_enable_csiint);
371
372 void vr41xx_disable_csiint(uint16_t mask)
373 {
374         struct irq_desc *desc = irq_desc + CSI_IRQ;
375         unsigned long flags;
376
377         if (current_cpu_data.cputype == CPU_VR4122 ||
378             current_cpu_data.cputype == CPU_VR4131 ||
379             current_cpu_data.cputype == CPU_VR4133) {
380                 spin_lock_irqsave(&desc->lock, flags);
381                 icu2_clear(MCSIINTREG, mask);
382                 spin_unlock_irqrestore(&desc->lock, flags);
383         }
384 }
385
386 EXPORT_SYMBOL(vr41xx_disable_csiint);
387
388 void vr41xx_enable_bcuint(void)
389 {
390         struct irq_desc *desc = irq_desc + BCU_IRQ;
391         unsigned long flags;
392
393         if (current_cpu_data.cputype == CPU_VR4122 ||
394             current_cpu_data.cputype == CPU_VR4131 ||
395             current_cpu_data.cputype == CPU_VR4133) {
396                 spin_lock_irqsave(&desc->lock, flags);
397                 icu2_write(MBCUINTREG, BCUINTR);
398                 spin_unlock_irqrestore(&desc->lock, flags);
399         }
400 }
401
402 EXPORT_SYMBOL(vr41xx_enable_bcuint);
403
404 void vr41xx_disable_bcuint(void)
405 {
406         struct irq_desc *desc = irq_desc + BCU_IRQ;
407         unsigned long flags;
408
409         if (current_cpu_data.cputype == CPU_VR4122 ||
410             current_cpu_data.cputype == CPU_VR4131 ||
411             current_cpu_data.cputype == CPU_VR4133) {
412                 spin_lock_irqsave(&desc->lock, flags);
413                 icu2_write(MBCUINTREG, 0);
414                 spin_unlock_irqrestore(&desc->lock, flags);
415         }
416 }
417
418 EXPORT_SYMBOL(vr41xx_disable_bcuint);
419
420 static unsigned int startup_sysint1_irq(unsigned int irq)
421 {
422         icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
423
424         return 0; /* never anything pending */
425 }
426
427 static void shutdown_sysint1_irq(unsigned int irq)
428 {
429         icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
430 }
431
432 static void enable_sysint1_irq(unsigned int irq)
433 {
434         icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435 }
436
437 #define disable_sysint1_irq     shutdown_sysint1_irq
438 #define ack_sysint1_irq         shutdown_sysint1_irq
439
440 static void end_sysint1_irq(unsigned int irq)
441 {
442         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
443                 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
444 }
445
446 static struct irq_chip sysint1_irq_type = {
447         .typename       = "SYSINT1",
448         .startup        = startup_sysint1_irq,
449         .shutdown       = shutdown_sysint1_irq,
450         .enable         = enable_sysint1_irq,
451         .disable        = disable_sysint1_irq,
452         .ack            = ack_sysint1_irq,
453         .end            = end_sysint1_irq,
454 };
455
456 static unsigned int startup_sysint2_irq(unsigned int irq)
457 {
458         icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459
460         return 0; /* never anything pending */
461 }
462
463 static void shutdown_sysint2_irq(unsigned int irq)
464 {
465         icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
466 }
467
468 static void enable_sysint2_irq(unsigned int irq)
469 {
470         icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
471 }
472
473 #define disable_sysint2_irq     shutdown_sysint2_irq
474 #define ack_sysint2_irq         shutdown_sysint2_irq
475
476 static void end_sysint2_irq(unsigned int irq)
477 {
478         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
479                 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
480 }
481
482 static struct irq_chip sysint2_irq_type = {
483         .typename       = "SYSINT2",
484         .startup        = startup_sysint2_irq,
485         .shutdown       = shutdown_sysint2_irq,
486         .enable         = enable_sysint2_irq,
487         .disable        = disable_sysint2_irq,
488         .ack            = ack_sysint2_irq,
489         .end            = end_sysint2_irq,
490 };
491
492 static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
493 {
494         struct irq_desc *desc = irq_desc + irq;
495         uint16_t intassign0, intassign1;
496         unsigned int pin;
497
498         pin = SYSINT1_IRQ_TO_PIN(irq);
499
500         spin_lock_irq(&desc->lock);
501
502         intassign0 = icu1_read(INTASSIGN0);
503         intassign1 = icu1_read(INTASSIGN1);
504
505         switch (pin) {
506         case 0:
507                 intassign0 &= ~INTASSIGN_MASK;
508                 intassign0 |= (uint16_t)assign;
509                 break;
510         case 1:
511                 intassign0 &= ~(INTASSIGN_MASK << 3);
512                 intassign0 |= (uint16_t)assign << 3;
513                 break;
514         case 2:
515                 intassign0 &= ~(INTASSIGN_MASK << 6);
516                 intassign0 |= (uint16_t)assign << 6;
517                 break;
518         case 3:
519                 intassign0 &= ~(INTASSIGN_MASK << 9);
520                 intassign0 |= (uint16_t)assign << 9;
521                 break;
522         case 8:
523                 intassign0 &= ~(INTASSIGN_MASK << 12);
524                 intassign0 |= (uint16_t)assign << 12;
525                 break;
526         case 9:
527                 intassign1 &= ~INTASSIGN_MASK;
528                 intassign1 |= (uint16_t)assign;
529                 break;
530         case 11:
531                 intassign1 &= ~(INTASSIGN_MASK << 6);
532                 intassign1 |= (uint16_t)assign << 6;
533                 break;
534         case 12:
535                 intassign1 &= ~(INTASSIGN_MASK << 9);
536                 intassign1 |= (uint16_t)assign << 9;
537                 break;
538         default:
539                 return -EINVAL;
540         }
541
542         sysint1_assign[pin] = assign;
543         icu1_write(INTASSIGN0, intassign0);
544         icu1_write(INTASSIGN1, intassign1);
545
546         spin_unlock_irq(&desc->lock);
547
548         return 0;
549 }
550
551 static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
552 {
553         struct irq_desc *desc = irq_desc + irq;
554         uint16_t intassign2, intassign3;
555         unsigned int pin;
556
557         pin = SYSINT2_IRQ_TO_PIN(irq);
558
559         spin_lock_irq(&desc->lock);
560
561         intassign2 = icu1_read(INTASSIGN2);
562         intassign3 = icu1_read(INTASSIGN3);
563
564         switch (pin) {
565         case 0:
566                 intassign2 &= ~INTASSIGN_MASK;
567                 intassign2 |= (uint16_t)assign;
568                 break;
569         case 1:
570                 intassign2 &= ~(INTASSIGN_MASK << 3);
571                 intassign2 |= (uint16_t)assign << 3;
572                 break;
573         case 3:
574                 intassign2 &= ~(INTASSIGN_MASK << 6);
575                 intassign2 |= (uint16_t)assign << 6;
576                 break;
577         case 4:
578                 intassign2 &= ~(INTASSIGN_MASK << 9);
579                 intassign2 |= (uint16_t)assign << 9;
580                 break;
581         case 5:
582                 intassign2 &= ~(INTASSIGN_MASK << 12);
583                 intassign2 |= (uint16_t)assign << 12;
584                 break;
585         case 6:
586                 intassign3 &= ~INTASSIGN_MASK;
587                 intassign3 |= (uint16_t)assign;
588                 break;
589         case 7:
590                 intassign3 &= ~(INTASSIGN_MASK << 3);
591                 intassign3 |= (uint16_t)assign << 3;
592                 break;
593         case 8:
594                 intassign3 &= ~(INTASSIGN_MASK << 6);
595                 intassign3 |= (uint16_t)assign << 6;
596                 break;
597         case 9:
598                 intassign3 &= ~(INTASSIGN_MASK << 9);
599                 intassign3 |= (uint16_t)assign << 9;
600                 break;
601         case 10:
602                 intassign3 &= ~(INTASSIGN_MASK << 12);
603                 intassign3 |= (uint16_t)assign << 12;
604                 break;
605         default:
606                 return -EINVAL;
607         }
608
609         sysint2_assign[pin] = assign;
610         icu1_write(INTASSIGN2, intassign2);
611         icu1_write(INTASSIGN3, intassign3);
612
613         spin_unlock_irq(&desc->lock);
614
615         return 0;
616 }
617
618 int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
619 {
620         int retval = -EINVAL;
621
622         if (current_cpu_data.cputype != CPU_VR4133)
623                 return -EINVAL;
624
625         if (intassign > INTASSIGN_MAX)
626                 return -EINVAL;
627
628         if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST)
629                 retval = set_sysint1_assign(irq, intassign);
630         else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST)
631                 retval = set_sysint2_assign(irq, intassign);
632
633         return retval;
634 }
635
636 EXPORT_SYMBOL(vr41xx_set_intassign);
637
638 static int icu_get_irq(unsigned int irq)
639 {
640         uint16_t pend1, pend2;
641         uint16_t mask1, mask2;
642         int i;
643
644         pend1 = icu1_read(SYSINT1REG);
645         mask1 = icu1_read(MSYSINT1REG);
646
647         pend2 = icu2_read(SYSINT2REG);
648         mask2 = icu2_read(MSYSINT2REG);
649
650         mask1 &= pend1;
651         mask2 &= pend2;
652
653         if (mask1) {
654                 for (i = 0; i < 16; i++) {
655                         if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
656                                 return SYSINT1_IRQ(i);
657                 }
658         }
659
660         if (mask2) {
661                 for (i = 0; i < 16; i++) {
662                         if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
663                                 return SYSINT2_IRQ(i);
664                 }
665         }
666
667         printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
668
669         atomic_inc(&irq_err_count);
670
671         return -1;
672 }
673
674 static int __init vr41xx_icu_init(void)
675 {
676         unsigned long icu1_start, icu2_start;
677         int i;
678
679         switch (current_cpu_data.cputype) {
680         case CPU_VR4111:
681         case CPU_VR4121:
682                 icu1_start = ICU1_TYPE1_BASE;
683                 icu2_start = ICU2_TYPE1_BASE;
684                 break;
685         case CPU_VR4122:
686         case CPU_VR4131:
687         case CPU_VR4133:
688                 icu1_start = ICU1_TYPE2_BASE;
689                 icu2_start = ICU2_TYPE2_BASE;
690                 break;
691         default:
692                 printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
693                 return -ENODEV;
694         }
695
696         if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
697                 return -EBUSY;
698
699         if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
700                 release_mem_region(icu1_start, ICU1_SIZE);
701                 return -EBUSY;
702         }
703
704         icu1_base = ioremap(icu1_start, ICU1_SIZE);
705         if (icu1_base == NULL) {
706                 release_mem_region(icu1_start, ICU1_SIZE);
707                 release_mem_region(icu2_start, ICU2_SIZE);
708                 return -ENOMEM;
709         }
710
711         icu2_base = ioremap(icu2_start, ICU2_SIZE);
712         if (icu2_base == NULL) {
713                 iounmap(icu1_base);
714                 release_mem_region(icu1_start, ICU1_SIZE);
715                 release_mem_region(icu2_start, ICU2_SIZE);
716                 return -ENOMEM;
717         }
718
719         icu1_write(MSYSINT1REG, 0);
720         icu1_write(MGIUINTLREG, 0xffff);
721
722         icu2_write(MSYSINT2REG, 0);
723         icu2_write(MGIUINTHREG, 0xffff);
724
725         for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
726                 irq_desc[i].chip = &sysint1_irq_type;
727
728         for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
729                 irq_desc[i].chip = &sysint2_irq_type;
730
731         cascade_irq(INT0_IRQ, icu_get_irq);
732         cascade_irq(INT1_IRQ, icu_get_irq);
733         cascade_irq(INT2_IRQ, icu_get_irq);
734         cascade_irq(INT3_IRQ, icu_get_irq);
735         cascade_irq(INT4_IRQ, icu_get_irq);
736
737         return 0;
738 }
739
740 core_initcall(vr41xx_icu_init);