[MIPS] IRQ cleanups
[linux-2.6.git] / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_irq.c
1 /*
2  * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
3  *
4  * Toshiba RBTX4927 specific interrupt handlers
5  *
6  * Author: MontaVista Software, Inc.
7  *         source@mvista.com
8  *
9  * Copyright 2001-2002 MontaVista Software Inc.
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the
13  *  Free Software Foundation; either version 2 of the License, or (at your
14  *  option) any later version.
15  *
16  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  *  You should have received a copy of the GNU General Public License along
28  *  with this program; if not, write to the Free Software Foundation, Inc.,
29  *  675 Mass Ave, Cambridge, MA 02139, USA.
30  */
31
32
33 /*
34 IRQ  Device
35 00   RBTX4927-ISA/00
36 01   RBTX4927-ISA/01 PS2/Keyboard
37 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
38 03   RBTX4927-ISA/03
39 04   RBTX4927-ISA/04
40 05   RBTX4927-ISA/05
41 06   RBTX4927-ISA/06
42 07   RBTX4927-ISA/07
43 08   RBTX4927-ISA/08
44 09   RBTX4927-ISA/09
45 10   RBTX4927-ISA/10
46 11   RBTX4927-ISA/11
47 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
48 13   RBTX4927-ISA/13
49 14   RBTX4927-ISA/14 IDE
50 15   RBTX4927-ISA/15
51
52 16   TX4927-CP0/00 Software 0
53 17   TX4927-CP0/01 Software 1
54 18   TX4927-CP0/02 Cascade TX4927-CP0
55 19   TX4927-CP0/03 Multiplexed -- do not use
56 20   TX4927-CP0/04 Multiplexed -- do not use
57 21   TX4927-CP0/05 Multiplexed -- do not use
58 22   TX4927-CP0/06 Multiplexed -- do not use
59 23   TX4927-CP0/07 CPU TIMER
60
61 24   TX4927-PIC/00
62 25   TX4927-PIC/01
63 26   TX4927-PIC/02
64 27   TX4927-PIC/03 Cascade RBTX4927-IOC
65 28   TX4927-PIC/04
66 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
67 30   TX4927-PIC/06
68 31   TX4927-PIC/07
69 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
70 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
71 34   TX4927-PIC/10
72 35   TX4927-PIC/11
73 36   TX4927-PIC/12
74 37   TX4927-PIC/13
75 38   TX4927-PIC/14
76 39   TX4927-PIC/15
77 40   TX4927-PIC/16 TX4927 PCI PCI-C
78 41   TX4927-PIC/17
79 42   TX4927-PIC/18
80 43   TX4927-PIC/19
81 44   TX4927-PIC/20
82 45   TX4927-PIC/21
83 46   TX4927-PIC/22 TX4927 PCI PCI-ERR
84 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
85 48   TX4927-PIC/24
86 49   TX4927-PIC/25
87 50   TX4927-PIC/26
88 51   TX4927-PIC/27
89 52   TX4927-PIC/28
90 53   TX4927-PIC/29
91 54   TX4927-PIC/30
92 55   TX4927-PIC/31
93
94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
98 60 RBTX4927-IOC/04
99 61 RBTX4927-IOC/05
100 62 RBTX4927-IOC/06
101 63 RBTX4927-IOC/07
102
103 NOTES:
104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105 SouthBridge/ISA/pin=0 no pci irq used by this device
106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
108 SouthBridge/PMC/pin=0 no pci irq used by this device
109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
112 */
113
114 #include <linux/init.h>
115 #include <linux/kernel.h>
116 #include <linux/types.h>
117 #include <linux/mm.h>
118 #include <linux/swap.h>
119 #include <linux/ioport.h>
120 #include <linux/sched.h>
121 #include <linux/interrupt.h>
122 #include <linux/pci.h>
123 #include <linux/timex.h>
124 #include <asm/bootinfo.h>
125 #include <asm/page.h>
126 #include <asm/io.h>
127 #include <asm/irq.h>
128 #include <asm/pci.h>
129 #include <asm/processor.h>
130 #include <asm/reboot.h>
131 #include <asm/time.h>
132 #include <asm/wbflush.h>
133 #include <linux/bootmem.h>
134 #include <linux/blkdev.h>
135 #ifdef CONFIG_RTC_DS1742
136 #include <linux/ds1742rtc.h>
137 #endif
138 #ifdef CONFIG_TOSHIBA_FPCIB0
139 #include <asm/tx4927/smsc_fdc37m81x.h>
140 #endif
141 #include <asm/tx4927/toshiba_rbtx4927.h>
142
143
144 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
145
146 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
147 #define TOSHIBA_RBTX4927_IRQ_NONE        0x00000000
148
149 #define TOSHIBA_RBTX4927_IRQ_INFO          ( 1 <<  0 )
150 #define TOSHIBA_RBTX4927_IRQ_WARN          ( 1 <<  1 )
151 #define TOSHIBA_RBTX4927_IRQ_EROR          ( 1 <<  2 )
152
153 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT      ( 1 << 10 )
154 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
155 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
156 #define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ    ( 1 << 16 )
157
158 #define TOSHIBA_RBTX4927_IRQ_ISA_INIT      ( 1 << 20 )
159 #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE    ( 1 << 23 )
160 #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE   ( 1 << 24 )
161 #define TOSHIBA_RBTX4927_IRQ_ISA_MASK      ( 1 << 25 )
162 #define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ    ( 1 << 26 )
163
164 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
165 #endif
166
167
168 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
169 static const u32 toshiba_rbtx4927_irq_debug_flag =
170     (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
171      TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
172 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT
173 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
174 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
175 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
176 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_INIT
177 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
178 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
179 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_MASK
180 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
181     );
182 #endif
183
184
185 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
186 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
187         if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
188         { \
189            char tmp[100]; \
190            sprintf( tmp, str ); \
191            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
192         }
193 #else
194 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
195 #endif
196
197
198
199
200 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG   0
201 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END   7
202
203 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
204 #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
205
206
207 #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
208 #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
209 #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
210
211
212 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
213 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
214 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
215
216 extern int tx4927_using_backplane;
217
218 #ifdef CONFIG_TOSHIBA_FPCIB0
219 extern void enable_8259A_irq(unsigned int irq);
220 extern void disable_8259A_irq(unsigned int irq);
221 extern void mask_and_ack_8259A(unsigned int irq);
222 #endif
223
224 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
225 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
226 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
227
228 #ifdef CONFIG_TOSHIBA_FPCIB0
229 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
230 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
231 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
232 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
233 #endif
234
235 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
236 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
237         .typename = TOSHIBA_RBTX4927_IOC_NAME,
238         .ack = toshiba_rbtx4927_irq_ioc_disable,
239         .mask = toshiba_rbtx4927_irq_ioc_disable,
240         .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
241         .unmask = toshiba_rbtx4927_irq_ioc_enable,
242         .end = toshiba_rbtx4927_irq_ioc_end,
243 };
244 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
245 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
246
247
248 #ifdef CONFIG_TOSHIBA_FPCIB0
249 #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
250 static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
251         .typename = TOSHIBA_RBTX4927_ISA_NAME,
252         .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
253         .mask = toshiba_rbtx4927_irq_isa_disable,
254         .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
255         .unmask = toshiba_rbtx4927_irq_isa_enable,
256         .end = toshiba_rbtx4927_irq_isa_end,
257 };
258 #endif
259
260
261 u32 bit2num(u32 num)
262 {
263         u32 i;
264
265         for (i = 0; i < (sizeof(num) * 8); i++) {
266                 if (num & (1 << i)) {
267                         return (i);
268                 }
269         }
270         return (0);
271 }
272
273 int toshiba_rbtx4927_irq_nested(int sw_irq)
274 {
275         u32 level3;
276         u32 level4;
277         u32 level5;
278
279         level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
280         if (level3) {
281                 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
282                 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
283                         goto RETURN;
284                 }
285         }
286 #ifdef CONFIG_TOSHIBA_FPCIB0
287         {
288                 if (tx4927_using_backplane) {
289                         outb(0x0A, 0x20);
290                         level4 = inb(0x20) & 0xff;
291                         if (level4) {
292                                 sw_irq =
293                                     TOSHIBA_RBTX4927_IRQ_ISA_BEG +
294                                     bit2num(level4);
295                                 if (sw_irq !=
296                                     TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
297                                         goto RETURN;
298                                 }
299                         }
300
301                         outb(0x0A, 0xA0);
302                         level5 = inb(0xA0) & 0xff;
303                         if (level5) {
304                                 sw_irq =
305                                     TOSHIBA_RBTX4927_IRQ_ISA_MID +
306                                     bit2num(level5);
307                                 goto RETURN;
308                         }
309                 }
310         }
311 #endif
312
313       RETURN:
314         return (sw_irq);
315 }
316
317 //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
318 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
319 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
320 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
321 #ifdef CONFIG_TOSHIBA_FPCIB0
322 static struct irqaction toshiba_rbtx4927_irq_isa_master =
323 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
324 static struct irqaction toshiba_rbtx4927_irq_isa_slave =
325 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
326 #endif
327
328
329 /**********************************************************************************/
330 /* Functions for ioc                                                              */
331 /**********************************************************************************/
332
333
334 static void __init toshiba_rbtx4927_irq_ioc_init(void)
335 {
336         int i;
337
338         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
339                                      "beg=%d end=%d\n",
340                                      TOSHIBA_RBTX4927_IRQ_IOC_BEG,
341                                      TOSHIBA_RBTX4927_IRQ_IOC_END);
342
343         for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
344              i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
345                 set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type);
346
347         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
348                   &toshiba_rbtx4927_irq_ioc_action);
349 }
350
351 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
352 {
353         volatile unsigned char v;
354
355         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
356                                      "irq=%d\n", irq);
357
358         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
359             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
360                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
361                                              "bad irq=%d\n", irq);
362                 panic("\n");
363         }
364
365         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
366         v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
367         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
368 }
369
370
371 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
372 {
373         volatile unsigned char v;
374
375         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
376                                      "irq=%d\n", irq);
377
378         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
379             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
380                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
381                                              "bad irq=%d\n", irq);
382                 panic("\n");
383         }
384
385         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
386         v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
387         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
388 }
389
390 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
391 {
392         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
393                                      "irq=%d\n", irq);
394
395         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
396             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
397                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
398                                              "bad irq=%d\n", irq);
399                 panic("\n");
400         }
401
402         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
403                 toshiba_rbtx4927_irq_ioc_enable(irq);
404         }
405 }
406
407
408 /**********************************************************************************/
409 /* Functions for isa                                                              */
410 /**********************************************************************************/
411
412
413 #ifdef CONFIG_TOSHIBA_FPCIB0
414 static void __init toshiba_rbtx4927_irq_isa_init(void)
415 {
416         int i;
417
418         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
419                                      "beg=%d end=%d\n",
420                                      TOSHIBA_RBTX4927_IRQ_ISA_BEG,
421                                      TOSHIBA_RBTX4927_IRQ_ISA_END);
422
423         for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
424              i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
425                 set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
426
427         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
428                   &toshiba_rbtx4927_irq_isa_master);
429         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
430                   &toshiba_rbtx4927_irq_isa_slave);
431
432         /* make sure we are looking at IRR (not ISR) */
433         outb(0x0A, 0x20);
434         outb(0x0A, 0xA0);
435 }
436 #endif
437
438
439 #ifdef CONFIG_TOSHIBA_FPCIB0
440 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
441 {
442         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
443                                      "irq=%d\n", irq);
444
445         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
446             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
447                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
448                                              "bad irq=%d\n", irq);
449                 panic("\n");
450         }
451
452         enable_8259A_irq(irq);
453 }
454 #endif
455
456
457 #ifdef CONFIG_TOSHIBA_FPCIB0
458 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
459 {
460         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
461                                      "irq=%d\n", irq);
462
463         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
464             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
465                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
466                                              "bad irq=%d\n", irq);
467                 panic("\n");
468         }
469
470         disable_8259A_irq(irq);
471 }
472 #endif
473
474
475 #ifdef CONFIG_TOSHIBA_FPCIB0
476 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
477 {
478         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
479                                      "irq=%d\n", irq);
480
481         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
482             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
483                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
484                                              "bad irq=%d\n", irq);
485                 panic("\n");
486         }
487
488         mask_and_ack_8259A(irq);
489 }
490 #endif
491
492
493 #ifdef CONFIG_TOSHIBA_FPCIB0
494 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
495 {
496         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
497                                      "irq=%d\n", irq);
498
499         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
500             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
501                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
502                                              "bad irq=%d\n", irq);
503                 panic("\n");
504         }
505
506         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
507                 toshiba_rbtx4927_irq_isa_enable(irq);
508         }
509 }
510 #endif
511
512
513 void __init arch_init_irq(void)
514 {
515         extern void tx4927_irq_init(void);
516
517         tx4927_irq_init();
518         toshiba_rbtx4927_irq_ioc_init();
519 #ifdef CONFIG_TOSHIBA_FPCIB0
520         {
521                 if (tx4927_using_backplane) {
522                         toshiba_rbtx4927_irq_isa_init();
523                 }
524         }
525 #endif
526
527         wbflush();
528 }
529
530 void toshiba_rbtx4927_irq_dump(char *key)
531 {
532 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
533         {
534                 u32 i, j = 0;
535                 for (i = 0; i < NR_IRQS; i++) {
536                         if (strcmp(irq_desc[i].chip->typename, "none")
537                             == 0)
538                                 continue;
539
540                         if ((i >= 1)
541                             && (irq_desc[i - 1].chip->typename ==
542                                 irq_desc[i].chip->typename)) {
543                                 j++;
544                         } else {
545                                 j = 0;
546                         }
547                         TOSHIBA_RBTX4927_IRQ_DPRINTK
548                             (TOSHIBA_RBTX4927_IRQ_INFO,
549                              "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
550                              key, i, i, irq_desc[i].status,
551                              (u32) irq_desc[i].chip,
552                              (u32) irq_desc[i].action,
553                              (u32) (irq_desc[i].action ? irq_desc[i].
554                                     action->handler : 0),
555                              irq_desc[i].depth,
556                              irq_desc[i].chip->typename, j);
557                 }
558         }
559 #endif
560 }
561
562 void toshiba_rbtx4927_irq_dump_pics(char *s)
563 {
564         u32 level0_m;
565         u32 level0_s;
566         u32 level1_m;
567         u32 level1_s;
568         u32 level2;
569         u32 level2_p;
570         u32 level2_s;
571         u32 level3_m;
572         u32 level3_s;
573         u32 level4_m;
574         u32 level4_s;
575         u32 level5_m;
576         u32 level5_s;
577
578         if (s == NULL)
579                 s = "null";
580
581         level0_m = (read_c0_status() & 0x0000ff00) >> 8;
582         level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
583
584         level1_m = level0_m;
585         level1_s = level0_s & 0x87;
586
587         level2 = TX4927_RD(0xff1ff6a0);
588         level2_p = (((level2 & 0x10000)) ? 0 : 1);
589         level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
590
591         level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
592         level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
593
594         level4_m = inb(0x21);
595         outb(0x0A, 0x20);
596         level4_s = inb(0x20);
597
598         level5_m = inb(0xa1);
599         outb(0x0A, 0xa0);
600         level5_s = inb(0xa0);
601
602         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
603                                      "dump_raw_pic() ");
604         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
605                                      "cp0:m=0x%02x/s=0x%02x ", level0_m,
606                                      level0_s);
607         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
608                                      "cp0:m=0x%02x/s=0x%02x ", level1_m,
609                                      level1_s);
610         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
611                                      "pic:e=0x%02x/s=0x%02x ", level2_p,
612                                      level2_s);
613         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
614                                      "ioc:m=0x%02x/s=0x%02x ", level3_m,
615                                      level3_s);
616         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
617                                      "sbm:m=0x%02x/s=0x%02x ", level4_m,
618                                      level4_s);
619         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
620                                      "sbs:m=0x%02x/s=0x%02x ", level5_m,
621                                      level5_s);
622         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
623                                      s);
624 }