ab44a2f59ee497a973da4c74a2405b6f7f5fcf3c
[linux-2.6.git] / arch / mips / sibyte / sb1250 / irq.c
1 /*
2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/smp.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
27
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/time.h>
32 #include <asm/io.h>
33
34 #include <asm/sibyte/sb1250_regs.h>
35 #include <asm/sibyte/sb1250_int.h>
36 #include <asm/sibyte/sb1250_uart.h>
37 #include <asm/sibyte/sb1250_scd.h>
38 #include <asm/sibyte/sb1250.h>
39
40 /*
41  * These are the routines that handle all the low level interrupt stuff.
42  * Actions handled here are: initialization of the interrupt map, requesting of
43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
44  * for interrupt lines
45  */
46
47
48 static void end_sb1250_irq(unsigned int irq);
49 static void enable_sb1250_irq(unsigned int irq);
50 static void disable_sb1250_irq(unsigned int irq);
51 static void ack_sb1250_irq(unsigned int irq);
52 #ifdef CONFIG_SMP
53 static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
54 #endif
55
56 #ifdef CONFIG_SIBYTE_HAS_LDT
57 extern unsigned long ldt_eoi_space;
58 #endif
59
60 static struct irq_chip sb1250_irq_type = {
61         .name = "SB1250-IMR",
62         .ack = ack_sb1250_irq,
63         .mask = disable_sb1250_irq,
64         .mask_ack = ack_sb1250_irq,
65         .unmask = enable_sb1250_irq,
66         .end = end_sb1250_irq,
67 #ifdef CONFIG_SMP
68         .set_affinity = sb1250_set_affinity
69 #endif
70 };
71
72 /* Store the CPU id (not the logical number) */
73 int sb1250_irq_owner[SB1250_NR_IRQS];
74
75 static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
76
77 void sb1250_mask_irq(int cpu, int irq)
78 {
79         unsigned long flags;
80         u64 cur_ints;
81
82         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
83         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
84                                         R_IMR_INTERRUPT_MASK));
85         cur_ints |= (((u64) 1) << irq);
86         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
87                                         R_IMR_INTERRUPT_MASK));
88         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
89 }
90
91 void sb1250_unmask_irq(int cpu, int irq)
92 {
93         unsigned long flags;
94         u64 cur_ints;
95
96         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
97         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
98                                         R_IMR_INTERRUPT_MASK));
99         cur_ints &= ~(((u64) 1) << irq);
100         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
101                                         R_IMR_INTERRUPT_MASK));
102         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
103 }
104
105 #ifdef CONFIG_SMP
106 static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
107 {
108         int i = 0, old_cpu, cpu, int_on;
109         u64 cur_ints;
110         unsigned long flags;
111
112         i = cpumask_first(mask);
113
114         /* Convert logical CPU to physical CPU */
115         cpu = cpu_logical_map(i);
116
117         /* Protect against other affinity changers and IMR manipulation */
118         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
119
120         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
121         old_cpu = sb1250_irq_owner[irq];
122         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
123                                         R_IMR_INTERRUPT_MASK));
124         int_on = !(cur_ints & (((u64) 1) << irq));
125         if (int_on) {
126                 /* If it was on, mask it */
127                 cur_ints |= (((u64) 1) << irq);
128                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
129                                         R_IMR_INTERRUPT_MASK));
130         }
131         sb1250_irq_owner[irq] = cpu;
132         if (int_on) {
133                 /* unmask for the new CPU */
134                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
135                                         R_IMR_INTERRUPT_MASK));
136                 cur_ints &= ~(((u64) 1) << irq);
137                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
138                                         R_IMR_INTERRUPT_MASK));
139         }
140         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
141
142         return 0;
143 }
144 #endif
145
146 /*****************************************************************************/
147
148 static void disable_sb1250_irq(unsigned int irq)
149 {
150         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
151 }
152
153 static void enable_sb1250_irq(unsigned int irq)
154 {
155         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
156 }
157
158
159 static void ack_sb1250_irq(unsigned int irq)
160 {
161 #ifdef CONFIG_SIBYTE_HAS_LDT
162         u64 pending;
163
164         /*
165          * If the interrupt was an HT interrupt, now is the time to
166          * clear it.  NOTE: we assume the HT bridge was set up to
167          * deliver the interrupts to all CPUs (which makes affinity
168          * changing easier for us)
169          */
170         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
171                                                     R_IMR_LDT_INTERRUPT)));
172         pending &= ((u64)1 << (irq));
173         if (pending) {
174                 int i;
175                 for (i=0; i<NR_CPUS; i++) {
176                         int cpu;
177 #ifdef CONFIG_SMP
178                         cpu = cpu_logical_map(i);
179 #else
180                         cpu = i;
181 #endif
182                         /*
183                          * Clear for all CPUs so an affinity switch
184                          * doesn't find an old status
185                          */
186                         __raw_writeq(pending,
187                                      IOADDR(A_IMR_REGISTER(cpu,
188                                                 R_IMR_LDT_INTERRUPT_CLR)));
189                 }
190
191                 /*
192                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
193                  * Pass 2, the LDT world may be edge-triggered, but
194                  * this EOI shouldn't hurt.  If they are
195                  * level-sensitive, the EOI is required.
196                  */
197                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
198         }
199 #endif
200         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
201 }
202
203
204 static void end_sb1250_irq(unsigned int irq)
205 {
206         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
207                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
208         }
209 }
210
211
212 void __init init_sb1250_irqs(void)
213 {
214         int i;
215
216         for (i = 0; i < SB1250_NR_IRQS; i++) {
217                 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
218                 sb1250_irq_owner[i] = 0;
219         }
220 }
221
222
223 /*
224  *  arch_init_irq is called early in the boot sequence from init/main.c via
225  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
226  *  installing the handler that will be responsible for dispatching interrupts
227  *  to the "right" place.
228  */
229 /*
230  * For now, map all interrupts to IP[2].  We could save
231  * some cycles by parceling out system interrupts to different
232  * IP lines, but keep it simple for bringup.  We'll also direct
233  * all interrupts to a single CPU; we should probably route
234  * PCI and LDT to one cpu and everything else to the other
235  * to balance the load a bit.
236  *
237  * On the second cpu, everything is set to IP5, which is
238  * ignored, EXCEPT the mailbox interrupt.  That one is
239  * set to IP[2] so it is handled.  This is needed so we
240  * can do cross-cpu function calls, as requred by SMP
241  */
242
243 #define IMR_IP2_VAL     K_INT_MAP_I0
244 #define IMR_IP3_VAL     K_INT_MAP_I1
245 #define IMR_IP4_VAL     K_INT_MAP_I2
246 #define IMR_IP5_VAL     K_INT_MAP_I3
247 #define IMR_IP6_VAL     K_INT_MAP_I4
248
249 void __init arch_init_irq(void)
250 {
251
252         unsigned int i;
253         u64 tmp;
254         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
255                 STATUSF_IP1 | STATUSF_IP0;
256
257         /* Default everything to IP2 */
258         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
259                 __raw_writeq(IMR_IP2_VAL,
260                              IOADDR(A_IMR_REGISTER(0,
261                                                    R_IMR_INTERRUPT_MAP_BASE) +
262                                     (i << 3)));
263                 __raw_writeq(IMR_IP2_VAL,
264                              IOADDR(A_IMR_REGISTER(1,
265                                                    R_IMR_INTERRUPT_MAP_BASE) +
266                                     (i << 3)));
267         }
268
269         init_sb1250_irqs();
270
271         /*
272          * Map the high 16 bits of the mailbox registers to IP[3], for
273          * inter-cpu messages
274          */
275         /* Was I1 */
276         __raw_writeq(IMR_IP3_VAL,
277                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
278                             (K_INT_MBOX_0 << 3)));
279         __raw_writeq(IMR_IP3_VAL,
280                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
281                             (K_INT_MBOX_0 << 3)));
282
283         /* Clear the mailboxes.  The firmware may leave them dirty */
284         __raw_writeq(0xffffffffffffffffULL,
285                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
286         __raw_writeq(0xffffffffffffffffULL,
287                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
288
289         /* Mask everything except the mailbox registers for both cpus */
290         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
291         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
292         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
293
294         /*
295          * Note that the timer interrupts are also mapped, but this is
296          * done in sb1250_time_init().  Also, the profiling driver
297          * does its own management of IP7.
298          */
299
300         /* Enable necessary IPs, disable the rest */
301         change_c0_status(ST0_IM, imask);
302 }
303
304 extern void sb1250_mailbox_interrupt(void);
305
306 static inline void dispatch_ip2(void)
307 {
308         unsigned int cpu = smp_processor_id();
309         unsigned long long mask;
310
311         /*
312          * Default...we've hit an IP[2] interrupt, which means we've got to
313          * check the 1250 interrupt registers to figure out what to do.  Need
314          * to detect which CPU we're on, now that smp_affinity is supported.
315          */
316         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
317                                   R_IMR_INTERRUPT_STATUS_BASE)));
318         if (mask)
319                 do_IRQ(fls64(mask) - 1);
320 }
321
322 asmlinkage void plat_irq_dispatch(void)
323 {
324         unsigned int cpu = smp_processor_id();
325         unsigned int pending;
326
327         /*
328          * What a pain. We have to be really careful saving the upper 32 bits
329          * of any * register across function calls if we don't want them
330          * trashed--since were running in -o32, the calling routing never saves
331          * the full 64 bits of a register across a function call.  Being the
332          * interrupt handler, we're guaranteed that interrupts are disabled
333          * during this code so we don't have to worry about random interrupts
334          * blasting the high 32 bits.
335          */
336
337         pending = read_c0_cause() & read_c0_status() & ST0_IM;
338
339         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
340                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
341         else if (pending & CAUSEF_IP4)
342                 do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
343
344 #ifdef CONFIG_SMP
345         else if (pending & CAUSEF_IP3)
346                 sb1250_mailbox_interrupt();
347 #endif
348
349         else if (pending & CAUSEF_IP2)
350                 dispatch_ip2();
351         else
352                 spurious_interrupt();
353 }