[MIPS] IRQ cleanups
[linux-2.6.git] / arch / mips / sgi-ip22 / ip22-int.c
1 /*
2  * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
3  *             found on INDY and Indigo2 workstations.
4  *
5  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6  * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
7  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
8  *                    - Indigo2 changes
9  *                    - Interrupt handling fixes
10  * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
11  */
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19
20 #include <asm/mipsregs.h>
21 #include <asm/addrspace.h>
22
23 #include <asm/sgi/ioc.h>
24 #include <asm/sgi/hpc3.h>
25 #include <asm/sgi/ip22.h>
26
27 /* #define DEBUG_SGINT */
28
29 /* So far nothing hangs here */
30 #undef USE_LIO3_IRQ
31
32 struct sgint_regs *sgint;
33
34 static char lc0msk_to_irqnr[256];
35 static char lc1msk_to_irqnr[256];
36 static char lc2msk_to_irqnr[256];
37 static char lc3msk_to_irqnr[256];
38
39 extern int ip22_eisa_init(void);
40
41 static void enable_local0_irq(unsigned int irq)
42 {
43         /* don't allow mappable interrupt to be enabled from setup_irq,
44          * we have our own way to do so */
45         if (irq != SGI_MAP_0_IRQ)
46                 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
47 }
48
49 static void disable_local0_irq(unsigned int irq)
50 {
51         sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
52 }
53
54 static void end_local0_irq (unsigned int irq)
55 {
56         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
57                 enable_local0_irq(irq);
58 }
59
60 static struct irq_chip ip22_local0_irq_type = {
61         .typename       = "IP22 local 0",
62         .ack            = disable_local0_irq,
63         .mask           = disable_local0_irq,
64         .mask_ack       = disable_local0_irq,
65         .unmask         = enable_local0_irq,
66         .end            = end_local0_irq,
67 };
68
69 static void enable_local1_irq(unsigned int irq)
70 {
71         /* don't allow mappable interrupt to be enabled from setup_irq,
72          * we have our own way to do so */
73         if (irq != SGI_MAP_1_IRQ)
74                 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
75 }
76
77 void disable_local1_irq(unsigned int irq)
78 {
79         sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
80 }
81
82 static void end_local1_irq (unsigned int irq)
83 {
84         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
85                 enable_local1_irq(irq);
86 }
87
88 static struct irq_chip ip22_local1_irq_type = {
89         .typename       = "IP22 local 1",
90         .ack            = disable_local1_irq,
91         .mask           = disable_local1_irq,
92         .mask_ack       = disable_local1_irq,
93         .unmask         = enable_local1_irq,
94         .end            = end_local1_irq,
95 };
96
97 static void enable_local2_irq(unsigned int irq)
98 {
99         sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
100         sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
101 }
102
103 void disable_local2_irq(unsigned int irq)
104 {
105         sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
106         if (!sgint->cmeimask0)
107                 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
108 }
109
110 static void end_local2_irq (unsigned int irq)
111 {
112         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
113                 enable_local2_irq(irq);
114 }
115
116 static struct irq_chip ip22_local2_irq_type = {
117         .typename       = "IP22 local 2",
118         .ack            = disable_local2_irq,
119         .mask           = disable_local2_irq,
120         .mask_ack       = disable_local2_irq,
121         .unmask         = enable_local2_irq,
122         .end            = end_local2_irq,
123 };
124
125 static void enable_local3_irq(unsigned int irq)
126 {
127         sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
128         sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
129 }
130
131 void disable_local3_irq(unsigned int irq)
132 {
133         sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
134         if (!sgint->cmeimask1)
135                 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
136 }
137
138 static void end_local3_irq (unsigned int irq)
139 {
140         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
141                 enable_local3_irq(irq);
142 }
143
144 static struct irq_chip ip22_local3_irq_type = {
145         .typename       = "IP22 local 3",
146         .ack            = disable_local3_irq,
147         .mask           = disable_local3_irq,
148         .mask_ack       = disable_local3_irq,
149         .unmask         = enable_local3_irq,
150         .end            = end_local3_irq,
151 };
152
153 static void indy_local0_irqdispatch(void)
154 {
155         u8 mask = sgint->istat0 & sgint->imask0;
156         u8 mask2;
157         int irq;
158
159         if (mask & SGINT_ISTAT0_LIO2) {
160                 mask2 = sgint->vmeistat & sgint->cmeimask0;
161                 irq = lc2msk_to_irqnr[mask2];
162         } else
163                 irq = lc0msk_to_irqnr[mask];
164
165         /* if irq == 0, then the interrupt has already been cleared */
166         if (irq)
167                 do_IRQ(irq);
168 }
169
170 static void indy_local1_irqdispatch(void)
171 {
172         u8 mask = sgint->istat1 & sgint->imask1;
173         u8 mask2;
174         int irq;
175
176         if (mask & SGINT_ISTAT1_LIO3) {
177                 mask2 = sgint->vmeistat & sgint->cmeimask1;
178                 irq = lc3msk_to_irqnr[mask2];
179         } else
180                 irq = lc1msk_to_irqnr[mask];
181
182         /* if irq == 0, then the interrupt has already been cleared */
183         if (irq)
184                 do_IRQ(irq);
185 }
186
187 extern void ip22_be_interrupt(int irq);
188
189 static void indy_buserror_irq(void)
190 {
191         int irq = SGI_BUSERR_IRQ;
192
193         irq_enter();
194         kstat_this_cpu.irqs[irq]++;
195         ip22_be_interrupt(irq);
196         irq_exit();
197 }
198
199 static struct irqaction local0_cascade = {
200         .handler        = no_action,
201         .flags          = IRQF_DISABLED,
202         .name           = "local0 cascade",
203 };
204
205 static struct irqaction local1_cascade = {
206         .handler        = no_action,
207         .flags          = IRQF_DISABLED,
208         .name           = "local1 cascade",
209 };
210
211 static struct irqaction buserr = {
212         .handler        = no_action,
213         .flags          = IRQF_DISABLED,
214         .name           = "Bus Error",
215 };
216
217 static struct irqaction map0_cascade = {
218         .handler        = no_action,
219         .flags          = IRQF_DISABLED,
220         .name           = "mapable0 cascade",
221 };
222
223 #ifdef USE_LIO3_IRQ
224 static struct irqaction map1_cascade = {
225         .handler        = no_action,
226         .flags          = IRQF_DISABLED,
227         .name           = "mapable1 cascade",
228 };
229 #define SGI_INTERRUPTS  SGINT_END
230 #else
231 #define SGI_INTERRUPTS  SGINT_LOCAL3
232 #endif
233
234 extern void indy_r4k_timer_interrupt(void);
235 extern void indy_8254timer_irq(void);
236
237 /*
238  * IRQs on the INDY look basically (barring software IRQs which we don't use
239  * at all) like:
240  *
241  *      MIPS IRQ        Source
242  *      --------        ------
243  *             0        Software (ignored)
244  *             1        Software (ignored)
245  *             2        Local IRQ level zero
246  *             3        Local IRQ level one
247  *             4        8254 Timer zero
248  *             5        8254 Timer one
249  *             6        Bus Error
250  *             7        R4k timer (what we use)
251  *
252  * We handle the IRQ according to _our_ priority which is:
253  *
254  * Highest ----     R4k Timer
255  *                  Local IRQ zero
256  *                  Local IRQ one
257  *                  Bus Error
258  *                  8254 Timer zero
259  * Lowest  ----     8254 Timer one
260  *
261  * then we just return, if multiple IRQs are pending then we will just take
262  * another exception, big deal.
263  */
264
265 asmlinkage void plat_irq_dispatch(void)
266 {
267         unsigned int pending = read_c0_cause();
268
269         /*
270          * First we check for r4k counter/timer IRQ.
271          */
272         if (pending & CAUSEF_IP7)
273                 indy_r4k_timer_interrupt();
274         else if (pending & CAUSEF_IP2)
275                 indy_local0_irqdispatch();
276         else if (pending & CAUSEF_IP3)
277                 indy_local1_irqdispatch();
278         else if (pending & CAUSEF_IP6)
279                 indy_buserror_irq();
280         else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
281                 indy_8254timer_irq();
282 }
283
284 extern void mips_cpu_irq_init(unsigned int irq_base);
285
286 void __init arch_init_irq(void)
287 {
288         int i;
289
290         /* Init local mask --> irq tables. */
291         for (i = 0; i < 256; i++) {
292                 if (i & 0x80) {
293                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
294                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
295                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
296                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
297                 } else if (i & 0x40) {
298                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
299                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
300                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
301                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
302                 } else if (i & 0x20) {
303                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
304                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
305                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
306                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
307                 } else if (i & 0x10) {
308                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
309                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
310                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
311                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
312                 } else if (i & 0x08) {
313                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
314                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
315                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
316                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
317                 } else if (i & 0x04) {
318                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
319                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
320                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
321                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
322                 } else if (i & 0x02) {
323                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
324                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
325                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
326                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
327                 } else if (i & 0x01) {
328                         lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
329                         lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
330                         lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
331                         lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
332                 } else {
333                         lc0msk_to_irqnr[i] = 0;
334                         lc1msk_to_irqnr[i] = 0;
335                         lc2msk_to_irqnr[i] = 0;
336                         lc3msk_to_irqnr[i] = 0;
337                 }
338         }
339
340         /* Mask out all interrupts. */
341         sgint->imask0 = 0;
342         sgint->imask1 = 0;
343         sgint->cmeimask0 = 0;
344         sgint->cmeimask1 = 0;
345
346         /* init CPU irqs */
347         mips_cpu_irq_init(SGINT_CPU);
348
349         for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
350                 struct irq_chip *handler;
351
352                 if (i < SGINT_LOCAL1)
353                         handler         = &ip22_local0_irq_type;
354                 else if (i < SGINT_LOCAL2)
355                         handler         = &ip22_local1_irq_type;
356                 else if (i < SGINT_LOCAL3)
357                         handler         = &ip22_local2_irq_type;
358                 else
359                         handler         = &ip22_local3_irq_type;
360
361                 set_irq_chip(i, handler);
362         }
363
364         /* vector handler. this register the IRQ as non-sharable */
365         setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
366         setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
367         setup_irq(SGI_BUSERR_IRQ, &buserr);
368
369         /* cascade in cascade. i love Indy ;-) */
370         setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
371 #ifdef USE_LIO3_IRQ
372         setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
373 #endif
374
375 #ifdef CONFIG_EISA
376         if (ip22_is_fullhouse())        /* Only Indigo-2 has EISA stuff */
377                 ip22_eisa_init ();
378 #endif
379 }