MIPS: EMMA: Migrate to new platform makefile style.
[linux-2.6.git] / arch / mips / nxp / pnx833x / common / interrupts.c
1 /*
2  *  interrupts.c: Interrupt mappings for PNX833X.
3  *
4  *  Copyright 2008 NXP Semiconductors
5  *        Chris Steel <chris.steel@nxp.com>
6  *    Daniel Laird <daniel.j.laird@nxp.com>
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program; if not, write to the Free Software
20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 #include <linux/kernel.h>
23 #include <linux/irq.h>
24 #include <linux/hardirq.h>
25 #include <linux/interrupt.h>
26 #include <asm/mipsregs.h>
27 #include <asm/irq_cpu.h>
28 #include <irq.h>
29 #include <irq-mapping.h>
30 #include <gpio.h>
31
32 static int mips_cpu_timer_irq;
33
34 static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
35 {
36     0, /* unused */
37     4, /* PNX833X_PIC_I2C0_INT                 1 */
38     4, /* PNX833X_PIC_I2C1_INT                 2 */
39     1, /* PNX833X_PIC_UART0_INT                3 */
40     1, /* PNX833X_PIC_UART1_INT                4 */
41     6, /* PNX833X_PIC_TS_IN0_DV_INT            5 */
42     6, /* PNX833X_PIC_TS_IN0_DMA_INT           6 */
43     7, /* PNX833X_PIC_GPIO_INT                 7 */
44     4, /* PNX833X_PIC_AUDIO_DEC_INT            8 */
45     5, /* PNX833X_PIC_VIDEO_DEC_INT            9 */
46     4, /* PNX833X_PIC_CONFIG_INT              10 */
47     4, /* PNX833X_PIC_AOI_INT                 11 */
48     9, /* PNX833X_PIC_SYNC_INT                12 */
49     9, /* PNX8335_PIC_SATA_INT                13 */
50     4, /* PNX833X_PIC_OSD_INT                 14 */
51     9, /* PNX833X_PIC_DISP1_INT               15 */
52     4, /* PNX833X_PIC_DEINTERLACER_INT        16 */
53     9, /* PNX833X_PIC_DISPLAY2_INT            17 */
54     4, /* PNX833X_PIC_VC_INT                  18 */
55     4, /* PNX833X_PIC_SC_INT                  19 */
56     9, /* PNX833X_PIC_IDE_INT                 20 */
57     9, /* PNX833X_PIC_IDE_DMA_INT             21 */
58     6, /* PNX833X_PIC_TS_IN1_DV_INT           22 */
59     6, /* PNX833X_PIC_TS_IN1_DMA_INT          23 */
60     4, /* PNX833X_PIC_SGDX_DMA_INT            24 */
61     4, /* PNX833X_PIC_TS_OUT_INT              25 */
62     4, /* PNX833X_PIC_IR_INT                  26 */
63     3, /* PNX833X_PIC_VMSP1_INT               27 */
64     3, /* PNX833X_PIC_VMSP2_INT               28 */
65     4, /* PNX833X_PIC_PIBC_INT                29 */
66     4, /* PNX833X_PIC_TS_IN0_TRD_INT          30 */
67     4, /* PNX833X_PIC_SGDX_TPD_INT            31 */
68     5, /* PNX833X_PIC_USB_INT                 32 */
69     4, /* PNX833X_PIC_TS_IN1_TRD_INT          33 */
70     4, /* PNX833X_PIC_CLOCK_INT               34 */
71     4, /* PNX833X_PIC_SGDX_PARSER_INT         35 */
72     4, /* PNX833X_PIC_VMSP_DMA_INT            36 */
73 #if defined(CONFIG_SOC_PNX8335)
74     4, /* PNX8335_PIC_MIU_INT                 37 */
75     4, /* PNX8335_PIC_AVCHIP_IRQ_INT          38 */
76     9, /* PNX8335_PIC_SYNC_HD_INT             39 */
77     9, /* PNX8335_PIC_DISP_HD_INT             40 */
78     9, /* PNX8335_PIC_DISP_SCALER_INT         41 */
79     4, /* PNX8335_PIC_OSD_HD1_INT             42 */
80     4, /* PNX8335_PIC_DTL_WRITER_Y_INT        43 */
81     4, /* PNX8335_PIC_DTL_WRITER_C_INT        44 */
82     4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45 */
83     4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46 */
84     4, /* PNX8335_PIC_DENC_TTX_INT            47 */
85     4, /* PNX8335_PIC_MMI_SIF0_INT            48 */
86     4, /* PNX8335_PIC_MMI_SIF1_INT            49 */
87     4, /* PNX8335_PIC_MMI_CDMMU_INT           50 */
88     4, /* PNX8335_PIC_PIBCS_INT               51 */
89    12, /* PNX8335_PIC_ETHERNET_INT            52 */
90     3, /* PNX8335_PIC_VMSP1_0_INT             53 */
91     3, /* PNX8335_PIC_VMSP1_1_INT             54 */
92     4, /* PNX8335_PIC_VMSP1_DMA_INT           55 */
93     4, /* PNX8335_PIC_TDGR_DE_INT             56 */
94     4, /* PNX8335_PIC_IR1_IRQ_INT             57 */
95 #endif
96 };
97
98 static void pnx833x_timer_dispatch(void)
99 {
100         do_IRQ(mips_cpu_timer_irq);
101 }
102
103 static void pic_dispatch(void)
104 {
105         unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
106
107         if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
108                 unsigned long priority = PNX833X_PIC_INT_PRIORITY;
109                 PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
110
111                 if (irq == PNX833X_PIC_GPIO_INT) {
112                         unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
113                         int pin;
114                         while ((pin = ffs(mask & 0xffff))) {
115                                 pin -= 1;
116                                 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
117                                 mask &= ~(1 << pin);
118                         }
119                 } else {
120                         do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
121                 }
122
123                 PNX833X_PIC_INT_PRIORITY = priority;
124         } else {
125                 printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
126         }
127 }
128
129 asmlinkage void plat_irq_dispatch(void)
130 {
131         unsigned int pending = read_c0_status() & read_c0_cause();
132
133         if (pending & STATUSF_IP4)
134                 pic_dispatch();
135         else if (pending & STATUSF_IP7)
136                 do_IRQ(PNX833X_TIMER_IRQ);
137         else
138                 spurious_interrupt();
139 }
140
141 static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
142 {
143         /* Currently we do this by setting IRQ priority to 1.
144            If priority support is being implemented, 1 should be repalced
145                 by a better value. */
146         PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
147 }
148
149 static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
150 {
151         /* Disable IRQ by writing setting it's priority to 0 */
152         PNX833X_PIC_INT_REG(irq) = 0;
153 }
154
155 static int irqflags[PNX833X_PIC_NUM_IRQ];       /* initialized by zeroes */
156 #define IRQFLAG_STARTED         1
157 #define IRQFLAG_DISABLED        2
158
159 static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
160
161 static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
162 {
163         unsigned long flags;
164         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
165
166         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
167
168         irqflags[pic_irq] = IRQFLAG_STARTED;    /* started, not disabled */
169         pnx833x_hard_enable_pic_irq(pic_irq);
170
171         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
172         return 0;
173 }
174
175 static void pnx833x_shutdown_pic_irq(unsigned int irq)
176 {
177         unsigned long flags;
178         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
179
180         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
181
182         irqflags[pic_irq] = 0;                  /* not started */
183         pnx833x_hard_disable_pic_irq(pic_irq);
184
185         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
186 }
187
188 static void pnx833x_enable_pic_irq(unsigned int irq)
189 {
190         unsigned long flags;
191         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
192
193         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
194
195         irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
196         if (irqflags[pic_irq] == IRQFLAG_STARTED)
197                 pnx833x_hard_enable_pic_irq(pic_irq);
198
199         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
200 }
201
202 static void pnx833x_disable_pic_irq(unsigned int irq)
203 {
204         unsigned long flags;
205         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
206
207         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
208
209         irqflags[pic_irq] |= IRQFLAG_DISABLED;
210         pnx833x_hard_disable_pic_irq(pic_irq);
211
212         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
213 }
214
215 static void pnx833x_ack_pic_irq(unsigned int irq)
216 {
217 }
218
219 static void pnx833x_end_pic_irq(unsigned int irq)
220 {
221 }
222
223 static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
224
225 static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
226 {
227         int pin = irq - PNX833X_GPIO_IRQ_BASE;
228         unsigned long flags;
229         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
230         pnx833x_gpio_enable_irq(pin);
231         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
232         return 0;
233 }
234
235 static void pnx833x_enable_gpio_irq(unsigned int irq)
236 {
237         int pin = irq - PNX833X_GPIO_IRQ_BASE;
238         unsigned long flags;
239         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
240         pnx833x_gpio_enable_irq(pin);
241         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
242 }
243
244 static void pnx833x_disable_gpio_irq(unsigned int irq)
245 {
246         int pin = irq - PNX833X_GPIO_IRQ_BASE;
247         unsigned long flags;
248         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
249         pnx833x_gpio_disable_irq(pin);
250         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
251 }
252
253 static void pnx833x_ack_gpio_irq(unsigned int irq)
254 {
255 }
256
257 static void pnx833x_end_gpio_irq(unsigned int irq)
258 {
259         int pin = irq - PNX833X_GPIO_IRQ_BASE;
260         unsigned long flags;
261         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
262         pnx833x_gpio_clear_irq(pin);
263         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
264 }
265
266 static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
267 {
268         int pin = irq - PNX833X_GPIO_IRQ_BASE;
269         int gpio_mode;
270
271         switch (flow_type) {
272         case IRQ_TYPE_EDGE_RISING:
273                 gpio_mode = GPIO_INT_EDGE_RISING;
274                 break;
275         case IRQ_TYPE_EDGE_FALLING:
276                 gpio_mode = GPIO_INT_EDGE_FALLING;
277                 break;
278         case IRQ_TYPE_EDGE_BOTH:
279                 gpio_mode = GPIO_INT_EDGE_BOTH;
280                 break;
281         case IRQ_TYPE_LEVEL_HIGH:
282                 gpio_mode = GPIO_INT_LEVEL_HIGH;
283                 break;
284         case IRQ_TYPE_LEVEL_LOW:
285                 gpio_mode = GPIO_INT_LEVEL_LOW;
286                 break;
287         default:
288                 gpio_mode = GPIO_INT_NONE;
289                 break;
290         }
291
292         pnx833x_gpio_setup_irq(gpio_mode, pin);
293
294         return 0;
295 }
296
297 static struct irq_chip pnx833x_pic_irq_type = {
298         .name = "PNX-PIC",
299         .startup = pnx833x_startup_pic_irq,
300         .shutdown = pnx833x_shutdown_pic_irq,
301         .enable = pnx833x_enable_pic_irq,
302         .disable = pnx833x_disable_pic_irq,
303         .ack = pnx833x_ack_pic_irq,
304         .end = pnx833x_end_pic_irq
305 };
306
307 static struct irq_chip pnx833x_gpio_irq_type = {
308         .name = "PNX-GPIO",
309         .startup = pnx833x_startup_gpio_irq,
310         .shutdown = pnx833x_disable_gpio_irq,
311         .enable = pnx833x_enable_gpio_irq,
312         .disable = pnx833x_disable_gpio_irq,
313         .ack = pnx833x_ack_gpio_irq,
314         .end = pnx833x_end_gpio_irq,
315         .set_type = pnx833x_set_type_gpio_irq
316 };
317
318 void __init arch_init_irq(void)
319 {
320         unsigned int irq;
321
322         /* setup standard internal cpu irqs */
323         mips_cpu_irq_init();
324
325         /* Set IRQ information in irq_desc */
326         for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
327                 pnx833x_hard_disable_pic_irq(irq);
328                 set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
329         }
330
331         for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
332                 set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
333
334         /* Set PIC priority limiter register to 0 */
335         PNX833X_PIC_INT_PRIORITY = 0;
336
337         /* Setup GPIO IRQ dispatching */
338         pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
339
340         /* Enable PIC IRQs (HWIRQ2) */
341         if (cpu_has_vint)
342                 set_vi_handler(4, pic_dispatch);
343
344         write_c0_status(read_c0_status() | IE_IRQ2);
345 }
346
347 unsigned int __cpuinit get_c0_compare_int(void)
348 {
349         if (cpu_has_vint)
350                 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
351
352         mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
353         return mips_cpu_timer_irq;
354 }
355
356 void __init plat_time_init(void)
357 {
358         /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
359
360         extern unsigned long mips_hpt_frequency;
361         unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
362
363         if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
364                 /* Functional clock is disabled so use crystal frequency */
365                 mips_hpt_frequency = 25;
366         } else {
367 #if defined(CONFIG_SOC_PNX8335)
368                 /* Functional clock is enabled, so get clock multiplier */
369                 mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
370 #else
371                 static const unsigned long int freq[4] = {240, 160, 120, 80};
372                 mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
373 #endif
374         }
375
376         printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
377
378         mips_hpt_frequency *= 500000;
379 }