MIPS: GIC: Remove dependencies from Malta files.
[linux-2.6.git] / arch / mips / mti-malta / malta-int.c
1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4  * Copyright (C) 2001 Ralf Baechle
5  *
6  *  This program is free software; you can distribute it and/or modify it
7  *  under the terms of the GNU General Public License (Version 2) as
8  *  published by the Free Software Foundation.
9  *
10  *  This program is distributed in the hope it will be useful, but WITHOUT
11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  *  for more details.
14  *
15  *  You should have received a copy of the GNU General Public License along
16  *  with this program; if not, write to the Free Software Foundation, Inc.,
17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18  *
19  * Routines for generic manipulation of the interrupts found on the MIPS
20  * Malta board.
21  * The interrupt controller is located in the South Bridge a PIIX4 device
22  * with two internal 82C95 interrupt controllers.
23  */
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/kernel.h>
32 #include <linux/random.h>
33
34 #include <asm/traps.h>
35 #include <asm/i8259.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/irq_regs.h>
38 #include <asm/mips-boards/malta.h>
39 #include <asm/mips-boards/maltaint.h>
40 #include <asm/mips-boards/piix4.h>
41 #include <asm/gt64120.h>
42 #include <asm/mips-boards/generic.h>
43 #include <asm/mips-boards/msc01_pci.h>
44 #include <asm/msc01_ic.h>
45 #include <asm/gic.h>
46 #include <asm/gcmpregs.h>
47
48 int gcmp_present = -1;
49 int gic_present;
50 static unsigned long _msc01_biu_base;
51 static unsigned long _gcmp_base;
52 static unsigned int ipi_map[NR_CPUS];
53
54 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
55
56 static inline int mips_pcibios_iack(void)
57 {
58         int irq;
59         u32 dummy;
60
61         /*
62          * Determine highest priority pending interrupt by performing
63          * a PCI Interrupt Acknowledge cycle.
64          */
65         switch (mips_revision_sconid) {
66         case MIPS_REVISION_SCON_SOCIT:
67         case MIPS_REVISION_SCON_ROCIT:
68         case MIPS_REVISION_SCON_SOCITSC:
69         case MIPS_REVISION_SCON_SOCITSCP:
70                 MSC_READ(MSC01_PCI_IACK, irq);
71                 irq &= 0xff;
72                 break;
73         case MIPS_REVISION_SCON_GT64120:
74                 irq = GT_READ(GT_PCI0_IACK_OFS);
75                 irq &= 0xff;
76                 break;
77         case MIPS_REVISION_SCON_BONITO:
78                 /* The following will generate a PCI IACK cycle on the
79                  * Bonito controller. It's a little bit kludgy, but it
80                  * was the easiest way to implement it in hardware at
81                  * the given time.
82                  */
83                 BONITO_PCIMAP_CFG = 0x20000;
84
85                 /* Flush Bonito register block */
86                 dummy = BONITO_PCIMAP_CFG;
87                 iob();    /* sync */
88
89                 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
90                 iob();    /* sync */
91                 irq &= 0xff;
92                 BONITO_PCIMAP_CFG = 0;
93                 break;
94         default:
95                 printk(KERN_WARNING "Unknown system controller.\n");
96                 return -1;
97         }
98         return irq;
99 }
100
101 static inline int get_int(void)
102 {
103         unsigned long flags;
104         int irq;
105         raw_spin_lock_irqsave(&mips_irq_lock, flags);
106
107         irq = mips_pcibios_iack();
108
109         /*
110          * The only way we can decide if an interrupt is spurious
111          * is by checking the 8259 registers.  This needs a spinlock
112          * on an SMP system,  so leave it up to the generic code...
113          */
114
115         raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
116
117         return irq;
118 }
119
120 static void malta_hw0_irqdispatch(void)
121 {
122         int irq;
123
124         irq = get_int();
125         if (irq < 0) {
126                 /* interrupt has already been cleared */
127                 return;
128         }
129
130         do_IRQ(MALTA_INT_BASE + irq);
131 }
132
133 static void malta_ipi_irqdispatch(void)
134 {
135         int irq;
136
137         irq = gic_get_int();
138         if (irq < 0)
139                 return;  /* interrupt has already been cleared */
140
141         do_IRQ(MIPS_GIC_IRQ_BASE + irq);
142 }
143
144 static void corehi_irqdispatch(void)
145 {
146         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
147         unsigned int pcimstat, intisr, inten, intpol;
148         unsigned int intrcause, datalo, datahi;
149         struct pt_regs *regs = get_irq_regs();
150
151         printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
152         printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
153                         "Cause : %08lx\nbadVaddr : %08lx\n",
154                         regs->cp0_epc, regs->cp0_status,
155                         regs->cp0_cause, regs->cp0_badvaddr);
156
157         /* Read all the registers and then print them as there is a
158            problem with interspersed printk's upsetting the Bonito controller.
159            Do it for the others too.
160         */
161
162         switch (mips_revision_sconid) {
163         case MIPS_REVISION_SCON_SOCIT:
164         case MIPS_REVISION_SCON_ROCIT:
165         case MIPS_REVISION_SCON_SOCITSC:
166         case MIPS_REVISION_SCON_SOCITSCP:
167                 ll_msc_irq();
168                 break;
169         case MIPS_REVISION_SCON_GT64120:
170                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
171                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
172                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
173                 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
174                 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
175                                 datahi, datalo);
176                 break;
177         case MIPS_REVISION_SCON_BONITO:
178                 pcibadaddr = BONITO_PCIBADADDR;
179                 pcimstat = BONITO_PCIMSTAT;
180                 intisr = BONITO_INTISR;
181                 inten = BONITO_INTEN;
182                 intpol = BONITO_INTPOL;
183                 intedge = BONITO_INTEDGE;
184                 intsteer = BONITO_INTSTEER;
185                 pcicmd = BONITO_PCICMD;
186                 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
187                 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
188                 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
189                 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
190                 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
191                 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
192                 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
193                 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
194                 break;
195         }
196
197         die("CoreHi interrupt", regs);
198 }
199
200 static inline int clz(unsigned long x)
201 {
202         __asm__(
203         "       .set    push                                    \n"
204         "       .set    mips32                                  \n"
205         "       clz     %0, %1                                  \n"
206         "       .set    pop                                     \n"
207         : "=r" (x)
208         : "r" (x));
209
210         return x;
211 }
212
213 /*
214  * Version of ffs that only looks at bits 12..15.
215  */
216 static inline unsigned int irq_ffs(unsigned int pending)
217 {
218 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
219         return -clz(pending) + 31 - CAUSEB_IP;
220 #else
221         unsigned int a0 = 7;
222         unsigned int t0;
223
224         t0 = pending & 0xf000;
225         t0 = t0 < 1;
226         t0 = t0 << 2;
227         a0 = a0 - t0;
228         pending = pending << t0;
229
230         t0 = pending & 0xc000;
231         t0 = t0 < 1;
232         t0 = t0 << 1;
233         a0 = a0 - t0;
234         pending = pending << t0;
235
236         t0 = pending & 0x8000;
237         t0 = t0 < 1;
238         /* t0 = t0 << 2; */
239         a0 = a0 - t0;
240         /* pending = pending << t0; */
241
242         return a0;
243 #endif
244 }
245
246 /*
247  * IRQs on the Malta board look basically (barring software IRQs which we
248  * don't use at all and all external interrupt sources are combined together
249  * on hardware interrupt 0 (MIPS IRQ 2)) like:
250  *
251  *      MIPS IRQ        Source
252  *      --------        ------
253  *             0        Software (ignored)
254  *             1        Software (ignored)
255  *             2        Combined hardware interrupt (hw0)
256  *             3        Hardware (ignored)
257  *             4        Hardware (ignored)
258  *             5        Hardware (ignored)
259  *             6        Hardware (ignored)
260  *             7        R4k timer (what we use)
261  *
262  * We handle the IRQ according to _our_ priority which is:
263  *
264  * Highest ----     R4k Timer
265  * Lowest  ----     Combined hardware interrupt
266  *
267  * then we just return, if multiple IRQs are pending then we will just take
268  * another exception, big deal.
269  */
270
271 asmlinkage void plat_irq_dispatch(void)
272 {
273         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
274         int irq;
275
276         irq = irq_ffs(pending);
277
278         if (irq == MIPSCPU_INT_I8259A)
279                 malta_hw0_irqdispatch();
280         else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
281                 malta_ipi_irqdispatch();
282         else if (irq >= 0)
283                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
284         else
285                 spurious_interrupt();
286 }
287
288 #ifdef CONFIG_MIPS_MT_SMP
289
290
291 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ    3
292 #define GIC_MIPS_CPU_IPI_CALL_IRQ       4
293
294 #define MIPS_CPU_IPI_RESCHED_IRQ 0      /* SW int 0 for resched */
295 #define C_RESCHED C_SW0
296 #define MIPS_CPU_IPI_CALL_IRQ 1         /* SW int 1 for resched */
297 #define C_CALL C_SW1
298 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
299
300 static void ipi_resched_dispatch(void)
301 {
302         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
303 }
304
305 static void ipi_call_dispatch(void)
306 {
307         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
308 }
309
310 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
311 {
312         return IRQ_HANDLED;
313 }
314
315 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
316 {
317         smp_call_function_interrupt();
318
319         return IRQ_HANDLED;
320 }
321
322 static struct irqaction irq_resched = {
323         .handler        = ipi_resched_interrupt,
324         .flags          = IRQF_DISABLED|IRQF_PERCPU,
325         .name           = "IPI_resched"
326 };
327
328 static struct irqaction irq_call = {
329         .handler        = ipi_call_interrupt,
330         .flags          = IRQF_DISABLED|IRQF_PERCPU,
331         .name           = "IPI_call"
332 };
333 #endif /* CONFIG_MIPS_MT_SMP */
334
335 static int gic_resched_int_base;
336 static int gic_call_int_base;
337 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
338 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
339
340 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
341 {
342         return GIC_CALL_INT(cpu);
343 }
344
345 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
346 {
347         return GIC_RESCHED_INT(cpu);
348 }
349
350 static struct irqaction i8259irq = {
351         .handler = no_action,
352         .name = "XT-PIC cascade"
353 };
354
355 static struct irqaction corehi_irqaction = {
356         .handler = no_action,
357         .name = "CoreHi"
358 };
359
360 static msc_irqmap_t __initdata msc_irqmap[] = {
361         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
362         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
363 };
364 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
365
366 static msc_irqmap_t __initdata msc_eicirqmap[] = {
367         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
368         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
369         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
370         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
371         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
372         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
373         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
374         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
375         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
376         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
377 };
378
379 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
380
381 /*
382  * This GIC specific tabular array defines the association between External
383  * Interrupts and CPUs/Core Interrupts. The nature of the External
384  * Interrupts is also defined here - polarity/trigger.
385  */
386
387 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
388 #define X GIC_UNUSED
389
390 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
391         { X, X,            X,           X,              0 },
392         { X, X,            X,           X,              0 },
393         { X, X,            X,           X,              0 },
394         { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
395         { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
396         { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
397         { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
398         { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
399         { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
400         { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
401         { X, X,            X,           X,              0 },
402         { X, X,            X,           X,              0 },
403         { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404         { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
405         { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
406         { X, X,            X,           X,              0 },
407         /* The remainder of this table is initialised by fill_ipi_map */
408 };
409 #undef X
410
411 /*
412  * GCMP needs to be detected before any SMP initialisation
413  */
414 int __init gcmp_probe(unsigned long addr, unsigned long size)
415 {
416         if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
417                 gcmp_present = 0;
418                 return gcmp_present;
419         }
420
421         if (gcmp_present >= 0)
422                 return gcmp_present;
423
424         _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
425         _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
426         gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
427
428         if (gcmp_present)
429                 pr_debug("GCMP present\n");
430         return gcmp_present;
431 }
432
433 /* Return the number of IOCU's present */
434 int __init gcmp_niocu(void)
435 {
436   return gcmp_present ?
437     (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
438     0;
439 }
440
441 /* Set GCMP region attributes */
442 void __init gcmp_setregion(int region, unsigned long base,
443                            unsigned long mask, int type)
444 {
445         GCMPGCBn(CMxBASE, region) = base;
446         GCMPGCBn(CMxMASK, region) = mask | type;
447 }
448
449 #if defined(CONFIG_MIPS_MT_SMP)
450 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
451 {
452         int intr = baseintr + cpu;
453         gic_intr_map[intr].cpunum = cpu;
454         gic_intr_map[intr].pin = cpupin;
455         gic_intr_map[intr].polarity = GIC_POL_POS;
456         gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
457         gic_intr_map[intr].flags = GIC_FLAG_IPI;
458         ipi_map[cpu] |= (1 << (cpupin + 2));
459 }
460
461 static void __init fill_ipi_map(void)
462 {
463         int cpu;
464
465         for (cpu = 0; cpu < NR_CPUS; cpu++) {
466                 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
467                 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
468         }
469 }
470 #endif
471
472 void __init arch_init_ipiirq(int irq, struct irqaction *action)
473 {
474         setup_irq(irq, action);
475         set_irq_handler(irq, handle_percpu_irq);
476 }
477
478 void __init arch_init_irq(void)
479 {
480         init_i8259_irqs();
481
482         if (!cpu_has_veic)
483                 mips_cpu_irq_init();
484
485         if (gcmp_present)  {
486                 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
487                 gic_present = 1;
488         } else {
489                 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
490                         _msc01_biu_base = (unsigned long)
491                                         ioremap_nocache(MSC01_BIU_REG_BASE,
492                                                 MSC01_BIU_ADDRSPACE_SZ);
493                         gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
494                                         MSC01_SC_CFG_GICPRES_MSK) >>
495                                         MSC01_SC_CFG_GICPRES_SHF;
496                 }
497         }
498         if (gic_present)
499                 pr_debug("GIC present\n");
500
501         switch (mips_revision_sconid) {
502         case MIPS_REVISION_SCON_SOCIT:
503         case MIPS_REVISION_SCON_ROCIT:
504                 if (cpu_has_veic)
505                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
506                                         MSC01E_INT_BASE, msc_eicirqmap,
507                                         msc_nr_eicirqs);
508                 else
509                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
510                                         MSC01C_INT_BASE, msc_irqmap,
511                                         msc_nr_irqs);
512                 break;
513
514         case MIPS_REVISION_SCON_SOCITSC:
515         case MIPS_REVISION_SCON_SOCITSCP:
516                 if (cpu_has_veic)
517                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
518                                         MSC01E_INT_BASE, msc_eicirqmap,
519                                         msc_nr_eicirqs);
520                 else
521                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
522                                         MSC01C_INT_BASE, msc_irqmap,
523                                         msc_nr_irqs);
524         }
525
526         if (cpu_has_veic) {
527                 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
528                 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
529                 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
530                 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
531         } else if (cpu_has_vint) {
532                 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
533                 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
534 #ifdef CONFIG_MIPS_MT_SMTC
535                 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
536                         (0x100 << MIPSCPU_INT_I8259A));
537                 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
538                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
539                 /*
540                  * Temporary hack to ensure that the subsidiary device
541                  * interrupts coing in via the i8259A, but associated
542                  * with low IRQ numbers, will restore the Status.IM
543                  * value associated with the i8259A.
544                  */
545                 {
546                         int i;
547
548                         for (i = 0; i < 16; i++)
549                                 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
550                 }
551 #else /* Not SMTC */
552                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
553                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
554                                                 &corehi_irqaction);
555 #endif /* CONFIG_MIPS_MT_SMTC */
556         } else {
557                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
558                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
559                                                 &corehi_irqaction);
560         }
561
562         if (gic_present) {
563                 /* FIXME */
564                 int i;
565 #if defined(CONFIG_MIPS_MT_SMP)
566                 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
567                 gic_resched_int_base = gic_call_int_base - NR_CPUS;
568                 fill_ipi_map();
569 #endif
570                 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
571                                 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
572                 if (!gcmp_present) {
573                         /* Enable the GIC */
574                         i = REG(_msc01_biu_base, MSC01_SC_CFG);
575                         REG(_msc01_biu_base, MSC01_SC_CFG) =
576                                 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
577                         pr_debug("GIC Enabled\n");
578                 }
579 #if defined(CONFIG_MIPS_MT_SMP)
580                 /* set up ipi interrupts */
581                 if (cpu_has_vint) {
582                         set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
583                         set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
584                 }
585                 /* Argh.. this really needs sorting out.. */
586                 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
587                 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
588                 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
589                 write_c0_status(0x1100dc00);
590                 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
591                 for (i = 0; i < NR_CPUS; i++) {
592                         arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
593                                          GIC_RESCHED_INT(i), &irq_resched);
594                         arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
595                                          GIC_CALL_INT(i), &irq_call);
596                 }
597 #endif
598         } else {
599 #if defined(CONFIG_MIPS_MT_SMP)
600                 /* set up ipi interrupts */
601                 if (cpu_has_veic) {
602                         set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
603                         set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
604                         cpu_ipi_resched_irq = MSC01E_INT_SW0;
605                         cpu_ipi_call_irq = MSC01E_INT_SW1;
606                 } else {
607                         if (cpu_has_vint) {
608                                 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
609                                 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
610                         }
611                         cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
612                         cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
613                 }
614                 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
615                 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
616 #endif
617         }
618 }
619
620 void malta_be_init(void)
621 {
622         if (gcmp_present) {
623                 /* Could change CM error mask register */
624         }
625 }
626
627
628 static char *tr[8] = {
629         "mem",  "gcr",  "gic",  "mmio",
630         "0x04", "0x05", "0x06", "0x07"
631 };
632
633 static char *mcmd[32] = {
634         [0x00] = "0x00",
635         [0x01] = "Legacy Write",
636         [0x02] = "Legacy Read",
637         [0x03] = "0x03",
638         [0x04] = "0x04",
639         [0x05] = "0x05",
640         [0x06] = "0x06",
641         [0x07] = "0x07",
642         [0x08] = "Coherent Read Own",
643         [0x09] = "Coherent Read Share",
644         [0x0a] = "Coherent Read Discard",
645         [0x0b] = "Coherent Ready Share Always",
646         [0x0c] = "Coherent Upgrade",
647         [0x0d] = "Coherent Writeback",
648         [0x0e] = "0x0e",
649         [0x0f] = "0x0f",
650         [0x10] = "Coherent Copyback",
651         [0x11] = "Coherent Copyback Invalidate",
652         [0x12] = "Coherent Invalidate",
653         [0x13] = "Coherent Write Invalidate",
654         [0x14] = "Coherent Completion Sync",
655         [0x15] = "0x15",
656         [0x16] = "0x16",
657         [0x17] = "0x17",
658         [0x18] = "0x18",
659         [0x19] = "0x19",
660         [0x1a] = "0x1a",
661         [0x1b] = "0x1b",
662         [0x1c] = "0x1c",
663         [0x1d] = "0x1d",
664         [0x1e] = "0x1e",
665         [0x1f] = "0x1f"
666 };
667
668 static char *core[8] = {
669         "Invalid/OK",   "Invalid/Data",
670         "Shared/OK",    "Shared/Data",
671         "Modified/OK",  "Modified/Data",
672         "Exclusive/OK", "Exclusive/Data"
673 };
674
675 static char *causes[32] = {
676         "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
677         "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
678         "0x08", "0x09", "0x0a", "0x0b",
679         "0x0c", "0x0d", "0x0e", "0x0f",
680         "0x10", "0x11", "0x12", "0x13",
681         "0x14", "0x15", "0x16", "INTVN_WR_ERR",
682         "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
683         "0x1c", "0x1d", "0x1e", "0x1f"
684 };
685
686 int malta_be_handler(struct pt_regs *regs, int is_fixup)
687 {
688         /* This duplicates the handling in do_be which seems wrong */
689         int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
690
691         if (gcmp_present) {
692                 unsigned long cm_error = GCMPGCB(GCMEC);
693                 unsigned long cm_addr = GCMPGCB(GCMEA);
694                 unsigned long cm_other = GCMPGCB(GCMEO);
695                 unsigned long cause, ocause;
696                 char buf[256];
697
698                 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
699                 if (cause != 0) {
700                         cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
701                         if (cause < 16) {
702                                 unsigned long cca_bits = (cm_error >> 15) & 7;
703                                 unsigned long tr_bits = (cm_error >> 12) & 7;
704                                 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
705                                 unsigned long stag_bits = (cm_error >> 3) & 15;
706                                 unsigned long sport_bits = (cm_error >> 0) & 7;
707
708                                 snprintf(buf, sizeof(buf),
709                                          "CCA=%lu TR=%s MCmd=%s STag=%lu "
710                                          "SPort=%lu\n",
711                                          cca_bits, tr[tr_bits], mcmd[mcmd_bits],
712                                          stag_bits, sport_bits);
713                         } else {
714                                 /* glob state & sresp together */
715                                 unsigned long c3_bits = (cm_error >> 18) & 7;
716                                 unsigned long c2_bits = (cm_error >> 15) & 7;
717                                 unsigned long c1_bits = (cm_error >> 12) & 7;
718                                 unsigned long c0_bits = (cm_error >> 9) & 7;
719                                 unsigned long sc_bit = (cm_error >> 8) & 1;
720                                 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
721                                 unsigned long sport_bits = (cm_error >> 0) & 7;
722                                 snprintf(buf, sizeof(buf),
723                                          "C3=%s C2=%s C1=%s C0=%s SC=%s "
724                                          "MCmd=%s SPort=%lu\n",
725                                          core[c3_bits], core[c2_bits],
726                                          core[c1_bits], core[c0_bits],
727                                          sc_bit ? "True" : "False",
728                                          mcmd[mcmd_bits], sport_bits);
729                         }
730
731                         ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
732                                  GCMP_GCB_GMEO_ERROR_2ND_SHF;
733
734                         printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
735                                causes[cause], buf);
736                         printk("CM_ADDR =%08lx\n", cm_addr);
737                         printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
738
739                         /* reprime cause register */
740                         GCMPGCB(GCMEC) = 0;
741                 }
742         }
743
744         return retval;
745 }