Remove obsolete #include <linux/config.h>
[linux-2.6.git] / arch / mips / momentum / ocelot_c / setup.c
1 /*
2  * BRIEF MODULE DESCRIPTION
3  * Momentum Computer Ocelot-C and -CS board dependent boot routines
4  *
5  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
6  * Copyright (C) 2000 RidgeRun, Inc.
7  * Copyright (C) 2001 Red Hat, Inc.
8  * Copyright (C) 2002 Momentum Computer
9  *
10  * Author: Matthew Dharm, Momentum Computer
11  *   mdharm@momenco.com
12  *
13  * Louis Hamilton, Red Hat, Inc.
14  *   hamilton@redhat.com  [MIPS64 modifications]
15  *
16  * Author: RidgeRun, Inc.
17  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18  *
19  * Copyright 2001 MontaVista Software Inc.
20  * Author: jsun@mvista.com or jsun@junsun.net
21  *
22  *  This program is free software; you can redistribute  it and/or modify it
23  *  under  the terms of  the GNU General  Public License as published by the
24  *  Free Software Foundation;  either version 2 of the  License, or (at your
25  *  option) any later version.
26  *
27  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
28  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
29  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
30  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
31  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
33  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
35  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  *
38  *  You should have received a copy of the  GNU General Public License along
39  *  with this program; if not, write  to the Free Software Foundation, Inc.,
40  *  675 Mass Ave, Cambridge, MA 02139, USA.
41  *
42  */
43 #include <linux/bcd.h>
44 #include <linux/init.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/mm.h>
48 #include <linux/swap.h>
49 #include <linux/ioport.h>
50 #include <linux/sched.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/pm.h>
54 #include <linux/timex.h>
55 #include <linux/vmalloc.h>
56 #include <linux/mv643xx.h>
57
58 #include <asm/time.h>
59 #include <asm/bootinfo.h>
60 #include <asm/page.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/pci.h>
64 #include <asm/processor.h>
65 #include <asm/ptrace.h>
66 #include <asm/reboot.h>
67 #include <asm/marvell.h>
68 #include <linux/bootmem.h>
69 #include <linux/blkdev.h>
70 #include "ocelot_c_fpga.h"
71
72 unsigned long marvell_base;
73 extern unsigned long mv64340_sram_base;
74 unsigned long cpu_clock;
75
76 /* These functions are used for rebooting or halting the machine*/
77 extern void momenco_ocelot_restart(char *command);
78 extern void momenco_ocelot_halt(void);
79 extern void momenco_ocelot_power_off(void);
80
81 void momenco_time_init(void);
82
83 static char reset_reason;
84
85 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
86
87 static unsigned long ENTRYLO(unsigned long paddr)
88 {
89         return ((paddr & PAGE_MASK) |
90                (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
91                 _CACHE_UNCACHED)) >> 6;
92 }
93
94 /* setup code for a handoff from a version 2 PMON 2000 PROM */
95 void PMON_v2_setup(void)
96 {
97         /* Some wired TLB entries for the MV64340 and perhiperals. The
98            MV64340 is going to be hit on every IRQ anyway - there's
99            absolutely no point in letting it be a random TLB entry, as
100            it'll just cause needless churning of the TLB. And we use
101            the other half for the serial port, which is just a PITA
102            otherwise :)
103
104                 Device                  Physical        Virtual
105                 MV64340 Internal Regs   0xf4000000      0xf4000000
106                 Ocelot-C[S] PLD (CS0)   0xfc000000      0xfc000000
107                 NVRAM (CS1)             0xfc800000      0xfc800000
108                 UARTs (CS2)             0xfd000000      0xfd000000
109                 Internal SRAM           0xfe000000      0xfe000000
110                 M-Systems DOC (CS3)     0xff000000      0xff000000
111         */
112   printk("PMON_v2_setup\n");
113
114 #ifdef CONFIG_64BIT
115         /* marvell and extra space */
116         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
117         /* fpga, rtc, and uart */
118         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
119         /* m-sys and internal SRAM */
120         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
121
122         marvell_base = 0xfffffffff4000000;
123         mv64340_sram_base = 0xfffffffffe000000;
124 #else
125         /* marvell and extra space */
126         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
127         /* fpga, rtc, and uart */
128         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
129         /* m-sys and internal SRAM */
130         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
131
132         marvell_base = 0xf4000000;
133         mv64340_sram_base = 0xfe000000;
134 #endif
135 }
136
137 unsigned long m48t37y_get_time(void)
138 {
139 #ifdef CONFIG_64BIT
140         unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
141 #else
142         unsigned char* rtc_base = (unsigned char*)0xfc800000;
143 #endif
144         unsigned int year, month, day, hour, min, sec;
145         unsigned long flags;
146
147         spin_lock_irqsave(&rtc_lock, flags);
148         /* stop the update */
149         rtc_base[0x7ff8] = 0x40;
150
151         year = BCD2BIN(rtc_base[0x7fff]);
152         year += BCD2BIN(rtc_base[0x7ff1]) * 100;
153
154         month = BCD2BIN(rtc_base[0x7ffe]);
155
156         day = BCD2BIN(rtc_base[0x7ffd]);
157
158         hour = BCD2BIN(rtc_base[0x7ffb]);
159         min = BCD2BIN(rtc_base[0x7ffa]);
160         sec = BCD2BIN(rtc_base[0x7ff9]);
161
162         /* start the update */
163         rtc_base[0x7ff8] = 0x00;
164         spin_unlock_irqrestore(&rtc_lock, flags);
165
166         return mktime(year, month, day, hour, min, sec);
167 }
168
169 int m48t37y_set_time(unsigned long sec)
170 {
171 #ifdef CONFIG_64BIT
172         unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
173 #else
174         unsigned char* rtc_base = (unsigned char*)0xfc800000;
175 #endif
176         struct rtc_time tm;
177         unsigned long flags;
178
179         /* convert to a more useful format -- note months count from 0 */
180         to_tm(sec, &tm);
181         tm.tm_mon += 1;
182
183         spin_lock_irqsave(&rtc_lock, flags);
184         /* enable writing */
185         rtc_base[0x7ff8] = 0x80;
186
187         /* year */
188         rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
189         rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
190
191         /* month */
192         rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
193
194         /* day */
195         rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
196
197         /* hour/min/sec */
198         rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
199         rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
200         rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
201
202         /* day of week -- not really used, but let's keep it up-to-date */
203         rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
204
205         /* disable writing */
206         rtc_base[0x7ff8] = 0x00;
207         spin_unlock_irqrestore(&rtc_lock, flags);
208
209         return 0;
210 }
211
212 void momenco_timer_setup(struct irqaction *irq)
213 {
214         setup_irq(7, irq);
215 }
216
217 void momenco_time_init(void)
218 {
219 #ifdef CONFIG_CPU_SR71000
220         mips_hpt_frequency = cpu_clock;
221 #elif defined(CONFIG_CPU_RM7000)
222         mips_hpt_frequency = cpu_clock / 2;
223 #else
224 #error Unknown CPU for this board
225 #endif
226         printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
227         board_timer_setup = momenco_timer_setup;
228
229         rtc_mips_get_time = m48t37y_get_time;
230         rtc_mips_set_time = m48t37y_set_time;
231 }
232
233 void __init plat_mem_setup(void)
234 {
235         unsigned int tmpword;
236
237         board_time_init = momenco_time_init;
238
239         _machine_restart = momenco_ocelot_restart;
240         _machine_halt = momenco_ocelot_halt;
241         pm_power_off = momenco_ocelot_power_off;
242
243         /*
244          * initrd_start = (unsigned long)ocelot_initrd_start;
245          * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
246          * initrd_below_start_ok = 1;
247          */
248
249         /* do handoff reconfiguration */
250         PMON_v2_setup();
251
252         /* shut down ethernet ports, just to be sure our memory doesn't get
253          * corrupted by random ethernet traffic.
254          */
255         MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
256         MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
257         MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
258         MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
259         do {}
260           while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
261         do {}
262           while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
263         do {}
264           while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
265         do {}
266           while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
267         MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
268                  MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
269         MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
270                  MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
271
272         /* Turn off the Bit-Error LED */
273         OCELOT_FPGA_WRITE(0x80, CLR);
274
275         tmpword = OCELOT_FPGA_READ(BOARDREV);
276 #ifdef CONFIG_CPU_SR71000
277         if (tmpword < 26)
278                 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
279                         'A'+tmpword);
280         else
281                 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
282                         tmpword);
283 #else
284         if (tmpword < 26)
285                 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
286                         'A'+tmpword);
287         else
288                 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
289                         tmpword);
290 #endif
291
292         tmpword = OCELOT_FPGA_READ(FPGA_REV);
293         printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
294         tmpword = OCELOT_FPGA_READ(RESET_STATUS);
295         printk("Reset reason: 0x%x\n", tmpword);
296         switch (tmpword) {
297                 case 0x1:
298                         printk("  - Power-up reset\n");
299                         break;
300                 case 0x2:
301                         printk("  - Push-button reset\n");
302                         break;
303                 case 0x4:
304                         printk("  - cPCI bus reset\n");
305                         break;
306                 case 0x8:
307                         printk("  - Watchdog reset\n");
308                         break;
309                 case 0x10:
310                         printk("  - Software reset\n");
311                         break;
312                 default:
313                         printk("  - Unknown reset cause\n");
314         }
315         reset_reason = tmpword;
316         OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
317
318         tmpword = OCELOT_FPGA_READ(CPCI_ID);
319         printk("cPCI ID register: 0x%02x\n", tmpword);
320         printk("  - Slot number: %d\n", tmpword & 0x1f);
321         printk("  - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
322         printk("  - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
323
324         tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
325         printk("Board Status register: 0x%02x\n", tmpword);
326         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
327         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
328         printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
329         printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
330
331         switch(tmpword &3) {
332         case 3:
333                 /* 512MiB */
334                 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
335                 break;
336         case 2:
337                 /* 256MiB */
338                 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
339                 break;
340         case 1:
341                 /* 128MiB */
342                 add_memory_region(0x0,  0x80<<20, BOOT_MEM_RAM);
343                 break;
344         case 0:
345                 /* 1GiB -- needs CONFIG_HIGHMEM */
346                 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
347                 break;
348         }
349 }
350
351 #ifndef CONFIG_64BIT
352 /* This needs to be one of the first initcalls, because no I/O port access
353    can work before this */
354 static int io_base_ioremap(void)
355 {
356         /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
357         void *io_remap_range = ioremap(0xc0000000, 0x30000000);
358
359         if (!io_remap_range) {
360                 panic("Could not ioremap I/O port range");
361         }
362         printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
363         set_io_port_base(io_remap_range - 0xc0000000);
364
365         return 0;
366 }
367
368 module_init(io_base_ioremap);
369 #endif