Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
[linux-2.6.git] / arch / mips / mm / c-r4k.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9  */
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/bitops.h>
20
21 #include <asm/bcache.h>
22 #include <asm/bootinfo.h>
23 #include <asm/cache.h>
24 #include <asm/cacheops.h>
25 #include <asm/cpu.h>
26 #include <asm/cpu-features.h>
27 #include <asm/io.h>
28 #include <asm/page.h>
29 #include <asm/pgtable.h>
30 #include <asm/r4kcache.h>
31 #include <asm/sections.h>
32 #include <asm/system.h>
33 #include <asm/mmu_context.h>
34 #include <asm/war.h>
35 #include <asm/cacheflush.h> /* for run_uncached() */
36
37
38 /*
39  * Special Variant of smp_call_function for use by cache functions:
40  *
41  *  o No return value
42  *  o collapses to normal function call on UP kernels
43  *  o collapses to normal function call on systems with a single shared
44  *    primary cache.
45  *  o doesn't disable interrupts on the local CPU
46  */
47 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
48 {
49         preempt_disable();
50
51 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
52         smp_call_function(func, info, 1);
53 #endif
54         func(info);
55         preempt_enable();
56 }
57
58 #if defined(CONFIG_MIPS_CMP)
59 #define cpu_has_safe_index_cacheops 0
60 #else
61 #define cpu_has_safe_index_cacheops 1
62 #endif
63
64 /*
65  * Must die.
66  */
67 static unsigned long icache_size __read_mostly;
68 static unsigned long dcache_size __read_mostly;
69 static unsigned long scache_size __read_mostly;
70
71 /*
72  * Dummy cache handling routines for machines without boardcaches
73  */
74 static void cache_noop(void) {}
75
76 static struct bcache_ops no_sc_ops = {
77         .bc_enable = (void *)cache_noop,
78         .bc_disable = (void *)cache_noop,
79         .bc_wback_inv = (void *)cache_noop,
80         .bc_inv = (void *)cache_noop
81 };
82
83 struct bcache_ops *bcops = &no_sc_ops;
84
85 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
86 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
87
88 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
89 do {                                                                    \
90         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
91                 *(volatile unsigned long *)CKSEG1;                      \
92         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
93                 __asm__ __volatile__("nop;nop;nop;nop");                \
94 } while (0)
95
96 static void (*r4k_blast_dcache_page)(unsigned long addr);
97
98 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
99 {
100         R4600_HIT_CACHEOP_WAR_IMPL;
101         blast_dcache32_page(addr);
102 }
103
104 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
105 {
106         R4600_HIT_CACHEOP_WAR_IMPL;
107         blast_dcache64_page(addr);
108 }
109
110 static void __cpuinit r4k_blast_dcache_page_setup(void)
111 {
112         unsigned long  dc_lsize = cpu_dcache_line_size();
113
114         if (dc_lsize == 0)
115                 r4k_blast_dcache_page = (void *)cache_noop;
116         else if (dc_lsize == 16)
117                 r4k_blast_dcache_page = blast_dcache16_page;
118         else if (dc_lsize == 32)
119                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
120         else if (dc_lsize == 64)
121                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
122 }
123
124 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125
126 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
127 {
128         unsigned long dc_lsize = cpu_dcache_line_size();
129
130         if (dc_lsize == 0)
131                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
132         else if (dc_lsize == 16)
133                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
134         else if (dc_lsize == 32)
135                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
136         else if (dc_lsize == 64)
137                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
138 }
139
140 static void (* r4k_blast_dcache)(void);
141
142 static void __cpuinit r4k_blast_dcache_setup(void)
143 {
144         unsigned long dc_lsize = cpu_dcache_line_size();
145
146         if (dc_lsize == 0)
147                 r4k_blast_dcache = (void *)cache_noop;
148         else if (dc_lsize == 16)
149                 r4k_blast_dcache = blast_dcache16;
150         else if (dc_lsize == 32)
151                 r4k_blast_dcache = blast_dcache32;
152         else if (dc_lsize == 64)
153                 r4k_blast_dcache = blast_dcache64;
154 }
155
156 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
157 #define JUMP_TO_ALIGN(order) \
158         __asm__ __volatile__( \
159                 "b\t1f\n\t" \
160                 ".align\t" #order "\n\t" \
161                 "1:\n\t" \
162                 )
163 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
164 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
165
166 static inline void blast_r4600_v1_icache32(void)
167 {
168         unsigned long flags;
169
170         local_irq_save(flags);
171         blast_icache32();
172         local_irq_restore(flags);
173 }
174
175 static inline void tx49_blast_icache32(void)
176 {
177         unsigned long start = INDEX_BASE;
178         unsigned long end = start + current_cpu_data.icache.waysize;
179         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
180         unsigned long ws_end = current_cpu_data.icache.ways <<
181                                current_cpu_data.icache.waybit;
182         unsigned long ws, addr;
183
184         CACHE32_UNROLL32_ALIGN2;
185         /* I'm in even chunk.  blast odd chunks */
186         for (ws = 0; ws < ws_end; ws += ws_inc)
187                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
188                         cache32_unroll32(addr|ws, Index_Invalidate_I);
189         CACHE32_UNROLL32_ALIGN;
190         /* I'm in odd chunk.  blast even chunks */
191         for (ws = 0; ws < ws_end; ws += ws_inc)
192                 for (addr = start; addr < end; addr += 0x400 * 2)
193                         cache32_unroll32(addr|ws, Index_Invalidate_I);
194 }
195
196 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
197 {
198         unsigned long flags;
199
200         local_irq_save(flags);
201         blast_icache32_page_indexed(page);
202         local_irq_restore(flags);
203 }
204
205 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
206 {
207         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
208         unsigned long start = INDEX_BASE + (page & indexmask);
209         unsigned long end = start + PAGE_SIZE;
210         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
211         unsigned long ws_end = current_cpu_data.icache.ways <<
212                                current_cpu_data.icache.waybit;
213         unsigned long ws, addr;
214
215         CACHE32_UNROLL32_ALIGN2;
216         /* I'm in even chunk.  blast odd chunks */
217         for (ws = 0; ws < ws_end; ws += ws_inc)
218                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
219                         cache32_unroll32(addr|ws, Index_Invalidate_I);
220         CACHE32_UNROLL32_ALIGN;
221         /* I'm in odd chunk.  blast even chunks */
222         for (ws = 0; ws < ws_end; ws += ws_inc)
223                 for (addr = start; addr < end; addr += 0x400 * 2)
224                         cache32_unroll32(addr|ws, Index_Invalidate_I);
225 }
226
227 static void (* r4k_blast_icache_page)(unsigned long addr);
228
229 static void __cpuinit r4k_blast_icache_page_setup(void)
230 {
231         unsigned long ic_lsize = cpu_icache_line_size();
232
233         if (ic_lsize == 0)
234                 r4k_blast_icache_page = (void *)cache_noop;
235         else if (ic_lsize == 16)
236                 r4k_blast_icache_page = blast_icache16_page;
237         else if (ic_lsize == 32)
238                 r4k_blast_icache_page = blast_icache32_page;
239         else if (ic_lsize == 64)
240                 r4k_blast_icache_page = blast_icache64_page;
241 }
242
243
244 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
245
246 static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
247 {
248         unsigned long ic_lsize = cpu_icache_line_size();
249
250         if (ic_lsize == 0)
251                 r4k_blast_icache_page_indexed = (void *)cache_noop;
252         else if (ic_lsize == 16)
253                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
254         else if (ic_lsize == 32) {
255                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
256                         r4k_blast_icache_page_indexed =
257                                 blast_icache32_r4600_v1_page_indexed;
258                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
259                         r4k_blast_icache_page_indexed =
260                                 tx49_blast_icache32_page_indexed;
261                 else
262                         r4k_blast_icache_page_indexed =
263                                 blast_icache32_page_indexed;
264         } else if (ic_lsize == 64)
265                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
266 }
267
268 static void (* r4k_blast_icache)(void);
269
270 static void __cpuinit r4k_blast_icache_setup(void)
271 {
272         unsigned long ic_lsize = cpu_icache_line_size();
273
274         if (ic_lsize == 0)
275                 r4k_blast_icache = (void *)cache_noop;
276         else if (ic_lsize == 16)
277                 r4k_blast_icache = blast_icache16;
278         else if (ic_lsize == 32) {
279                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
280                         r4k_blast_icache = blast_r4600_v1_icache32;
281                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
282                         r4k_blast_icache = tx49_blast_icache32;
283                 else
284                         r4k_blast_icache = blast_icache32;
285         } else if (ic_lsize == 64)
286                 r4k_blast_icache = blast_icache64;
287 }
288
289 static void (* r4k_blast_scache_page)(unsigned long addr);
290
291 static void __cpuinit r4k_blast_scache_page_setup(void)
292 {
293         unsigned long sc_lsize = cpu_scache_line_size();
294
295         if (scache_size == 0)
296                 r4k_blast_scache_page = (void *)cache_noop;
297         else if (sc_lsize == 16)
298                 r4k_blast_scache_page = blast_scache16_page;
299         else if (sc_lsize == 32)
300                 r4k_blast_scache_page = blast_scache32_page;
301         else if (sc_lsize == 64)
302                 r4k_blast_scache_page = blast_scache64_page;
303         else if (sc_lsize == 128)
304                 r4k_blast_scache_page = blast_scache128_page;
305 }
306
307 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
308
309 static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
310 {
311         unsigned long sc_lsize = cpu_scache_line_size();
312
313         if (scache_size == 0)
314                 r4k_blast_scache_page_indexed = (void *)cache_noop;
315         else if (sc_lsize == 16)
316                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
317         else if (sc_lsize == 32)
318                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
319         else if (sc_lsize == 64)
320                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
321         else if (sc_lsize == 128)
322                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
323 }
324
325 static void (* r4k_blast_scache)(void);
326
327 static void __cpuinit r4k_blast_scache_setup(void)
328 {
329         unsigned long sc_lsize = cpu_scache_line_size();
330
331         if (scache_size == 0)
332                 r4k_blast_scache = (void *)cache_noop;
333         else if (sc_lsize == 16)
334                 r4k_blast_scache = blast_scache16;
335         else if (sc_lsize == 32)
336                 r4k_blast_scache = blast_scache32;
337         else if (sc_lsize == 64)
338                 r4k_blast_scache = blast_scache64;
339         else if (sc_lsize == 128)
340                 r4k_blast_scache = blast_scache128;
341 }
342
343 static inline void local_r4k___flush_cache_all(void * args)
344 {
345 #if defined(CONFIG_CPU_LOONGSON2)
346         r4k_blast_scache();
347         return;
348 #endif
349         r4k_blast_dcache();
350         r4k_blast_icache();
351
352         switch (current_cpu_type()) {
353         case CPU_R4000SC:
354         case CPU_R4000MC:
355         case CPU_R4400SC:
356         case CPU_R4400MC:
357         case CPU_R10000:
358         case CPU_R12000:
359         case CPU_R14000:
360                 r4k_blast_scache();
361         }
362 }
363
364 static void r4k___flush_cache_all(void)
365 {
366         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
367 }
368
369 static inline int has_valid_asid(const struct mm_struct *mm)
370 {
371 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
372         int i;
373
374         for_each_online_cpu(i)
375                 if (cpu_context(i, mm))
376                         return 1;
377
378         return 0;
379 #else
380         return cpu_context(smp_processor_id(), mm);
381 #endif
382 }
383
384 static void r4k__flush_cache_vmap(void)
385 {
386         r4k_blast_dcache();
387 }
388
389 static void r4k__flush_cache_vunmap(void)
390 {
391         r4k_blast_dcache();
392 }
393
394 static inline void local_r4k_flush_cache_range(void * args)
395 {
396         struct vm_area_struct *vma = args;
397         int exec = vma->vm_flags & VM_EXEC;
398
399         if (!(has_valid_asid(vma->vm_mm)))
400                 return;
401
402         r4k_blast_dcache();
403         if (exec)
404                 r4k_blast_icache();
405 }
406
407 static void r4k_flush_cache_range(struct vm_area_struct *vma,
408         unsigned long start, unsigned long end)
409 {
410         int exec = vma->vm_flags & VM_EXEC;
411
412         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
413                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
414 }
415
416 static inline void local_r4k_flush_cache_mm(void * args)
417 {
418         struct mm_struct *mm = args;
419
420         if (!has_valid_asid(mm))
421                 return;
422
423         /*
424          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
425          * only flush the primary caches but R10000 and R12000 behave sane ...
426          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
427          * caches, so we can bail out early.
428          */
429         if (current_cpu_type() == CPU_R4000SC ||
430             current_cpu_type() == CPU_R4000MC ||
431             current_cpu_type() == CPU_R4400SC ||
432             current_cpu_type() == CPU_R4400MC) {
433                 r4k_blast_scache();
434                 return;
435         }
436
437         r4k_blast_dcache();
438 }
439
440 static void r4k_flush_cache_mm(struct mm_struct *mm)
441 {
442         if (!cpu_has_dc_aliases)
443                 return;
444
445         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
446 }
447
448 struct flush_cache_page_args {
449         struct vm_area_struct *vma;
450         unsigned long addr;
451         unsigned long pfn;
452 };
453
454 static inline void local_r4k_flush_cache_page(void *args)
455 {
456         struct flush_cache_page_args *fcp_args = args;
457         struct vm_area_struct *vma = fcp_args->vma;
458         unsigned long addr = fcp_args->addr;
459         struct page *page = pfn_to_page(fcp_args->pfn);
460         int exec = vma->vm_flags & VM_EXEC;
461         struct mm_struct *mm = vma->vm_mm;
462         int map_coherent = 0;
463         pgd_t *pgdp;
464         pud_t *pudp;
465         pmd_t *pmdp;
466         pte_t *ptep;
467         void *vaddr;
468
469         /*
470          * If ownes no valid ASID yet, cannot possibly have gotten
471          * this page into the cache.
472          */
473         if (!has_valid_asid(mm))
474                 return;
475
476         addr &= PAGE_MASK;
477         pgdp = pgd_offset(mm, addr);
478         pudp = pud_offset(pgdp, addr);
479         pmdp = pmd_offset(pudp, addr);
480         ptep = pte_offset(pmdp, addr);
481
482         /*
483          * If the page isn't marked valid, the page cannot possibly be
484          * in the cache.
485          */
486         if (!(pte_present(*ptep)))
487                 return;
488
489         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
490                 vaddr = NULL;
491         else {
492                 /*
493                  * Use kmap_coherent or kmap_atomic to do flushes for
494                  * another ASID than the current one.
495                  */
496                 map_coherent = (cpu_has_dc_aliases &&
497                                 page_mapped(page) && !Page_dcache_dirty(page));
498                 if (map_coherent)
499                         vaddr = kmap_coherent(page, addr);
500                 else
501                         vaddr = kmap_atomic(page, KM_USER0);
502                 addr = (unsigned long)vaddr;
503         }
504
505         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
506                 r4k_blast_dcache_page(addr);
507                 if (exec && !cpu_icache_snoops_remote_store)
508                         r4k_blast_scache_page(addr);
509         }
510         if (exec) {
511                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
512                         int cpu = smp_processor_id();
513
514                         if (cpu_context(cpu, mm) != 0)
515                                 drop_mmu_context(mm, cpu);
516                 } else
517                         r4k_blast_icache_page(addr);
518         }
519
520         if (vaddr) {
521                 if (map_coherent)
522                         kunmap_coherent();
523                 else
524                         kunmap_atomic(vaddr, KM_USER0);
525         }
526 }
527
528 static void r4k_flush_cache_page(struct vm_area_struct *vma,
529         unsigned long addr, unsigned long pfn)
530 {
531         struct flush_cache_page_args args;
532
533         args.vma = vma;
534         args.addr = addr;
535         args.pfn = pfn;
536
537         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
538 }
539
540 static inline void local_r4k_flush_data_cache_page(void * addr)
541 {
542         r4k_blast_dcache_page((unsigned long) addr);
543 }
544
545 static void r4k_flush_data_cache_page(unsigned long addr)
546 {
547         if (in_atomic())
548                 local_r4k_flush_data_cache_page((void *)addr);
549         else
550                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
551 }
552
553 struct flush_icache_range_args {
554         unsigned long start;
555         unsigned long end;
556 };
557
558 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
559 {
560         if (!cpu_has_ic_fills_f_dc) {
561                 if (end - start >= dcache_size) {
562                         r4k_blast_dcache();
563                 } else {
564                         R4600_HIT_CACHEOP_WAR_IMPL;
565                         protected_blast_dcache_range(start, end);
566                 }
567         }
568
569         if (end - start > icache_size)
570                 r4k_blast_icache();
571         else
572                 protected_blast_icache_range(start, end);
573 }
574
575 static inline void local_r4k_flush_icache_range_ipi(void *args)
576 {
577         struct flush_icache_range_args *fir_args = args;
578         unsigned long start = fir_args->start;
579         unsigned long end = fir_args->end;
580
581         local_r4k_flush_icache_range(start, end);
582 }
583
584 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
585 {
586         struct flush_icache_range_args args;
587
588         args.start = start;
589         args.end = end;
590
591         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
592         instruction_hazard();
593 }
594
595 #ifdef CONFIG_DMA_NONCOHERENT
596
597 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
598 {
599         /* Catch bad driver code */
600         BUG_ON(size == 0);
601
602         if (cpu_has_inclusive_pcaches) {
603                 if (size >= scache_size)
604                         r4k_blast_scache();
605                 else
606                         blast_scache_range(addr, addr + size);
607                 __sync();
608                 return;
609         }
610
611         /*
612          * Either no secondary cache or the available caches don't have the
613          * subset property so we have to flush the primary caches
614          * explicitly
615          */
616         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
617                 r4k_blast_dcache();
618         } else {
619                 R4600_HIT_CACHEOP_WAR_IMPL;
620                 blast_dcache_range(addr, addr + size);
621         }
622
623         bc_wback_inv(addr, size);
624         __sync();
625 }
626
627 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
628 {
629         /* Catch bad driver code */
630         BUG_ON(size == 0);
631
632         if (cpu_has_inclusive_pcaches) {
633                 if (size >= scache_size)
634                         r4k_blast_scache();
635                 else {
636                         unsigned long lsize = cpu_scache_line_size();
637                         unsigned long almask = ~(lsize - 1);
638
639                         /*
640                          * There is no clearly documented alignment requirement
641                          * for the cache instruction on MIPS processors and
642                          * some processors, among them the RM5200 and RM7000
643                          * QED processors will throw an address error for cache
644                          * hit ops with insufficient alignment.  Solved by
645                          * aligning the address to cache line size.
646                          */
647                         cache_op(Hit_Writeback_Inv_SD, addr & almask);
648                         cache_op(Hit_Writeback_Inv_SD,
649                                  (addr + size - 1) & almask);
650                         blast_inv_scache_range(addr, addr + size);
651                 }
652                 __sync();
653                 return;
654         }
655
656         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
657                 r4k_blast_dcache();
658         } else {
659                 unsigned long lsize = cpu_dcache_line_size();
660                 unsigned long almask = ~(lsize - 1);
661
662                 R4600_HIT_CACHEOP_WAR_IMPL;
663                 cache_op(Hit_Writeback_Inv_D, addr & almask);
664                 cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
665                 blast_inv_dcache_range(addr, addr + size);
666         }
667
668         bc_inv(addr, size);
669         __sync();
670 }
671 #endif /* CONFIG_DMA_NONCOHERENT */
672
673 /*
674  * While we're protected against bad userland addresses we don't care
675  * very much about what happens in that case.  Usually a segmentation
676  * fault will dump the process later on anyway ...
677  */
678 static void local_r4k_flush_cache_sigtramp(void * arg)
679 {
680         unsigned long ic_lsize = cpu_icache_line_size();
681         unsigned long dc_lsize = cpu_dcache_line_size();
682         unsigned long sc_lsize = cpu_scache_line_size();
683         unsigned long addr = (unsigned long) arg;
684
685         R4600_HIT_CACHEOP_WAR_IMPL;
686         if (dc_lsize)
687                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
688         if (!cpu_icache_snoops_remote_store && scache_size)
689                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
690         if (ic_lsize)
691                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
692         if (MIPS4K_ICACHE_REFILL_WAR) {
693                 __asm__ __volatile__ (
694                         ".set push\n\t"
695                         ".set noat\n\t"
696                         ".set mips3\n\t"
697 #ifdef CONFIG_32BIT
698                         "la     $at,1f\n\t"
699 #endif
700 #ifdef CONFIG_64BIT
701                         "dla    $at,1f\n\t"
702 #endif
703                         "cache  %0,($at)\n\t"
704                         "nop; nop; nop\n"
705                         "1:\n\t"
706                         ".set pop"
707                         :
708                         : "i" (Hit_Invalidate_I));
709         }
710         if (MIPS_CACHE_SYNC_WAR)
711                 __asm__ __volatile__ ("sync");
712 }
713
714 static void r4k_flush_cache_sigtramp(unsigned long addr)
715 {
716         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
717 }
718
719 static void r4k_flush_icache_all(void)
720 {
721         if (cpu_has_vtag_icache)
722                 r4k_blast_icache();
723 }
724
725 static inline void rm7k_erratum31(void)
726 {
727         const unsigned long ic_lsize = 32;
728         unsigned long addr;
729
730         /* RM7000 erratum #31. The icache is screwed at startup. */
731         write_c0_taglo(0);
732         write_c0_taghi(0);
733
734         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
735                 __asm__ __volatile__ (
736                         ".set push\n\t"
737                         ".set noreorder\n\t"
738                         ".set mips3\n\t"
739                         "cache\t%1, 0(%0)\n\t"
740                         "cache\t%1, 0x1000(%0)\n\t"
741                         "cache\t%1, 0x2000(%0)\n\t"
742                         "cache\t%1, 0x3000(%0)\n\t"
743                         "cache\t%2, 0(%0)\n\t"
744                         "cache\t%2, 0x1000(%0)\n\t"
745                         "cache\t%2, 0x2000(%0)\n\t"
746                         "cache\t%2, 0x3000(%0)\n\t"
747                         "cache\t%1, 0(%0)\n\t"
748                         "cache\t%1, 0x1000(%0)\n\t"
749                         "cache\t%1, 0x2000(%0)\n\t"
750                         "cache\t%1, 0x3000(%0)\n\t"
751                         ".set pop\n"
752                         :
753                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
754         }
755 }
756
757 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
758         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
759 };
760
761 static void __cpuinit probe_pcache(void)
762 {
763         struct cpuinfo_mips *c = &current_cpu_data;
764         unsigned int config = read_c0_config();
765         unsigned int prid = read_c0_prid();
766         unsigned long config1;
767         unsigned int lsize;
768
769         switch (c->cputype) {
770         case CPU_R4600:                 /* QED style two way caches? */
771         case CPU_R4700:
772         case CPU_R5000:
773         case CPU_NEVADA:
774                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
775                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
776                 c->icache.ways = 2;
777                 c->icache.waybit = __ffs(icache_size/2);
778
779                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
780                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
781                 c->dcache.ways = 2;
782                 c->dcache.waybit= __ffs(dcache_size/2);
783
784                 c->options |= MIPS_CPU_CACHE_CDEX_P;
785                 break;
786
787         case CPU_R5432:
788         case CPU_R5500:
789                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
790                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
791                 c->icache.ways = 2;
792                 c->icache.waybit= 0;
793
794                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
795                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
796                 c->dcache.ways = 2;
797                 c->dcache.waybit = 0;
798
799                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
800                 break;
801
802         case CPU_TX49XX:
803                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
804                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
805                 c->icache.ways = 4;
806                 c->icache.waybit= 0;
807
808                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
809                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
810                 c->dcache.ways = 4;
811                 c->dcache.waybit = 0;
812
813                 c->options |= MIPS_CPU_CACHE_CDEX_P;
814                 c->options |= MIPS_CPU_PREFETCH;
815                 break;
816
817         case CPU_R4000PC:
818         case CPU_R4000SC:
819         case CPU_R4000MC:
820         case CPU_R4400PC:
821         case CPU_R4400SC:
822         case CPU_R4400MC:
823         case CPU_R4300:
824                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
825                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
826                 c->icache.ways = 1;
827                 c->icache.waybit = 0;   /* doesn't matter */
828
829                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
830                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
831                 c->dcache.ways = 1;
832                 c->dcache.waybit = 0;   /* does not matter */
833
834                 c->options |= MIPS_CPU_CACHE_CDEX_P;
835                 break;
836
837         case CPU_R10000:
838         case CPU_R12000:
839         case CPU_R14000:
840                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
841                 c->icache.linesz = 64;
842                 c->icache.ways = 2;
843                 c->icache.waybit = 0;
844
845                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
846                 c->dcache.linesz = 32;
847                 c->dcache.ways = 2;
848                 c->dcache.waybit = 0;
849
850                 c->options |= MIPS_CPU_PREFETCH;
851                 break;
852
853         case CPU_VR4133:
854                 write_c0_config(config & ~VR41_CONF_P4K);
855         case CPU_VR4131:
856                 /* Workaround for cache instruction bug of VR4131 */
857                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
858                     c->processor_id == 0x0c82U) {
859                         config |= 0x00400000U;
860                         if (c->processor_id == 0x0c80U)
861                                 config |= VR41_CONF_BP;
862                         write_c0_config(config);
863                 } else
864                         c->options |= MIPS_CPU_CACHE_CDEX_P;
865
866                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
867                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
868                 c->icache.ways = 2;
869                 c->icache.waybit = __ffs(icache_size/2);
870
871                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
872                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
873                 c->dcache.ways = 2;
874                 c->dcache.waybit = __ffs(dcache_size/2);
875                 break;
876
877         case CPU_VR41XX:
878         case CPU_VR4111:
879         case CPU_VR4121:
880         case CPU_VR4122:
881         case CPU_VR4181:
882         case CPU_VR4181A:
883                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
884                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
885                 c->icache.ways = 1;
886                 c->icache.waybit = 0;   /* doesn't matter */
887
888                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
889                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
890                 c->dcache.ways = 1;
891                 c->dcache.waybit = 0;   /* does not matter */
892
893                 c->options |= MIPS_CPU_CACHE_CDEX_P;
894                 break;
895
896         case CPU_RM7000:
897                 rm7k_erratum31();
898
899         case CPU_RM9000:
900                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
901                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
902                 c->icache.ways = 4;
903                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
904
905                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
906                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
907                 c->dcache.ways = 4;
908                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
909
910 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
911                 c->options |= MIPS_CPU_CACHE_CDEX_P;
912 #endif
913                 c->options |= MIPS_CPU_PREFETCH;
914                 break;
915
916         case CPU_LOONGSON2:
917                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
918                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
919                 if (prid & 0x3)
920                         c->icache.ways = 4;
921                 else
922                         c->icache.ways = 2;
923                 c->icache.waybit = 0;
924
925                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
926                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
927                 if (prid & 0x3)
928                         c->dcache.ways = 4;
929                 else
930                         c->dcache.ways = 2;
931                 c->dcache.waybit = 0;
932                 break;
933
934         default:
935                 if (!(config & MIPS_CONF_M))
936                         panic("Don't know how to probe P-caches on this cpu.");
937
938                 /*
939                  * So we seem to be a MIPS32 or MIPS64 CPU
940                  * So let's probe the I-cache ...
941                  */
942                 config1 = read_c0_config1();
943
944                 if ((lsize = ((config1 >> 19) & 7)))
945                         c->icache.linesz = 2 << lsize;
946                 else
947                         c->icache.linesz = lsize;
948                 c->icache.sets = 64 << ((config1 >> 22) & 7);
949                 c->icache.ways = 1 + ((config1 >> 16) & 7);
950
951                 icache_size = c->icache.sets *
952                               c->icache.ways *
953                               c->icache.linesz;
954                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
955
956                 if (config & 0x8)               /* VI bit */
957                         c->icache.flags |= MIPS_CACHE_VTAG;
958
959                 /*
960                  * Now probe the MIPS32 / MIPS64 data cache.
961                  */
962                 c->dcache.flags = 0;
963
964                 if ((lsize = ((config1 >> 10) & 7)))
965                         c->dcache.linesz = 2 << lsize;
966                 else
967                         c->dcache.linesz= lsize;
968                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
969                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
970
971                 dcache_size = c->dcache.sets *
972                               c->dcache.ways *
973                               c->dcache.linesz;
974                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
975
976                 c->options |= MIPS_CPU_PREFETCH;
977                 break;
978         }
979
980         /*
981          * Processor configuration sanity check for the R4000SC erratum
982          * #5.  With page sizes larger than 32kB there is no possibility
983          * to get a VCE exception anymore so we don't care about this
984          * misconfiguration.  The case is rather theoretical anyway;
985          * presumably no vendor is shipping his hardware in the "bad"
986          * configuration.
987          */
988         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
989             !(config & CONF_SC) && c->icache.linesz != 16 &&
990             PAGE_SIZE <= 0x8000)
991                 panic("Improper R4000SC processor configuration detected");
992
993         /* compute a couple of other cache variables */
994         c->icache.waysize = icache_size / c->icache.ways;
995         c->dcache.waysize = dcache_size / c->dcache.ways;
996
997         c->icache.sets = c->icache.linesz ?
998                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
999         c->dcache.sets = c->dcache.linesz ?
1000                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1001
1002         /*
1003          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1004          * 2-way virtually indexed so normally would suffer from aliases.  So
1005          * normally they'd suffer from aliases but magic in the hardware deals
1006          * with that for us so we don't need to take care ourselves.
1007          */
1008         switch (c->cputype) {
1009         case CPU_20KC:
1010         case CPU_25KF:
1011         case CPU_SB1:
1012         case CPU_SB1A:
1013         case CPU_XLR:
1014                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1015                 break;
1016
1017         case CPU_R10000:
1018         case CPU_R12000:
1019         case CPU_R14000:
1020                 break;
1021
1022         case CPU_24K:
1023         case CPU_34K:
1024         case CPU_74K:
1025         case CPU_1004K:
1026                 if ((read_c0_config7() & (1 << 16))) {
1027                         /* effectively physically indexed dcache,
1028                            thus no virtual aliases. */
1029                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1030                         break;
1031                 }
1032         default:
1033                 if (c->dcache.waysize > PAGE_SIZE)
1034                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1035         }
1036
1037         switch (c->cputype) {
1038         case CPU_20KC:
1039                 /*
1040                  * Some older 20Kc chips doesn't have the 'VI' bit in
1041                  * the config register.
1042                  */
1043                 c->icache.flags |= MIPS_CACHE_VTAG;
1044                 break;
1045
1046         case CPU_ALCHEMY:
1047                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1048                 break;
1049         }
1050
1051 #ifdef  CONFIG_CPU_LOONGSON2
1052         /*
1053          * LOONGSON2 has 4 way icache, but when using indexed cache op,
1054          * one op will act on all 4 ways
1055          */
1056         c->icache.ways = 1;
1057 #endif
1058
1059         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1060                icache_size >> 10,
1061                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1062                way_string[c->icache.ways], c->icache.linesz);
1063
1064         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1065                dcache_size >> 10, way_string[c->dcache.ways],
1066                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1067                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1068                         "cache aliases" : "no aliases",
1069                c->dcache.linesz);
1070 }
1071
1072 /*
1073  * If you even _breathe_ on this function, look at the gcc output and make sure
1074  * it does not pop things on and off the stack for the cache sizing loop that
1075  * executes in KSEG1 space or else you will crash and burn badly.  You have
1076  * been warned.
1077  */
1078 static int __cpuinit probe_scache(void)
1079 {
1080         unsigned long flags, addr, begin, end, pow2;
1081         unsigned int config = read_c0_config();
1082         struct cpuinfo_mips *c = &current_cpu_data;
1083
1084         if (config & CONF_SC)
1085                 return 0;
1086
1087         begin = (unsigned long) &_stext;
1088         begin &= ~((4 * 1024 * 1024) - 1);
1089         end = begin + (4 * 1024 * 1024);
1090
1091         /*
1092          * This is such a bitch, you'd think they would make it easy to do
1093          * this.  Away you daemons of stupidity!
1094          */
1095         local_irq_save(flags);
1096
1097         /* Fill each size-multiple cache line with a valid tag. */
1098         pow2 = (64 * 1024);
1099         for (addr = begin; addr < end; addr = (begin + pow2)) {
1100                 unsigned long *p = (unsigned long *) addr;
1101                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1102                 pow2 <<= 1;
1103         }
1104
1105         /* Load first line with zero (therefore invalid) tag. */
1106         write_c0_taglo(0);
1107         write_c0_taghi(0);
1108         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1109         cache_op(Index_Store_Tag_I, begin);
1110         cache_op(Index_Store_Tag_D, begin);
1111         cache_op(Index_Store_Tag_SD, begin);
1112
1113         /* Now search for the wrap around point. */
1114         pow2 = (128 * 1024);
1115         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1116                 cache_op(Index_Load_Tag_SD, addr);
1117                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1118                 if (!read_c0_taglo())
1119                         break;
1120                 pow2 <<= 1;
1121         }
1122         local_irq_restore(flags);
1123         addr -= begin;
1124
1125         scache_size = addr;
1126         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1127         c->scache.ways = 1;
1128         c->dcache.waybit = 0;           /* does not matter */
1129
1130         return 1;
1131 }
1132
1133 #if defined(CONFIG_CPU_LOONGSON2)
1134 static void __init loongson2_sc_init(void)
1135 {
1136         struct cpuinfo_mips *c = &current_cpu_data;
1137
1138         scache_size = 512*1024;
1139         c->scache.linesz = 32;
1140         c->scache.ways = 4;
1141         c->scache.waybit = 0;
1142         c->scache.waysize = scache_size / (c->scache.ways);
1143         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1144         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1145                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1146
1147         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1148 }
1149 #endif
1150
1151 extern int r5k_sc_init(void);
1152 extern int rm7k_sc_init(void);
1153 extern int mips_sc_init(void);
1154
1155 static void __cpuinit setup_scache(void)
1156 {
1157         struct cpuinfo_mips *c = &current_cpu_data;
1158         unsigned int config = read_c0_config();
1159         int sc_present = 0;
1160
1161         /*
1162          * Do the probing thing on R4000SC and R4400SC processors.  Other
1163          * processors don't have a S-cache that would be relevant to the
1164          * Linux memory management.
1165          */
1166         switch (c->cputype) {
1167         case CPU_R4000SC:
1168         case CPU_R4000MC:
1169         case CPU_R4400SC:
1170         case CPU_R4400MC:
1171                 sc_present = run_uncached(probe_scache);
1172                 if (sc_present)
1173                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1174                 break;
1175
1176         case CPU_R10000:
1177         case CPU_R12000:
1178         case CPU_R14000:
1179                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1180                 c->scache.linesz = 64 << ((config >> 13) & 1);
1181                 c->scache.ways = 2;
1182                 c->scache.waybit= 0;
1183                 sc_present = 1;
1184                 break;
1185
1186         case CPU_R5000:
1187         case CPU_NEVADA:
1188 #ifdef CONFIG_R5000_CPU_SCACHE
1189                 r5k_sc_init();
1190 #endif
1191                 return;
1192
1193         case CPU_RM7000:
1194         case CPU_RM9000:
1195 #ifdef CONFIG_RM7000_CPU_SCACHE
1196                 rm7k_sc_init();
1197 #endif
1198                 return;
1199
1200 #if defined(CONFIG_CPU_LOONGSON2)
1201         case CPU_LOONGSON2:
1202                 loongson2_sc_init();
1203                 return;
1204 #endif
1205
1206         default:
1207                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1208                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1209                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1210                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1211 #ifdef CONFIG_MIPS_CPU_SCACHE
1212                         if (mips_sc_init ()) {
1213                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1214                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1215                                        scache_size >> 10,
1216                                        way_string[c->scache.ways], c->scache.linesz);
1217                         }
1218 #else
1219                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1220                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1221 #endif
1222                         return;
1223                 }
1224                 sc_present = 0;
1225         }
1226
1227         if (!sc_present)
1228                 return;
1229
1230         /* compute a couple of other cache variables */
1231         c->scache.waysize = scache_size / c->scache.ways;
1232
1233         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1234
1235         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1236                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1237
1238         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1239 }
1240
1241 void au1x00_fixup_config_od(void)
1242 {
1243         /*
1244          * c0_config.od (bit 19) was write only (and read as 0)
1245          * on the early revisions of Alchemy SOCs.  It disables the bus
1246          * transaction overlapping and needs to be set to fix various errata.
1247          */
1248         switch (read_c0_prid()) {
1249         case 0x00030100: /* Au1000 DA */
1250         case 0x00030201: /* Au1000 HA */
1251         case 0x00030202: /* Au1000 HB */
1252         case 0x01030200: /* Au1500 AB */
1253         /*
1254          * Au1100 errata actually keeps silence about this bit, so we set it
1255          * just in case for those revisions that require it to be set according
1256          * to the (now gone) cpu table.
1257          */
1258         case 0x02030200: /* Au1100 AB */
1259         case 0x02030201: /* Au1100 BA */
1260         case 0x02030202: /* Au1100 BC */
1261                 set_c0_config(1 << 19);
1262                 break;
1263         }
1264 }
1265
1266 /* CP0 hazard avoidance. */
1267 #define NXP_BARRIER()                                                   \
1268          __asm__ __volatile__(                                          \
1269         ".set noreorder\n\t"                                            \
1270         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1271         ".set reorder\n\t")
1272
1273 static void nxp_pr4450_fixup_config(void)
1274 {
1275         unsigned long config0;
1276
1277         config0 = read_c0_config();
1278
1279         /* clear all three cache coherency fields */
1280         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1281         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1282                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1283                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1284         write_c0_config(config0);
1285         NXP_BARRIER();
1286 }
1287
1288 static int __cpuinitdata cca = -1;
1289
1290 static int __init cca_setup(char *str)
1291 {
1292         get_option(&str, &cca);
1293
1294         return 1;
1295 }
1296
1297 __setup("cca=", cca_setup);
1298
1299 static void __cpuinit coherency_setup(void)
1300 {
1301         if (cca < 0 || cca > 7)
1302                 cca = read_c0_config() & CONF_CM_CMASK;
1303         _page_cachable_default = cca << _CACHE_SHIFT;
1304
1305         pr_debug("Using cache attribute %d\n", cca);
1306         change_c0_config(CONF_CM_CMASK, cca);
1307
1308         /*
1309          * c0_status.cu=0 specifies that updates by the sc instruction use
1310          * the coherency mode specified by the TLB; 1 means cachable
1311          * coherent update on write will be used.  Not all processors have
1312          * this bit and; some wire it to zero, others like Toshiba had the
1313          * silly idea of putting something else there ...
1314          */
1315         switch (current_cpu_type()) {
1316         case CPU_R4000PC:
1317         case CPU_R4000SC:
1318         case CPU_R4000MC:
1319         case CPU_R4400PC:
1320         case CPU_R4400SC:
1321         case CPU_R4400MC:
1322                 clear_c0_config(CONF_CU);
1323                 break;
1324         /*
1325          * We need to catch the early Alchemy SOCs with
1326          * the write-only co_config.od bit and set it back to one on:
1327          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1328          */
1329         case CPU_ALCHEMY:
1330                 au1x00_fixup_config_od();
1331                 break;
1332
1333         case PRID_IMP_PR4450:
1334                 nxp_pr4450_fixup_config();
1335                 break;
1336         }
1337 }
1338
1339 #if defined(CONFIG_DMA_NONCOHERENT)
1340
1341 static int __cpuinitdata coherentio;
1342
1343 static int __init setcoherentio(char *str)
1344 {
1345         coherentio = 1;
1346
1347         return 1;
1348 }
1349
1350 __setup("coherentio", setcoherentio);
1351 #endif
1352
1353 void __cpuinit r4k_cache_init(void)
1354 {
1355         extern void build_clear_page(void);
1356         extern void build_copy_page(void);
1357         extern char __weak except_vec2_generic;
1358         extern char __weak except_vec2_sb1;
1359         struct cpuinfo_mips *c = &current_cpu_data;
1360
1361         switch (c->cputype) {
1362         case CPU_SB1:
1363         case CPU_SB1A:
1364                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1365                 break;
1366
1367         default:
1368                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1369                 break;
1370         }
1371
1372         probe_pcache();
1373         setup_scache();
1374
1375         r4k_blast_dcache_page_setup();
1376         r4k_blast_dcache_page_indexed_setup();
1377         r4k_blast_dcache_setup();
1378         r4k_blast_icache_page_setup();
1379         r4k_blast_icache_page_indexed_setup();
1380         r4k_blast_icache_setup();
1381         r4k_blast_scache_page_setup();
1382         r4k_blast_scache_page_indexed_setup();
1383         r4k_blast_scache_setup();
1384
1385         /*
1386          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1387          * This code supports virtually indexed processors and will be
1388          * unnecessarily inefficient on physically indexed processors.
1389          */
1390         if (c->dcache.linesz)
1391                 shm_align_mask = max_t( unsigned long,
1392                                         c->dcache.sets * c->dcache.linesz - 1,
1393                                         PAGE_SIZE - 1);
1394         else
1395                 shm_align_mask = PAGE_SIZE-1;
1396
1397         __flush_cache_vmap      = r4k__flush_cache_vmap;
1398         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1399
1400         flush_cache_all         = cache_noop;
1401         __flush_cache_all       = r4k___flush_cache_all;
1402         flush_cache_mm          = r4k_flush_cache_mm;
1403         flush_cache_page        = r4k_flush_cache_page;
1404         flush_cache_range       = r4k_flush_cache_range;
1405
1406         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1407         flush_icache_all        = r4k_flush_icache_all;
1408         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1409         flush_data_cache_page   = r4k_flush_data_cache_page;
1410         flush_icache_range      = r4k_flush_icache_range;
1411         local_flush_icache_range        = local_r4k_flush_icache_range;
1412
1413 #if defined(CONFIG_DMA_NONCOHERENT)
1414         if (coherentio) {
1415                 _dma_cache_wback_inv    = (void *)cache_noop;
1416                 _dma_cache_wback        = (void *)cache_noop;
1417                 _dma_cache_inv          = (void *)cache_noop;
1418         } else {
1419                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1420                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1421                 _dma_cache_inv          = r4k_dma_cache_inv;
1422         }
1423 #endif
1424
1425         build_clear_page();
1426         build_copy_page();
1427 #if !defined(CONFIG_MIPS_CMP)
1428         local_r4k___flush_cache_all(NULL);
1429 #endif
1430         coherency_setup();
1431 }