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[linux-2.6.git] / arch / mips / math-emu / cp1emu.c
1 /*
2  * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3  *
4  * MIPS floating point support
5  * Copyright (C) 1994-2000 Algorithmics Ltd.
6  *
7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8  * Copyright (C) 2000  MIPS Technologies, Inc.
9  *
10  *  This program is free software; you can distribute it and/or modify it
11  *  under the terms of the GNU General Public License (Version 2) as
12  *  published by the Free Software Foundation.
13  *
14  *  This program is distributed in the hope it will be useful, but WITHOUT
15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17  *  for more details.
18  *
19  *  You should have received a copy of the GNU General Public License along
20  *  with this program; if not, write to the Free Software Foundation, Inc.,
21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22  *
23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
24  * required for #float(switch) or #float(trap), where it catches all
25  * COP1 instructions via the "CoProcessor Unusable" exception.
26  *
27  * More surprisingly it is also required for #float(ieee), to help out
28  * the hardware fpu at the boundaries of the IEEE-754 representation
29  * (denormalised values, infinities, underflow, etc).  It is made
30  * quite nasty because emulation of some non-COP1 instructions is
31  * required, e.g. in branch delay slots.
32  *
33  * Note if you know that you won't have an fpu, then you'll get much
34  * better performance by compiling with -msoft-float!
35  */
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39
40 #include <asm/inst.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
49
50 #include "ieee754.h"
51
52 /* Strap kernel emulator for full MIPS IV emulation */
53
54 #ifdef __mips
55 #undef __mips
56 #endif
57 #define __mips 4
58
59 /* Function which emulates a floating point instruction. */
60
61 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
62         mips_instruction);
63
64 #if __mips >= 4 && __mips != 32
65 static int fpux_emu(struct pt_regs *,
66         struct mips_fpu_struct *, mips_instruction);
67 #endif
68
69 /* Further private data for which no space exists in mips_fpu_struct */
70
71 #ifdef CONFIG_DEBUG_FS
72 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
73 #endif
74
75 /* Control registers */
76
77 #define FPCREG_RID      0       /* $0  = revision id */
78 #define FPCREG_CSR      31      /* $31 = csr */
79
80 /* Determine rounding mode from the RM bits of the FCSR */
81 #define modeindex(v) ((v) & FPU_CSR_RM)
82
83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
84 static const unsigned char ieee_rm[4] = {
85         [FPU_CSR_RN] = IEEE754_RN,
86         [FPU_CSR_RZ] = IEEE754_RZ,
87         [FPU_CSR_RU] = IEEE754_RU,
88         [FPU_CSR_RD] = IEEE754_RD,
89 };
90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
91 static const unsigned char mips_rm[4] = {
92         [IEEE754_RN] = FPU_CSR_RN,
93         [IEEE754_RZ] = FPU_CSR_RZ,
94         [IEEE754_RD] = FPU_CSR_RD,
95         [IEEE754_RU] = FPU_CSR_RU,
96 };
97
98 #if __mips >= 4
99 /* convert condition code register number to csr bit */
100 static const unsigned int fpucondbit[8] = {
101         FPU_CSR_COND0,
102         FPU_CSR_COND1,
103         FPU_CSR_COND2,
104         FPU_CSR_COND3,
105         FPU_CSR_COND4,
106         FPU_CSR_COND5,
107         FPU_CSR_COND6,
108         FPU_CSR_COND7
109 };
110 #endif
111
112
113 /*
114  * Redundant with logic already in kernel/branch.c,
115  * embedded in compute_return_epc.  At some point,
116  * a single subroutine should be used across both
117  * modules.
118  */
119 static int isBranchInstr(mips_instruction * i)
120 {
121         switch (MIPSInst_OPCODE(*i)) {
122         case spec_op:
123                 switch (MIPSInst_FUNC(*i)) {
124                 case jalr_op:
125                 case jr_op:
126                         return 1;
127                 }
128                 break;
129
130         case bcond_op:
131                 switch (MIPSInst_RT(*i)) {
132                 case bltz_op:
133                 case bgez_op:
134                 case bltzl_op:
135                 case bgezl_op:
136                 case bltzal_op:
137                 case bgezal_op:
138                 case bltzall_op:
139                 case bgezall_op:
140                         return 1;
141                 }
142                 break;
143
144         case j_op:
145         case jal_op:
146         case jalx_op:
147         case beq_op:
148         case bne_op:
149         case blez_op:
150         case bgtz_op:
151         case beql_op:
152         case bnel_op:
153         case blezl_op:
154         case bgtzl_op:
155                 return 1;
156
157         case cop0_op:
158         case cop1_op:
159         case cop2_op:
160         case cop1x_op:
161                 if (MIPSInst_RS(*i) == bc_op)
162                         return 1;
163                 break;
164         }
165
166         return 0;
167 }
168
169 /*
170  * In the Linux kernel, we support selection of FPR format on the
171  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
172  * is hardwired to zero, which would imply a 32-bit FPU even for
173  * 64-bit CPUs.  For 64-bit kernels with no FPU we use TIF_32BIT_REGS
174  * as a proxy for the FR bit so that a 64-bit FPU is emulated.  In any
175  * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
176  * even FPRs are used (Status.FR = 0).
177  */
178 static inline int cop1_64bit(struct pt_regs *xcp)
179 {
180         if (cpu_has_fpu)
181                 return xcp->cp0_status & ST0_FR;
182 #ifdef CONFIG_64BIT
183         return !test_thread_flag(TIF_32BIT_REGS);
184 #else
185         return 0;
186 #endif
187 }
188
189 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
190                         (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
191
192 #define SITOREG(si, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
193                         cop1_64bit(xcp) || !(x & 1) ? \
194                         ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
195                         ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
196
197 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
198 #define DITOREG(di, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
199
200 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
201 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
202 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
203 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
204
205 /*
206  * Emulate the single floating point instruction pointed at by EPC.
207  * Two instructions if the instruction is in a branch delay slot.
208  */
209
210 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
211 {
212         mips_instruction ir;
213         unsigned long emulpc, contpc;
214         unsigned int cond;
215
216         if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
217                 MIPS_FPU_EMU_INC_STATS(errors);
218                 return SIGBUS;
219         }
220
221         /* XXX NEC Vr54xx bug workaround */
222         if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
223                 xcp->cp0_cause &= ~CAUSEF_BD;
224
225         if (xcp->cp0_cause & CAUSEF_BD) {
226                 /*
227                  * The instruction to be emulated is in a branch delay slot
228                  * which means that we have to  emulate the branch instruction
229                  * BEFORE we do the cop1 instruction.
230                  *
231                  * This branch could be a COP1 branch, but in that case we
232                  * would have had a trap for that instruction, and would not
233                  * come through this route.
234                  *
235                  * Linux MIPS branch emulator operates on context, updating the
236                  * cp0_epc.
237                  */
238                 emulpc = xcp->cp0_epc + 4;      /* Snapshot emulation target */
239
240                 if (__compute_return_epc(xcp)) {
241 #ifdef CP1DBG
242                         printk("failed to emulate branch at %p\n",
243                                 (void *) (xcp->cp0_epc));
244 #endif
245                         return SIGILL;
246                 }
247                 if (get_user(ir, (mips_instruction __user *) emulpc)) {
248                         MIPS_FPU_EMU_INC_STATS(errors);
249                         return SIGBUS;
250                 }
251                 /* __compute_return_epc() will have updated cp0_epc */
252                 contpc = xcp->cp0_epc;
253                 /* In order not to confuse ptrace() et al, tweak context */
254                 xcp->cp0_epc = emulpc - 4;
255         } else {
256                 emulpc = xcp->cp0_epc;
257                 contpc = xcp->cp0_epc + 4;
258         }
259
260       emul:
261         MIPS_FPU_EMU_INC_STATS(emulated);
262         switch (MIPSInst_OPCODE(ir)) {
263         case ldc1_op:{
264                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
265                         MIPSInst_SIMM(ir));
266                 u64 val;
267
268                 MIPS_FPU_EMU_INC_STATS(loads);
269                 if (get_user(val, va)) {
270                         MIPS_FPU_EMU_INC_STATS(errors);
271                         return SIGBUS;
272                 }
273                 DITOREG(val, MIPSInst_RT(ir));
274                 break;
275         }
276
277         case sdc1_op:{
278                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
279                         MIPSInst_SIMM(ir));
280                 u64 val;
281
282                 MIPS_FPU_EMU_INC_STATS(stores);
283                 DIFROMREG(val, MIPSInst_RT(ir));
284                 if (put_user(val, va)) {
285                         MIPS_FPU_EMU_INC_STATS(errors);
286                         return SIGBUS;
287                 }
288                 break;
289         }
290
291         case lwc1_op:{
292                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
293                         MIPSInst_SIMM(ir));
294                 u32 val;
295
296                 MIPS_FPU_EMU_INC_STATS(loads);
297                 if (get_user(val, va)) {
298                         MIPS_FPU_EMU_INC_STATS(errors);
299                         return SIGBUS;
300                 }
301                 SITOREG(val, MIPSInst_RT(ir));
302                 break;
303         }
304
305         case swc1_op:{
306                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
307                         MIPSInst_SIMM(ir));
308                 u32 val;
309
310                 MIPS_FPU_EMU_INC_STATS(stores);
311                 SIFROMREG(val, MIPSInst_RT(ir));
312                 if (put_user(val, va)) {
313                         MIPS_FPU_EMU_INC_STATS(errors);
314                         return SIGBUS;
315                 }
316                 break;
317         }
318
319         case cop1_op:
320                 switch (MIPSInst_RS(ir)) {
321
322 #if defined(__mips64)
323                 case dmfc_op:
324                         /* copregister fs -> gpr[rt] */
325                         if (MIPSInst_RT(ir) != 0) {
326                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
327                                         MIPSInst_RD(ir));
328                         }
329                         break;
330
331                 case dmtc_op:
332                         /* copregister fs <- rt */
333                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
334                         break;
335 #endif
336
337                 case mfc_op:
338                         /* copregister rd -> gpr[rt] */
339                         if (MIPSInst_RT(ir) != 0) {
340                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
341                                         MIPSInst_RD(ir));
342                         }
343                         break;
344
345                 case mtc_op:
346                         /* copregister rd <- rt */
347                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
348                         break;
349
350                 case cfc_op:{
351                         /* cop control register rd -> gpr[rt] */
352                         u32 value;
353
354                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
355                                 value = ctx->fcr31;
356                                 value = (value & ~FPU_CSR_RM) |
357                                         mips_rm[modeindex(value)];
358 #ifdef CSRTRACE
359                                 printk("%p gpr[%d]<-csr=%08x\n",
360                                         (void *) (xcp->cp0_epc),
361                                         MIPSInst_RT(ir), value);
362 #endif
363                         }
364                         else if (MIPSInst_RD(ir) == FPCREG_RID)
365                                 value = 0;
366                         else
367                                 value = 0;
368                         if (MIPSInst_RT(ir))
369                                 xcp->regs[MIPSInst_RT(ir)] = value;
370                         break;
371                 }
372
373                 case ctc_op:{
374                         /* copregister rd <- rt */
375                         u32 value;
376
377                         if (MIPSInst_RT(ir) == 0)
378                                 value = 0;
379                         else
380                                 value = xcp->regs[MIPSInst_RT(ir)];
381
382                         /* we only have one writable control reg
383                          */
384                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
385 #ifdef CSRTRACE
386                                 printk("%p gpr[%d]->csr=%08x\n",
387                                         (void *) (xcp->cp0_epc),
388                                         MIPSInst_RT(ir), value);
389 #endif
390
391                                 /*
392                                  * Don't write reserved bits,
393                                  * and convert to ieee library modes
394                                  */
395                                 ctx->fcr31 = (value &
396                                                 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
397                                                 ieee_rm[modeindex(value)];
398                         }
399                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
400                                 return SIGFPE;
401                         }
402                         break;
403                 }
404
405                 case bc_op:{
406                         int likely = 0;
407
408                         if (xcp->cp0_cause & CAUSEF_BD)
409                                 return SIGILL;
410
411 #if __mips >= 4
412                         cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
413 #else
414                         cond = ctx->fcr31 & FPU_CSR_COND;
415 #endif
416                         switch (MIPSInst_RT(ir) & 3) {
417                         case bcfl_op:
418                                 likely = 1;
419                         case bcf_op:
420                                 cond = !cond;
421                                 break;
422                         case bctl_op:
423                                 likely = 1;
424                         case bct_op:
425                                 break;
426                         default:
427                                 /* thats an illegal instruction */
428                                 return SIGILL;
429                         }
430
431                         xcp->cp0_cause |= CAUSEF_BD;
432                         if (cond) {
433                                 /* branch taken: emulate dslot
434                                  * instruction
435                                  */
436                                 xcp->cp0_epc += 4;
437                                 contpc = (xcp->cp0_epc +
438                                         (MIPSInst_SIMM(ir) << 2));
439
440                                 if (get_user(ir,
441                                     (mips_instruction __user *) xcp->cp0_epc)) {
442                                         MIPS_FPU_EMU_INC_STATS(errors);
443                                         return SIGBUS;
444                                 }
445
446                                 switch (MIPSInst_OPCODE(ir)) {
447                                 case lwc1_op:
448                                 case swc1_op:
449 #if (__mips >= 2 || defined(__mips64))
450                                 case ldc1_op:
451                                 case sdc1_op:
452 #endif
453                                 case cop1_op:
454 #if __mips >= 4 && __mips != 32
455                                 case cop1x_op:
456 #endif
457                                         /* its one of ours */
458                                         goto emul;
459 #if __mips >= 4
460                                 case spec_op:
461                                         if (MIPSInst_FUNC(ir) == movc_op)
462                                                 goto emul;
463                                         break;
464 #endif
465                                 }
466
467                                 /*
468                                  * Single step the non-cp1
469                                  * instruction in the dslot
470                                  */
471                                 return mips_dsemul(xcp, ir, contpc);
472                         }
473                         else {
474                                 /* branch not taken */
475                                 if (likely) {
476                                         /*
477                                          * branch likely nullifies
478                                          * dslot if not taken
479                                          */
480                                         xcp->cp0_epc += 4;
481                                         contpc += 4;
482                                         /*
483                                          * else continue & execute
484                                          * dslot as normal insn
485                                          */
486                                 }
487                         }
488                         break;
489                 }
490
491                 default:
492                         if (!(MIPSInst_RS(ir) & 0x10))
493                                 return SIGILL;
494                         {
495                                 int sig;
496
497                                 /* a real fpu computation instruction */
498                                 if ((sig = fpu_emu(xcp, ctx, ir)))
499                                         return sig;
500                         }
501                 }
502                 break;
503
504 #if __mips >= 4 && __mips != 32
505         case cop1x_op:{
506                 int sig;
507
508                 if ((sig = fpux_emu(xcp, ctx, ir)))
509                         return sig;
510                 break;
511         }
512 #endif
513
514 #if __mips >= 4
515         case spec_op:
516                 if (MIPSInst_FUNC(ir) != movc_op)
517                         return SIGILL;
518                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
519                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
520                         xcp->regs[MIPSInst_RD(ir)] =
521                                 xcp->regs[MIPSInst_RS(ir)];
522                 break;
523 #endif
524
525         default:
526                 return SIGILL;
527         }
528
529         /* we did it !! */
530         xcp->cp0_epc = contpc;
531         xcp->cp0_cause &= ~CAUSEF_BD;
532
533         return 0;
534 }
535
536 /*
537  * Conversion table from MIPS compare ops 48-63
538  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
539  */
540 static const unsigned char cmptab[8] = {
541         0,                      /* cmp_0 (sig) cmp_sf */
542         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
543         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
544         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
545         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
546         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
547         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
548         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
549 };
550
551
552 #if __mips >= 4 && __mips != 32
553
554 /*
555  * Additional MIPS4 instructions
556  */
557
558 #define DEF3OP(name, p, f1, f2, f3) \
559 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
560     ieee754##p t) \
561 { \
562         struct _ieee754_csr ieee754_csr_save; \
563         s = f1(s, t); \
564         ieee754_csr_save = ieee754_csr; \
565         s = f2(s, r); \
566         ieee754_csr_save.cx |= ieee754_csr.cx; \
567         ieee754_csr_save.sx |= ieee754_csr.sx; \
568         s = f3(s); \
569         ieee754_csr.cx |= ieee754_csr_save.cx; \
570         ieee754_csr.sx |= ieee754_csr_save.sx; \
571         return s; \
572 }
573
574 static ieee754dp fpemu_dp_recip(ieee754dp d)
575 {
576         return ieee754dp_div(ieee754dp_one(0), d);
577 }
578
579 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
580 {
581         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
582 }
583
584 static ieee754sp fpemu_sp_recip(ieee754sp s)
585 {
586         return ieee754sp_div(ieee754sp_one(0), s);
587 }
588
589 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
590 {
591         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
592 }
593
594 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
595 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
596 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
597 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
598 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
599 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
600 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
601 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
602
603 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
604         mips_instruction ir)
605 {
606         unsigned rcsr = 0;      /* resulting csr */
607
608         MIPS_FPU_EMU_INC_STATS(cp1xops);
609
610         switch (MIPSInst_FMA_FFMT(ir)) {
611         case s_fmt:{            /* 0 */
612
613                 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
614                 ieee754sp fd, fr, fs, ft;
615                 u32 __user *va;
616                 u32 val;
617
618                 switch (MIPSInst_FUNC(ir)) {
619                 case lwxc1_op:
620                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
621                                 xcp->regs[MIPSInst_FT(ir)]);
622
623                         MIPS_FPU_EMU_INC_STATS(loads);
624                         if (get_user(val, va)) {
625                                 MIPS_FPU_EMU_INC_STATS(errors);
626                                 return SIGBUS;
627                         }
628                         SITOREG(val, MIPSInst_FD(ir));
629                         break;
630
631                 case swxc1_op:
632                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
633                                 xcp->regs[MIPSInst_FT(ir)]);
634
635                         MIPS_FPU_EMU_INC_STATS(stores);
636
637                         SIFROMREG(val, MIPSInst_FS(ir));
638                         if (put_user(val, va)) {
639                                 MIPS_FPU_EMU_INC_STATS(errors);
640                                 return SIGBUS;
641                         }
642                         break;
643
644                 case madd_s_op:
645                         handler = fpemu_sp_madd;
646                         goto scoptop;
647                 case msub_s_op:
648                         handler = fpemu_sp_msub;
649                         goto scoptop;
650                 case nmadd_s_op:
651                         handler = fpemu_sp_nmadd;
652                         goto scoptop;
653                 case nmsub_s_op:
654                         handler = fpemu_sp_nmsub;
655                         goto scoptop;
656
657                       scoptop:
658                         SPFROMREG(fr, MIPSInst_FR(ir));
659                         SPFROMREG(fs, MIPSInst_FS(ir));
660                         SPFROMREG(ft, MIPSInst_FT(ir));
661                         fd = (*handler) (fr, fs, ft);
662                         SPTOREG(fd, MIPSInst_FD(ir));
663
664                       copcsr:
665                         if (ieee754_cxtest(IEEE754_INEXACT))
666                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
667                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
668                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
669                         if (ieee754_cxtest(IEEE754_OVERFLOW))
670                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
671                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
672                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
673
674                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
675                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
676                                 /*printk ("SIGFPE: fpu csr = %08x\n",
677                                    ctx->fcr31); */
678                                 return SIGFPE;
679                         }
680
681                         break;
682
683                 default:
684                         return SIGILL;
685                 }
686                 break;
687         }
688
689         case d_fmt:{            /* 1 */
690                 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
691                 ieee754dp fd, fr, fs, ft;
692                 u64 __user *va;
693                 u64 val;
694
695                 switch (MIPSInst_FUNC(ir)) {
696                 case ldxc1_op:
697                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
698                                 xcp->regs[MIPSInst_FT(ir)]);
699
700                         MIPS_FPU_EMU_INC_STATS(loads);
701                         if (get_user(val, va)) {
702                                 MIPS_FPU_EMU_INC_STATS(errors);
703                                 return SIGBUS;
704                         }
705                         DITOREG(val, MIPSInst_FD(ir));
706                         break;
707
708                 case sdxc1_op:
709                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
710                                 xcp->regs[MIPSInst_FT(ir)]);
711
712                         MIPS_FPU_EMU_INC_STATS(stores);
713                         DIFROMREG(val, MIPSInst_FS(ir));
714                         if (put_user(val, va)) {
715                                 MIPS_FPU_EMU_INC_STATS(errors);
716                                 return SIGBUS;
717                         }
718                         break;
719
720                 case madd_d_op:
721                         handler = fpemu_dp_madd;
722                         goto dcoptop;
723                 case msub_d_op:
724                         handler = fpemu_dp_msub;
725                         goto dcoptop;
726                 case nmadd_d_op:
727                         handler = fpemu_dp_nmadd;
728                         goto dcoptop;
729                 case nmsub_d_op:
730                         handler = fpemu_dp_nmsub;
731                         goto dcoptop;
732
733                       dcoptop:
734                         DPFROMREG(fr, MIPSInst_FR(ir));
735                         DPFROMREG(fs, MIPSInst_FS(ir));
736                         DPFROMREG(ft, MIPSInst_FT(ir));
737                         fd = (*handler) (fr, fs, ft);
738                         DPTOREG(fd, MIPSInst_FD(ir));
739                         goto copcsr;
740
741                 default:
742                         return SIGILL;
743                 }
744                 break;
745         }
746
747         case 0x7:               /* 7 */
748                 if (MIPSInst_FUNC(ir) != pfetch_op) {
749                         return SIGILL;
750                 }
751                 /* ignore prefx operation */
752                 break;
753
754         default:
755                 return SIGILL;
756         }
757
758         return 0;
759 }
760 #endif
761
762
763
764 /*
765  * Emulate a single COP1 arithmetic instruction.
766  */
767 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
768         mips_instruction ir)
769 {
770         int rfmt;               /* resulting format */
771         unsigned rcsr = 0;      /* resulting csr */
772         unsigned cond;
773         union {
774                 ieee754dp d;
775                 ieee754sp s;
776                 int w;
777 #ifdef __mips64
778                 s64 l;
779 #endif
780         } rv;                   /* resulting value */
781
782         MIPS_FPU_EMU_INC_STATS(cp1ops);
783         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
784         case s_fmt:{            /* 0 */
785                 union {
786                         ieee754sp(*b) (ieee754sp, ieee754sp);
787                         ieee754sp(*u) (ieee754sp);
788                 } handler;
789
790                 switch (MIPSInst_FUNC(ir)) {
791                         /* binary ops */
792                 case fadd_op:
793                         handler.b = ieee754sp_add;
794                         goto scopbop;
795                 case fsub_op:
796                         handler.b = ieee754sp_sub;
797                         goto scopbop;
798                 case fmul_op:
799                         handler.b = ieee754sp_mul;
800                         goto scopbop;
801                 case fdiv_op:
802                         handler.b = ieee754sp_div;
803                         goto scopbop;
804
805                         /* unary  ops */
806 #if __mips >= 2 || defined(__mips64)
807                 case fsqrt_op:
808                         handler.u = ieee754sp_sqrt;
809                         goto scopuop;
810 #endif
811 #if __mips >= 4 && __mips != 32
812                 case frsqrt_op:
813                         handler.u = fpemu_sp_rsqrt;
814                         goto scopuop;
815                 case frecip_op:
816                         handler.u = fpemu_sp_recip;
817                         goto scopuop;
818 #endif
819 #if __mips >= 4
820                 case fmovc_op:
821                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
822                         if (((ctx->fcr31 & cond) != 0) !=
823                                 ((MIPSInst_FT(ir) & 1) != 0))
824                                 return 0;
825                         SPFROMREG(rv.s, MIPSInst_FS(ir));
826                         break;
827                 case fmovz_op:
828                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
829                                 return 0;
830                         SPFROMREG(rv.s, MIPSInst_FS(ir));
831                         break;
832                 case fmovn_op:
833                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
834                                 return 0;
835                         SPFROMREG(rv.s, MIPSInst_FS(ir));
836                         break;
837 #endif
838                 case fabs_op:
839                         handler.u = ieee754sp_abs;
840                         goto scopuop;
841                 case fneg_op:
842                         handler.u = ieee754sp_neg;
843                         goto scopuop;
844                 case fmov_op:
845                         /* an easy one */
846                         SPFROMREG(rv.s, MIPSInst_FS(ir));
847                         goto copcsr;
848
849                         /* binary op on handler */
850                       scopbop:
851                         {
852                                 ieee754sp fs, ft;
853
854                                 SPFROMREG(fs, MIPSInst_FS(ir));
855                                 SPFROMREG(ft, MIPSInst_FT(ir));
856
857                                 rv.s = (*handler.b) (fs, ft);
858                                 goto copcsr;
859                         }
860                       scopuop:
861                         {
862                                 ieee754sp fs;
863
864                                 SPFROMREG(fs, MIPSInst_FS(ir));
865                                 rv.s = (*handler.u) (fs);
866                                 goto copcsr;
867                         }
868                       copcsr:
869                         if (ieee754_cxtest(IEEE754_INEXACT))
870                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
871                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
872                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
873                         if (ieee754_cxtest(IEEE754_OVERFLOW))
874                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
875                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
876                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
877                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
878                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
879                         break;
880
881                         /* unary conv ops */
882                 case fcvts_op:
883                         return SIGILL;  /* not defined */
884                 case fcvtd_op:{
885                         ieee754sp fs;
886
887                         SPFROMREG(fs, MIPSInst_FS(ir));
888                         rv.d = ieee754dp_fsp(fs);
889                         rfmt = d_fmt;
890                         goto copcsr;
891                 }
892                 case fcvtw_op:{
893                         ieee754sp fs;
894
895                         SPFROMREG(fs, MIPSInst_FS(ir));
896                         rv.w = ieee754sp_tint(fs);
897                         rfmt = w_fmt;
898                         goto copcsr;
899                 }
900
901 #if __mips >= 2 || defined(__mips64)
902                 case fround_op:
903                 case ftrunc_op:
904                 case fceil_op:
905                 case ffloor_op:{
906                         unsigned int oldrm = ieee754_csr.rm;
907                         ieee754sp fs;
908
909                         SPFROMREG(fs, MIPSInst_FS(ir));
910                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
911                         rv.w = ieee754sp_tint(fs);
912                         ieee754_csr.rm = oldrm;
913                         rfmt = w_fmt;
914                         goto copcsr;
915                 }
916 #endif /* __mips >= 2 */
917
918 #if defined(__mips64)
919                 case fcvtl_op:{
920                         ieee754sp fs;
921
922                         SPFROMREG(fs, MIPSInst_FS(ir));
923                         rv.l = ieee754sp_tlong(fs);
924                         rfmt = l_fmt;
925                         goto copcsr;
926                 }
927
928                 case froundl_op:
929                 case ftruncl_op:
930                 case fceill_op:
931                 case ffloorl_op:{
932                         unsigned int oldrm = ieee754_csr.rm;
933                         ieee754sp fs;
934
935                         SPFROMREG(fs, MIPSInst_FS(ir));
936                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
937                         rv.l = ieee754sp_tlong(fs);
938                         ieee754_csr.rm = oldrm;
939                         rfmt = l_fmt;
940                         goto copcsr;
941                 }
942 #endif /* defined(__mips64) */
943
944                 default:
945                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
946                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
947                                 ieee754sp fs, ft;
948
949                                 SPFROMREG(fs, MIPSInst_FS(ir));
950                                 SPFROMREG(ft, MIPSInst_FT(ir));
951                                 rv.w = ieee754sp_cmp(fs, ft,
952                                         cmptab[cmpop & 0x7], cmpop & 0x8);
953                                 rfmt = -1;
954                                 if ((cmpop & 0x8) && ieee754_cxtest
955                                         (IEEE754_INVALID_OPERATION))
956                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
957                                 else
958                                         goto copcsr;
959
960                         }
961                         else {
962                                 return SIGILL;
963                         }
964                         break;
965                 }
966                 break;
967         }
968
969         case d_fmt:{
970                 union {
971                         ieee754dp(*b) (ieee754dp, ieee754dp);
972                         ieee754dp(*u) (ieee754dp);
973                 } handler;
974
975                 switch (MIPSInst_FUNC(ir)) {
976                         /* binary ops */
977                 case fadd_op:
978                         handler.b = ieee754dp_add;
979                         goto dcopbop;
980                 case fsub_op:
981                         handler.b = ieee754dp_sub;
982                         goto dcopbop;
983                 case fmul_op:
984                         handler.b = ieee754dp_mul;
985                         goto dcopbop;
986                 case fdiv_op:
987                         handler.b = ieee754dp_div;
988                         goto dcopbop;
989
990                         /* unary  ops */
991 #if __mips >= 2 || defined(__mips64)
992                 case fsqrt_op:
993                         handler.u = ieee754dp_sqrt;
994                         goto dcopuop;
995 #endif
996 #if __mips >= 4 && __mips != 32
997                 case frsqrt_op:
998                         handler.u = fpemu_dp_rsqrt;
999                         goto dcopuop;
1000                 case frecip_op:
1001                         handler.u = fpemu_dp_recip;
1002                         goto dcopuop;
1003 #endif
1004 #if __mips >= 4
1005                 case fmovc_op:
1006                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1007                         if (((ctx->fcr31 & cond) != 0) !=
1008                                 ((MIPSInst_FT(ir) & 1) != 0))
1009                                 return 0;
1010                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1011                         break;
1012                 case fmovz_op:
1013                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1014                                 return 0;
1015                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1016                         break;
1017                 case fmovn_op:
1018                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1019                                 return 0;
1020                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1021                         break;
1022 #endif
1023                 case fabs_op:
1024                         handler.u = ieee754dp_abs;
1025                         goto dcopuop;
1026
1027                 case fneg_op:
1028                         handler.u = ieee754dp_neg;
1029                         goto dcopuop;
1030
1031                 case fmov_op:
1032                         /* an easy one */
1033                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1034                         goto copcsr;
1035
1036                         /* binary op on handler */
1037                       dcopbop:{
1038                                 ieee754dp fs, ft;
1039
1040                                 DPFROMREG(fs, MIPSInst_FS(ir));
1041                                 DPFROMREG(ft, MIPSInst_FT(ir));
1042
1043                                 rv.d = (*handler.b) (fs, ft);
1044                                 goto copcsr;
1045                         }
1046                       dcopuop:{
1047                                 ieee754dp fs;
1048
1049                                 DPFROMREG(fs, MIPSInst_FS(ir));
1050                                 rv.d = (*handler.u) (fs);
1051                                 goto copcsr;
1052                         }
1053
1054                         /* unary conv ops */
1055                 case fcvts_op:{
1056                         ieee754dp fs;
1057
1058                         DPFROMREG(fs, MIPSInst_FS(ir));
1059                         rv.s = ieee754sp_fdp(fs);
1060                         rfmt = s_fmt;
1061                         goto copcsr;
1062                 }
1063                 case fcvtd_op:
1064                         return SIGILL;  /* not defined */
1065
1066                 case fcvtw_op:{
1067                         ieee754dp fs;
1068
1069                         DPFROMREG(fs, MIPSInst_FS(ir));
1070                         rv.w = ieee754dp_tint(fs);      /* wrong */
1071                         rfmt = w_fmt;
1072                         goto copcsr;
1073                 }
1074
1075 #if __mips >= 2 || defined(__mips64)
1076                 case fround_op:
1077                 case ftrunc_op:
1078                 case fceil_op:
1079                 case ffloor_op:{
1080                         unsigned int oldrm = ieee754_csr.rm;
1081                         ieee754dp fs;
1082
1083                         DPFROMREG(fs, MIPSInst_FS(ir));
1084                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1085                         rv.w = ieee754dp_tint(fs);
1086                         ieee754_csr.rm = oldrm;
1087                         rfmt = w_fmt;
1088                         goto copcsr;
1089                 }
1090 #endif
1091
1092 #if defined(__mips64)
1093                 case fcvtl_op:{
1094                         ieee754dp fs;
1095
1096                         DPFROMREG(fs, MIPSInst_FS(ir));
1097                         rv.l = ieee754dp_tlong(fs);
1098                         rfmt = l_fmt;
1099                         goto copcsr;
1100                 }
1101
1102                 case froundl_op:
1103                 case ftruncl_op:
1104                 case fceill_op:
1105                 case ffloorl_op:{
1106                         unsigned int oldrm = ieee754_csr.rm;
1107                         ieee754dp fs;
1108
1109                         DPFROMREG(fs, MIPSInst_FS(ir));
1110                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1111                         rv.l = ieee754dp_tlong(fs);
1112                         ieee754_csr.rm = oldrm;
1113                         rfmt = l_fmt;
1114                         goto copcsr;
1115                 }
1116 #endif /* __mips >= 3 */
1117
1118                 default:
1119                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1120                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1121                                 ieee754dp fs, ft;
1122
1123                                 DPFROMREG(fs, MIPSInst_FS(ir));
1124                                 DPFROMREG(ft, MIPSInst_FT(ir));
1125                                 rv.w = ieee754dp_cmp(fs, ft,
1126                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1127                                 rfmt = -1;
1128                                 if ((cmpop & 0x8)
1129                                         &&
1130                                         ieee754_cxtest
1131                                         (IEEE754_INVALID_OPERATION))
1132                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1133                                 else
1134                                         goto copcsr;
1135
1136                         }
1137                         else {
1138                                 return SIGILL;
1139                         }
1140                         break;
1141                 }
1142                 break;
1143         }
1144
1145         case w_fmt:{
1146                 ieee754sp fs;
1147
1148                 switch (MIPSInst_FUNC(ir)) {
1149                 case fcvts_op:
1150                         /* convert word to single precision real */
1151                         SPFROMREG(fs, MIPSInst_FS(ir));
1152                         rv.s = ieee754sp_fint(fs.bits);
1153                         rfmt = s_fmt;
1154                         goto copcsr;
1155                 case fcvtd_op:
1156                         /* convert word to double precision real */
1157                         SPFROMREG(fs, MIPSInst_FS(ir));
1158                         rv.d = ieee754dp_fint(fs.bits);
1159                         rfmt = d_fmt;
1160                         goto copcsr;
1161                 default:
1162                         return SIGILL;
1163                 }
1164                 break;
1165         }
1166
1167 #if defined(__mips64)
1168         case l_fmt:{
1169                 switch (MIPSInst_FUNC(ir)) {
1170                 case fcvts_op:
1171                         /* convert long to single precision real */
1172                         rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1173                         rfmt = s_fmt;
1174                         goto copcsr;
1175                 case fcvtd_op:
1176                         /* convert long to double precision real */
1177                         rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1178                         rfmt = d_fmt;
1179                         goto copcsr;
1180                 default:
1181                         return SIGILL;
1182                 }
1183                 break;
1184         }
1185 #endif
1186
1187         default:
1188                 return SIGILL;
1189         }
1190
1191         /*
1192          * Update the fpu CSR register for this operation.
1193          * If an exception is required, generate a tidy SIGFPE exception,
1194          * without updating the result register.
1195          * Note: cause exception bits do not accumulate, they are rewritten
1196          * for each op; only the flag/sticky bits accumulate.
1197          */
1198         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1199         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1200                 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1201                 return SIGFPE;
1202         }
1203
1204         /*
1205          * Now we can safely write the result back to the register file.
1206          */
1207         switch (rfmt) {
1208         case -1:{
1209 #if __mips >= 4
1210                 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1211 #else
1212                 cond = FPU_CSR_COND;
1213 #endif
1214                 if (rv.w)
1215                         ctx->fcr31 |= cond;
1216                 else
1217                         ctx->fcr31 &= ~cond;
1218                 break;
1219         }
1220         case d_fmt:
1221                 DPTOREG(rv.d, MIPSInst_FD(ir));
1222                 break;
1223         case s_fmt:
1224                 SPTOREG(rv.s, MIPSInst_FD(ir));
1225                 break;
1226         case w_fmt:
1227                 SITOREG(rv.w, MIPSInst_FD(ir));
1228                 break;
1229 #if defined(__mips64)
1230         case l_fmt:
1231                 DITOREG(rv.l, MIPSInst_FD(ir));
1232                 break;
1233 #endif
1234         default:
1235                 return SIGILL;
1236         }
1237
1238         return 0;
1239 }
1240
1241 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1242         int has_fpu)
1243 {
1244         unsigned long oldepc, prevepc;
1245         mips_instruction insn;
1246         int sig = 0;
1247
1248         oldepc = xcp->cp0_epc;
1249         do {
1250                 prevepc = xcp->cp0_epc;
1251
1252                 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1253                         MIPS_FPU_EMU_INC_STATS(errors);
1254                         return SIGBUS;
1255                 }
1256                 if (insn == 0)
1257                         xcp->cp0_epc += 4;      /* skip nops */
1258                 else {
1259                         /*
1260                          * The 'ieee754_csr' is an alias of
1261                          * ctx->fcr31.  No need to copy ctx->fcr31 to
1262                          * ieee754_csr.  But ieee754_csr.rm is ieee
1263                          * library modes. (not mips rounding mode)
1264                          */
1265                         /* convert to ieee library modes */
1266                         ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1267                         sig = cop1Emulate(xcp, ctx);
1268                         /* revert to mips rounding mode */
1269                         ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1270                 }
1271
1272                 if (has_fpu)
1273                         break;
1274                 if (sig)
1275                         break;
1276
1277                 cond_resched();
1278         } while (xcp->cp0_epc > prevepc);
1279
1280         /* SIGILL indicates a non-fpu instruction */
1281         if (sig == SIGILL && xcp->cp0_epc != oldepc)
1282                 /* but if epc has advanced, then ignore it */
1283                 sig = 0;
1284
1285         return sig;
1286 }
1287
1288 #ifdef CONFIG_DEBUG_FS
1289
1290 static int fpuemu_stat_get(void *data, u64 *val)
1291 {
1292         int cpu;
1293         unsigned long sum = 0;
1294         for_each_online_cpu(cpu) {
1295                 struct mips_fpu_emulator_stats *ps;
1296                 local_t *pv;
1297                 ps = &per_cpu(fpuemustats, cpu);
1298                 pv = (void *)ps + (unsigned long)data;
1299                 sum += local_read(pv);
1300         }
1301         *val = sum;
1302         return 0;
1303 }
1304 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1305
1306 extern struct dentry *mips_debugfs_dir;
1307 static int __init debugfs_fpuemu(void)
1308 {
1309         struct dentry *d, *dir;
1310
1311         if (!mips_debugfs_dir)
1312                 return -ENODEV;
1313         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1314         if (!dir)
1315                 return -ENOMEM;
1316
1317 #define FPU_STAT_CREATE(M)                                              \
1318         do {                                                            \
1319                 d = debugfs_create_file(#M , S_IRUGO, dir,              \
1320                         (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1321                         &fops_fpuemu_stat);                             \
1322                 if (!d)                                                 \
1323                         return -ENOMEM;                                 \
1324         } while (0)
1325
1326         FPU_STAT_CREATE(emulated);
1327         FPU_STAT_CREATE(loads);
1328         FPU_STAT_CREATE(stores);
1329         FPU_STAT_CREATE(cp1ops);
1330         FPU_STAT_CREATE(cp1xops);
1331         FPU_STAT_CREATE(errors);
1332
1333         return 0;
1334 }
1335 __initcall(debugfs_fpuemu);
1336 #endif