Base Au1200 2.6 support.
[linux-2.6.git] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 2003  Maciej W. Rozycki
6  * Copyright (C) 1994 - 2003 Ralf Baechle
7  * Copyright (C) 2001 MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
19
20 #include <asm/bugs.h>
21 #include <asm/cpu.h>
22 #include <asm/fpu.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
25
26 /*
27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28  * the implementation of the "wait" feature differs between CPU families. This
29  * points to the function that implements CPU specific wait.
30  * The wait instruction stops the pipeline and reduces the power consumption of
31  * the CPU very much.
32  */
33 void (*cpu_wait)(void) = NULL;
34
35 static void r3081_wait(void)
36 {
37         unsigned long cfg = read_c0_conf();
38         write_c0_conf(cfg | R30XX_CONF_HALT);
39 }
40
41 static void r39xx_wait(void)
42 {
43         unsigned long cfg = read_c0_conf();
44         write_c0_conf(cfg | TX39_CONF_HALT);
45 }
46
47 static void r4k_wait(void)
48 {
49         __asm__(".set\tmips3\n\t"
50                 "wait\n\t"
51                 ".set\tmips0");
52 }
53
54 /*
55  * The Au1xxx wait is available only if we run CONFIG_PM and
56  * the timer setup found we had a 32KHz counter available.
57  * There are still problems with functions that may call au1k_wait
58  * directly, but that will be discovered pretty quickly.
59  */
60 extern void (*au1k_wait_ptr)(void);
61
62 void au1k_wait(void)
63 {
64 #ifdef CONFIG_PM
65         /* using the wait instruction makes CP0 counter unusable */
66         __asm__(".set\tmips3\n\t"
67                 "wait\n\t"
68                 "nop\n\t"
69                 "nop\n\t"
70                 "nop\n\t"
71                 "nop\n\t"
72                 ".set\tmips0");
73 #else
74         __asm__("nop\n\t"
75                 "nop");
76 #endif
77 }
78
79 static inline void check_wait(void)
80 {
81         struct cpuinfo_mips *c = &current_cpu_data;
82
83         printk("Checking for 'wait' instruction... ");
84         switch (c->cputype) {
85         case CPU_R3081:
86         case CPU_R3081E:
87                 cpu_wait = r3081_wait;
88                 printk(" available.\n");
89                 break;
90         case CPU_TX3927:
91                 cpu_wait = r39xx_wait;
92                 printk(" available.\n");
93                 break;
94         case CPU_R4200:
95 /*      case CPU_R4300: */
96         case CPU_R4600:
97         case CPU_R4640:
98         case CPU_R4650:
99         case CPU_R4700:
100         case CPU_R5000:
101         case CPU_NEVADA:
102         case CPU_RM7000:
103         case CPU_RM9000:
104         case CPU_TX49XX:
105         case CPU_4KC:
106         case CPU_4KEC:
107         case CPU_4KSC:
108         case CPU_5KC:
109 /*      case CPU_20KC:*/
110         case CPU_24K:
111         case CPU_25KF:
112                 cpu_wait = r4k_wait;
113                 printk(" available.\n");
114                 break;
115 #ifdef CONFIG_PM
116         case CPU_AU1000:
117         case CPU_AU1100:
118         case CPU_AU1500:
119         case CPU_AU1550:
120         case CPU_AU1200:
121                 if (au1k_wait_ptr != NULL) {
122                         cpu_wait = au1k_wait_ptr;
123                         printk(" available.\n");
124                 }
125                 else {
126                         printk(" unavailable.\n");
127                 }
128                 break;
129 #endif
130         default:
131                 printk(" unavailable.\n");
132                 break;
133         }
134 }
135
136 void __init check_bugs32(void)
137 {
138         check_wait();
139 }
140
141 /*
142  * Probe whether cpu has config register by trying to play with
143  * alternate cache bit and see whether it matters.
144  * It's used by cpu_probe to distinguish between R3000A and R3081.
145  */
146 static inline int cpu_has_confreg(void)
147 {
148 #ifdef CONFIG_CPU_R3000
149         extern unsigned long r3k_cache_size(unsigned long);
150         unsigned long size1, size2;
151         unsigned long cfg = read_c0_conf();
152
153         size1 = r3k_cache_size(ST0_ISC);
154         write_c0_conf(cfg ^ R30XX_CONF_AC);
155         size2 = r3k_cache_size(ST0_ISC);
156         write_c0_conf(cfg);
157         return size1 != size2;
158 #else
159         return 0;
160 #endif
161 }
162
163 /*
164  * Get the FPU Implementation/Revision.
165  */
166 static inline unsigned long cpu_get_fpu_id(void)
167 {
168         unsigned long tmp, fpu_id;
169
170         tmp = read_c0_status();
171         __enable_fpu();
172         fpu_id = read_32bit_cp1_register(CP1_REVISION);
173         write_c0_status(tmp);
174         return fpu_id;
175 }
176
177 /*
178  * Check the CPU has an FPU the official way.
179  */
180 static inline int __cpu_has_fpu(void)
181 {
182         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
183 }
184
185 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
186                 | MIPS_CPU_COUNTER)
187
188 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
189 {
190         switch (c->processor_id & 0xff00) {
191         case PRID_IMP_R2000:
192                 c->cputype = CPU_R2000;
193                 c->isa_level = MIPS_CPU_ISA_I;
194                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
195                 if (__cpu_has_fpu())
196                         c->options |= MIPS_CPU_FPU;
197                 c->tlbsize = 64;
198                 break;
199         case PRID_IMP_R3000:
200                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
201                         if (cpu_has_confreg())
202                                 c->cputype = CPU_R3081E;
203                         else
204                                 c->cputype = CPU_R3000A;
205                 else
206                         c->cputype = CPU_R3000;
207                 c->isa_level = MIPS_CPU_ISA_I;
208                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
209                 if (__cpu_has_fpu())
210                         c->options |= MIPS_CPU_FPU;
211                 c->tlbsize = 64;
212                 break;
213         case PRID_IMP_R4000:
214                 if (read_c0_config() & CONF_SC) {
215                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
216                                 c->cputype = CPU_R4400PC;
217                         else
218                                 c->cputype = CPU_R4000PC;
219                 } else {
220                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
221                                 c->cputype = CPU_R4400SC;
222                         else
223                                 c->cputype = CPU_R4000SC;
224                 }
225
226                 c->isa_level = MIPS_CPU_ISA_III;
227                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
228                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
229                              MIPS_CPU_LLSC;
230                 c->tlbsize = 48;
231                 break;
232         case PRID_IMP_VR41XX:
233                 switch (c->processor_id & 0xf0) {
234                 case PRID_REV_VR4111:
235                         c->cputype = CPU_VR4111;
236                         break;
237                 case PRID_REV_VR4121:
238                         c->cputype = CPU_VR4121;
239                         break;
240                 case PRID_REV_VR4122:
241                         if ((c->processor_id & 0xf) < 0x3)
242                                 c->cputype = CPU_VR4122;
243                         else
244                                 c->cputype = CPU_VR4181A;
245                         break;
246                 case PRID_REV_VR4130:
247                         if ((c->processor_id & 0xf) < 0x4)
248                                 c->cputype = CPU_VR4131;
249                         else
250                                 c->cputype = CPU_VR4133;
251                         break;
252                 default:
253                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
254                         c->cputype = CPU_VR41XX;
255                         break;
256                 }
257                 c->isa_level = MIPS_CPU_ISA_III;
258                 c->options = R4K_OPTS;
259                 c->tlbsize = 32;
260                 break;
261         case PRID_IMP_R4300:
262                 c->cputype = CPU_R4300;
263                 c->isa_level = MIPS_CPU_ISA_III;
264                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
265                              MIPS_CPU_LLSC;
266                 c->tlbsize = 32;
267                 break;
268         case PRID_IMP_R4600:
269                 c->cputype = CPU_R4600;
270                 c->isa_level = MIPS_CPU_ISA_III;
271                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
272                 c->tlbsize = 48;
273                 break;
274         #if 0
275         case PRID_IMP_R4650:
276                 /*
277                  * This processor doesn't have an MMU, so it's not
278                  * "real easy" to run Linux on it. It is left purely
279                  * for documentation.  Commented out because it shares
280                  * it's c0_prid id number with the TX3900.
281                  */
282                 c->cputype = CPU_R4650;
283                 c->isa_level = MIPS_CPU_ISA_III;
284                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
285                 c->tlbsize = 48;
286                 break;
287         #endif
288         case PRID_IMP_TX39:
289                 c->isa_level = MIPS_CPU_ISA_I;
290                 c->options = MIPS_CPU_TLB;
291
292                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
293                         c->cputype = CPU_TX3927;
294                         c->tlbsize = 64;
295                 } else {
296                         switch (c->processor_id & 0xff) {
297                         case PRID_REV_TX3912:
298                                 c->cputype = CPU_TX3912;
299                                 c->tlbsize = 32;
300                                 break;
301                         case PRID_REV_TX3922:
302                                 c->cputype = CPU_TX3922;
303                                 c->tlbsize = 64;
304                                 break;
305                         default:
306                                 c->cputype = CPU_UNKNOWN;
307                                 break;
308                         }
309                 }
310                 break;
311         case PRID_IMP_R4700:
312                 c->cputype = CPU_R4700;
313                 c->isa_level = MIPS_CPU_ISA_III;
314                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
315                              MIPS_CPU_LLSC;
316                 c->tlbsize = 48;
317                 break;
318         case PRID_IMP_TX49:
319                 c->cputype = CPU_TX49XX;
320                 c->isa_level = MIPS_CPU_ISA_III;
321                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
322                 if (!(c->processor_id & 0x08))
323                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
324                 c->tlbsize = 48;
325                 break;
326         case PRID_IMP_R5000:
327                 c->cputype = CPU_R5000;
328                 c->isa_level = MIPS_CPU_ISA_IV;
329                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
330                              MIPS_CPU_LLSC;
331                 c->tlbsize = 48;
332                 break;
333         case PRID_IMP_R5432:
334                 c->cputype = CPU_R5432;
335                 c->isa_level = MIPS_CPU_ISA_IV;
336                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
337                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
338                 c->tlbsize = 48;
339                 break;
340         case PRID_IMP_R5500:
341                 c->cputype = CPU_R5500;
342                 c->isa_level = MIPS_CPU_ISA_IV;
343                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
344                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
345                 c->tlbsize = 48;
346                 break;
347         case PRID_IMP_NEVADA:
348                 c->cputype = CPU_NEVADA;
349                 c->isa_level = MIPS_CPU_ISA_IV;
350                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
351                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
352                 c->tlbsize = 48;
353                 break;
354         case PRID_IMP_R6000:
355                 c->cputype = CPU_R6000;
356                 c->isa_level = MIPS_CPU_ISA_II;
357                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
358                              MIPS_CPU_LLSC;
359                 c->tlbsize = 32;
360                 break;
361         case PRID_IMP_R6000A:
362                 c->cputype = CPU_R6000A;
363                 c->isa_level = MIPS_CPU_ISA_II;
364                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
365                              MIPS_CPU_LLSC;
366                 c->tlbsize = 32;
367                 break;
368         case PRID_IMP_RM7000:
369                 c->cputype = CPU_RM7000;
370                 c->isa_level = MIPS_CPU_ISA_IV;
371                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
372                              MIPS_CPU_LLSC;
373                 /*
374                  * Undocumented RM7000:  Bit 29 in the info register of
375                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
376                  * entries.
377                  *
378                  * 29      1 =>    64 entry JTLB
379                  *         0 =>    48 entry JTLB
380                  */
381                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
382                 break;
383         case PRID_IMP_RM9000:
384                 c->cputype = CPU_RM9000;
385                 c->isa_level = MIPS_CPU_ISA_IV;
386                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
387                              MIPS_CPU_LLSC;
388                 /*
389                  * Bit 29 in the info register of the RM9000
390                  * indicates if the TLB has 48 or 64 entries.
391                  *
392                  * 29      1 =>    64 entry JTLB
393                  *         0 =>    48 entry JTLB
394                  */
395                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
396                 break;
397         case PRID_IMP_R8000:
398                 c->cputype = CPU_R8000;
399                 c->isa_level = MIPS_CPU_ISA_IV;
400                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
401                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
402                              MIPS_CPU_LLSC;
403                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
404                 break;
405         case PRID_IMP_R10000:
406                 c->cputype = CPU_R10000;
407                 c->isa_level = MIPS_CPU_ISA_IV;
408                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
409                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
410                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
411                              MIPS_CPU_LLSC;
412                 c->tlbsize = 64;
413                 break;
414         case PRID_IMP_R12000:
415                 c->cputype = CPU_R12000;
416                 c->isa_level = MIPS_CPU_ISA_IV;
417                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
418                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
419                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
420                              MIPS_CPU_LLSC;
421                 c->tlbsize = 64;
422                 break;
423         }
424 }
425
426 static inline void decode_config1(struct cpuinfo_mips *c)
427 {
428         unsigned long config0 = read_c0_config();
429         unsigned long config1;
430
431         if ((config0 & (1 << 31)) == 0)
432                 return;                 /* actually wort a panic() */
433
434         /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
435         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
436                 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
437                 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
438         config1 = read_c0_config1();
439         if (config1 & (1 << 3))
440                 c->options |= MIPS_CPU_WATCH;
441         if (config1 & (1 << 2))
442                 c->options |= MIPS_CPU_MIPS16;
443         if (config1 & (1 << 1))
444                 c->options |= MIPS_CPU_EJTAG;
445         if (config1 & 1) {
446                 c->options |= MIPS_CPU_FPU;
447                 c->options |= MIPS_CPU_32FPR;
448         }
449         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
450
451         c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
452 }
453
454 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
455 {
456         decode_config1(c);
457         switch (c->processor_id & 0xff00) {
458         case PRID_IMP_4KC:
459                 c->cputype = CPU_4KC;
460                 c->isa_level = MIPS_CPU_ISA_M32;
461                 break;
462         case PRID_IMP_4KEC:
463                 c->cputype = CPU_4KEC;
464                 c->isa_level = MIPS_CPU_ISA_M32;
465                 break;
466         case PRID_IMP_4KSC:
467                 c->cputype = CPU_4KSC;
468                 c->isa_level = MIPS_CPU_ISA_M32;
469                 break;
470         case PRID_IMP_5KC:
471                 c->cputype = CPU_5KC;
472                 c->isa_level = MIPS_CPU_ISA_M64;
473                 break;
474         case PRID_IMP_20KC:
475                 c->cputype = CPU_20KC;
476                 c->isa_level = MIPS_CPU_ISA_M64;
477                 break;
478         case PRID_IMP_24K:
479                 c->cputype = CPU_24K;
480                 c->isa_level = MIPS_CPU_ISA_M32;
481                 break;
482         case PRID_IMP_25KF:
483                 c->cputype = CPU_25KF;
484                 c->isa_level = MIPS_CPU_ISA_M64;
485                 /* Probe for L2 cache */
486                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
487                 break;
488         }
489 }
490
491 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
492 {
493         decode_config1(c);
494         switch (c->processor_id & 0xff00) {
495         case PRID_IMP_AU1_REV1:
496         case PRID_IMP_AU1_REV2:
497                 switch ((c->processor_id >> 24) & 0xff) {
498                 case 0:
499                         c->cputype = CPU_AU1000;
500                         break;
501                 case 1:
502                         c->cputype = CPU_AU1500;
503                         break;
504                 case 2:
505                         c->cputype = CPU_AU1100;
506                         break;
507                 case 3:
508                         c->cputype = CPU_AU1550;
509                         break;
510                 case 4:
511                         c->cputype = CPU_AU1200;
512                         break;
513                 default:
514                         panic("Unknown Au Core!");
515                         break;
516                 }
517                 c->isa_level = MIPS_CPU_ISA_M32;
518                 break;
519         }
520 }
521
522 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
523 {
524         decode_config1(c);
525         switch (c->processor_id & 0xff00) {
526         case PRID_IMP_SB1:
527                 c->cputype = CPU_SB1;
528                 c->isa_level = MIPS_CPU_ISA_M64;
529                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
530                              MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
531                              MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
532                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
533 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
534                 /* FPU in pass1 is known to have issues. */
535                 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
536 #endif
537                 break;
538         }
539 }
540
541 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
542 {
543         decode_config1(c);
544         switch (c->processor_id & 0xff00) {
545         case PRID_IMP_SR71000:
546                 c->cputype = CPU_SR71000;
547                 c->isa_level = MIPS_CPU_ISA_M64;
548                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
549                              MIPS_CPU_4KTLB | MIPS_CPU_FPU |
550                              MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
551                 c->scache.ways = 8;
552                 c->tlbsize = 64;
553                 break;
554         }
555 }
556
557 __init void cpu_probe(void)
558 {
559         struct cpuinfo_mips *c = &current_cpu_data;
560
561         c->processor_id = PRID_IMP_UNKNOWN;
562         c->fpu_id       = FPIR_IMP_NONE;
563         c->cputype      = CPU_UNKNOWN;
564
565         c->processor_id = read_c0_prid();
566         switch (c->processor_id & 0xff0000) {
567         case PRID_COMP_LEGACY:
568                 cpu_probe_legacy(c);
569                 break;
570         case PRID_COMP_MIPS:
571                 cpu_probe_mips(c);
572                 break;
573         case PRID_COMP_ALCHEMY:
574                 cpu_probe_alchemy(c);
575                 break;
576         case PRID_COMP_SIBYTE:
577                 cpu_probe_sibyte(c);
578                 break;
579
580         case PRID_COMP_SANDCRAFT:
581                 cpu_probe_sandcraft(c);
582                 break;
583         default:
584                 c->cputype = CPU_UNKNOWN;
585         }
586         if (c->options & MIPS_CPU_FPU)
587                 c->fpu_id = cpu_get_fpu_id();
588 }
589
590 __init void cpu_report(void)
591 {
592         struct cpuinfo_mips *c = &current_cpu_data;
593
594         printk("CPU revision is: %08x\n", c->processor_id);
595         if (c->options & MIPS_CPU_FPU)
596                 printk("FPU revision is: %08x\n", c->fpu_id);
597 }