Remove obsolete #include <linux/config.h>
[linux-2.6.git] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/cpu.h>
20 #include <asm/fpu.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
23
24 /*
25  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26  * the implementation of the "wait" feature differs between CPU families. This
27  * points to the function that implements CPU specific wait.
28  * The wait instruction stops the pipeline and reduces the power consumption of
29  * the CPU very much.
30  */
31 void (*cpu_wait)(void) = NULL;
32
33 static void r3081_wait(void)
34 {
35         unsigned long cfg = read_c0_conf();
36         write_c0_conf(cfg | R30XX_CONF_HALT);
37 }
38
39 static void r39xx_wait(void)
40 {
41         unsigned long cfg = read_c0_conf();
42         write_c0_conf(cfg | TX39_CONF_HALT);
43 }
44
45 static void r4k_wait(void)
46 {
47         __asm__(".set\tmips3\n\t"
48                 "wait\n\t"
49                 ".set\tmips0");
50 }
51
52 /* The Au1xxx wait is available only if using 32khz counter or
53  * external timer source, but specifically not CP0 Counter. */
54 int allow_au1k_wait;
55
56 static void au1k_wait(void)
57 {
58         /* using the wait instruction makes CP0 counter unusable */
59         __asm__(".set mips3\n\t"
60                 "cache 0x14, 0(%0)\n\t"
61                 "cache 0x14, 32(%0)\n\t"
62                 "sync\n\t"
63                 "nop\n\t"
64                 "wait\n\t"
65                 "nop\n\t"
66                 "nop\n\t"
67                 "nop\n\t"
68                 "nop\n\t"
69                 ".set mips0\n\t"
70                 : : "r" (au1k_wait));
71 }
72
73 static int __initdata nowait = 0;
74
75 int __init wait_disable(char *s)
76 {
77         nowait = 1;
78
79         return 1;
80 }
81
82 __setup("nowait", wait_disable);
83
84 static inline void check_wait(void)
85 {
86         struct cpuinfo_mips *c = &current_cpu_data;
87
88         printk("Checking for 'wait' instruction... ");
89         if (nowait) {
90                 printk (" disabled.\n");
91                 return;
92         }
93
94         switch (c->cputype) {
95         case CPU_R3081:
96         case CPU_R3081E:
97                 cpu_wait = r3081_wait;
98                 printk(" available.\n");
99                 break;
100         case CPU_TX3927:
101                 cpu_wait = r39xx_wait;
102                 printk(" available.\n");
103                 break;
104         case CPU_R4200:
105 /*      case CPU_R4300: */
106         case CPU_R4600:
107         case CPU_R4640:
108         case CPU_R4650:
109         case CPU_R4700:
110         case CPU_R5000:
111         case CPU_NEVADA:
112         case CPU_RM7000:
113         case CPU_RM9000:
114         case CPU_TX49XX:
115         case CPU_4KC:
116         case CPU_4KEC:
117         case CPU_4KSC:
118         case CPU_5KC:
119 /*      case CPU_20KC:*/
120         case CPU_24K:
121         case CPU_25KF:
122         case CPU_34K:
123         case CPU_74K:
124         case CPU_PR4450:
125                 cpu_wait = r4k_wait;
126                 printk(" available.\n");
127                 break;
128         case CPU_AU1000:
129         case CPU_AU1100:
130         case CPU_AU1500:
131         case CPU_AU1550:
132         case CPU_AU1200:
133                 if (allow_au1k_wait) {
134                         cpu_wait = au1k_wait;
135                         printk(" available.\n");
136                 } else
137                         printk(" unavailable.\n");
138                 break;
139         default:
140                 printk(" unavailable.\n");
141                 break;
142         }
143 }
144
145 void __init check_bugs32(void)
146 {
147         check_wait();
148 }
149
150 /*
151  * Probe whether cpu has config register by trying to play with
152  * alternate cache bit and see whether it matters.
153  * It's used by cpu_probe to distinguish between R3000A and R3081.
154  */
155 static inline int cpu_has_confreg(void)
156 {
157 #ifdef CONFIG_CPU_R3000
158         extern unsigned long r3k_cache_size(unsigned long);
159         unsigned long size1, size2;
160         unsigned long cfg = read_c0_conf();
161
162         size1 = r3k_cache_size(ST0_ISC);
163         write_c0_conf(cfg ^ R30XX_CONF_AC);
164         size2 = r3k_cache_size(ST0_ISC);
165         write_c0_conf(cfg);
166         return size1 != size2;
167 #else
168         return 0;
169 #endif
170 }
171
172 /*
173  * Get the FPU Implementation/Revision.
174  */
175 static inline unsigned long cpu_get_fpu_id(void)
176 {
177         unsigned long tmp, fpu_id;
178
179         tmp = read_c0_status();
180         __enable_fpu();
181         fpu_id = read_32bit_cp1_register(CP1_REVISION);
182         write_c0_status(tmp);
183         return fpu_id;
184 }
185
186 /*
187  * Check the CPU has an FPU the official way.
188  */
189 static inline int __cpu_has_fpu(void)
190 {
191         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
192 }
193
194 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
195                 | MIPS_CPU_COUNTER)
196
197 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
198 {
199         switch (c->processor_id & 0xff00) {
200         case PRID_IMP_R2000:
201                 c->cputype = CPU_R2000;
202                 c->isa_level = MIPS_CPU_ISA_I;
203                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
204                              MIPS_CPU_NOFPUEX;
205                 if (__cpu_has_fpu())
206                         c->options |= MIPS_CPU_FPU;
207                 c->tlbsize = 64;
208                 break;
209         case PRID_IMP_R3000:
210                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
211                         if (cpu_has_confreg())
212                                 c->cputype = CPU_R3081E;
213                         else
214                                 c->cputype = CPU_R3000A;
215                 else
216                         c->cputype = CPU_R3000;
217                 c->isa_level = MIPS_CPU_ISA_I;
218                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
219                              MIPS_CPU_NOFPUEX;
220                 if (__cpu_has_fpu())
221                         c->options |= MIPS_CPU_FPU;
222                 c->tlbsize = 64;
223                 break;
224         case PRID_IMP_R4000:
225                 if (read_c0_config() & CONF_SC) {
226                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
227                                 c->cputype = CPU_R4400PC;
228                         else
229                                 c->cputype = CPU_R4000PC;
230                 } else {
231                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
232                                 c->cputype = CPU_R4400SC;
233                         else
234                                 c->cputype = CPU_R4000SC;
235                 }
236
237                 c->isa_level = MIPS_CPU_ISA_III;
238                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
239                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
240                              MIPS_CPU_LLSC;
241                 c->tlbsize = 48;
242                 break;
243         case PRID_IMP_VR41XX:
244                 switch (c->processor_id & 0xf0) {
245                 case PRID_REV_VR4111:
246                         c->cputype = CPU_VR4111;
247                         break;
248                 case PRID_REV_VR4121:
249                         c->cputype = CPU_VR4121;
250                         break;
251                 case PRID_REV_VR4122:
252                         if ((c->processor_id & 0xf) < 0x3)
253                                 c->cputype = CPU_VR4122;
254                         else
255                                 c->cputype = CPU_VR4181A;
256                         break;
257                 case PRID_REV_VR4130:
258                         if ((c->processor_id & 0xf) < 0x4)
259                                 c->cputype = CPU_VR4131;
260                         else
261                                 c->cputype = CPU_VR4133;
262                         break;
263                 default:
264                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
265                         c->cputype = CPU_VR41XX;
266                         break;
267                 }
268                 c->isa_level = MIPS_CPU_ISA_III;
269                 c->options = R4K_OPTS;
270                 c->tlbsize = 32;
271                 break;
272         case PRID_IMP_R4300:
273                 c->cputype = CPU_R4300;
274                 c->isa_level = MIPS_CPU_ISA_III;
275                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
276                              MIPS_CPU_LLSC;
277                 c->tlbsize = 32;
278                 break;
279         case PRID_IMP_R4600:
280                 c->cputype = CPU_R4600;
281                 c->isa_level = MIPS_CPU_ISA_III;
282                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
283                              MIPS_CPU_LLSC;
284                 c->tlbsize = 48;
285                 break;
286         #if 0
287         case PRID_IMP_R4650:
288                 /*
289                  * This processor doesn't have an MMU, so it's not
290                  * "real easy" to run Linux on it. It is left purely
291                  * for documentation.  Commented out because it shares
292                  * it's c0_prid id number with the TX3900.
293                  */
294                 c->cputype = CPU_R4650;
295                 c->isa_level = MIPS_CPU_ISA_III;
296                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
297                 c->tlbsize = 48;
298                 break;
299         #endif
300         case PRID_IMP_TX39:
301                 c->isa_level = MIPS_CPU_ISA_I;
302                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
303
304                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
305                         c->cputype = CPU_TX3927;
306                         c->tlbsize = 64;
307                 } else {
308                         switch (c->processor_id & 0xff) {
309                         case PRID_REV_TX3912:
310                                 c->cputype = CPU_TX3912;
311                                 c->tlbsize = 32;
312                                 break;
313                         case PRID_REV_TX3922:
314                                 c->cputype = CPU_TX3922;
315                                 c->tlbsize = 64;
316                                 break;
317                         default:
318                                 c->cputype = CPU_UNKNOWN;
319                                 break;
320                         }
321                 }
322                 break;
323         case PRID_IMP_R4700:
324                 c->cputype = CPU_R4700;
325                 c->isa_level = MIPS_CPU_ISA_III;
326                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
327                              MIPS_CPU_LLSC;
328                 c->tlbsize = 48;
329                 break;
330         case PRID_IMP_TX49:
331                 c->cputype = CPU_TX49XX;
332                 c->isa_level = MIPS_CPU_ISA_III;
333                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
334                 if (!(c->processor_id & 0x08))
335                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
336                 c->tlbsize = 48;
337                 break;
338         case PRID_IMP_R5000:
339                 c->cputype = CPU_R5000;
340                 c->isa_level = MIPS_CPU_ISA_IV;
341                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
342                              MIPS_CPU_LLSC;
343                 c->tlbsize = 48;
344                 break;
345         case PRID_IMP_R5432:
346                 c->cputype = CPU_R5432;
347                 c->isa_level = MIPS_CPU_ISA_IV;
348                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
349                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
350                 c->tlbsize = 48;
351                 break;
352         case PRID_IMP_R5500:
353                 c->cputype = CPU_R5500;
354                 c->isa_level = MIPS_CPU_ISA_IV;
355                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
356                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
357                 c->tlbsize = 48;
358                 break;
359         case PRID_IMP_NEVADA:
360                 c->cputype = CPU_NEVADA;
361                 c->isa_level = MIPS_CPU_ISA_IV;
362                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
363                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
364                 c->tlbsize = 48;
365                 break;
366         case PRID_IMP_R6000:
367                 c->cputype = CPU_R6000;
368                 c->isa_level = MIPS_CPU_ISA_II;
369                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
370                              MIPS_CPU_LLSC;
371                 c->tlbsize = 32;
372                 break;
373         case PRID_IMP_R6000A:
374                 c->cputype = CPU_R6000A;
375                 c->isa_level = MIPS_CPU_ISA_II;
376                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
377                              MIPS_CPU_LLSC;
378                 c->tlbsize = 32;
379                 break;
380         case PRID_IMP_RM7000:
381                 c->cputype = CPU_RM7000;
382                 c->isa_level = MIPS_CPU_ISA_IV;
383                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
384                              MIPS_CPU_LLSC;
385                 /*
386                  * Undocumented RM7000:  Bit 29 in the info register of
387                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
388                  * entries.
389                  *
390                  * 29      1 =>    64 entry JTLB
391                  *         0 =>    48 entry JTLB
392                  */
393                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
394                 break;
395         case PRID_IMP_RM9000:
396                 c->cputype = CPU_RM9000;
397                 c->isa_level = MIPS_CPU_ISA_IV;
398                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
399                              MIPS_CPU_LLSC;
400                 /*
401                  * Bit 29 in the info register of the RM9000
402                  * indicates if the TLB has 48 or 64 entries.
403                  *
404                  * 29      1 =>    64 entry JTLB
405                  *         0 =>    48 entry JTLB
406                  */
407                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
408                 break;
409         case PRID_IMP_R8000:
410                 c->cputype = CPU_R8000;
411                 c->isa_level = MIPS_CPU_ISA_IV;
412                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
413                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
414                              MIPS_CPU_LLSC;
415                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
416                 break;
417         case PRID_IMP_R10000:
418                 c->cputype = CPU_R10000;
419                 c->isa_level = MIPS_CPU_ISA_IV;
420                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
421                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
422                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
423                              MIPS_CPU_LLSC;
424                 c->tlbsize = 64;
425                 break;
426         case PRID_IMP_R12000:
427                 c->cputype = CPU_R12000;
428                 c->isa_level = MIPS_CPU_ISA_IV;
429                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
430                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
431                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
432                              MIPS_CPU_LLSC;
433                 c->tlbsize = 64;
434                 break;
435         case PRID_IMP_R14000:
436                 c->cputype = CPU_R14000;
437                 c->isa_level = MIPS_CPU_ISA_IV;
438                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
439                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
440                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
441                              MIPS_CPU_LLSC;
442                 c->tlbsize = 64;
443                 break;
444         }
445 }
446
447 static char unknown_isa[] __initdata = KERN_ERR \
448         "Unsupported ISA type, c0.config0: %d.";
449
450 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
451 {
452         unsigned int config0;
453         int isa;
454
455         config0 = read_c0_config();
456
457         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
458                 c->options |= MIPS_CPU_TLB;
459         isa = (config0 & MIPS_CONF_AT) >> 13;
460         switch (isa) {
461         case 0:
462                 switch ((config0 >> 10) & 7) {
463                 case 0:
464                         c->isa_level = MIPS_CPU_ISA_M32R1;
465                         break;
466                 case 1:
467                         c->isa_level = MIPS_CPU_ISA_M32R2;
468                         break;
469                 default:
470                         goto unknown;
471                 }
472                 break;
473         case 2:
474                 switch ((config0 >> 10) & 7) {
475                 case 0:
476                         c->isa_level = MIPS_CPU_ISA_M64R1;
477                         break;
478                 case 1:
479                         c->isa_level = MIPS_CPU_ISA_M64R2;
480                         break;
481                 default:
482                         goto unknown;
483                 }
484                 break;
485         default:
486                 goto unknown;
487         }
488
489         return config0 & MIPS_CONF_M;
490
491 unknown:
492         panic(unknown_isa, config0);
493 }
494
495 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
496 {
497         unsigned int config1;
498
499         config1 = read_c0_config1();
500
501         if (config1 & MIPS_CONF1_MD)
502                 c->ases |= MIPS_ASE_MDMX;
503         if (config1 & MIPS_CONF1_WR)
504                 c->options |= MIPS_CPU_WATCH;
505         if (config1 & MIPS_CONF1_CA)
506                 c->ases |= MIPS_ASE_MIPS16;
507         if (config1 & MIPS_CONF1_EP)
508                 c->options |= MIPS_CPU_EJTAG;
509         if (config1 & MIPS_CONF1_FP) {
510                 c->options |= MIPS_CPU_FPU;
511                 c->options |= MIPS_CPU_32FPR;
512         }
513         if (cpu_has_tlb)
514                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
515
516         return config1 & MIPS_CONF_M;
517 }
518
519 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
520 {
521         unsigned int config2;
522
523         config2 = read_c0_config2();
524
525         if (config2 & MIPS_CONF2_SL)
526                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
527
528         return config2 & MIPS_CONF_M;
529 }
530
531 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
532 {
533         unsigned int config3;
534
535         config3 = read_c0_config3();
536
537         if (config3 & MIPS_CONF3_SM)
538                 c->ases |= MIPS_ASE_SMARTMIPS;
539         if (config3 & MIPS_CONF3_DSP)
540                 c->ases |= MIPS_ASE_DSP;
541         if (config3 & MIPS_CONF3_VINT)
542                 c->options |= MIPS_CPU_VINT;
543         if (config3 & MIPS_CONF3_VEIC)
544                 c->options |= MIPS_CPU_VEIC;
545         if (config3 & MIPS_CONF3_MT)
546                 c->ases |= MIPS_ASE_MIPSMT;
547
548         return config3 & MIPS_CONF_M;
549 }
550
551 static inline void decode_configs(struct cpuinfo_mips *c)
552 {
553         /* MIPS32 or MIPS64 compliant CPU.  */
554         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
555                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
556
557         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
558
559         /* Read Config registers.  */
560         if (!decode_config0(c))
561                 return;                 /* actually worth a panic() */
562         if (!decode_config1(c))
563                 return;
564         if (!decode_config2(c))
565                 return;
566         if (!decode_config3(c))
567                 return;
568 }
569
570 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
571 {
572         decode_configs(c);
573         switch (c->processor_id & 0xff00) {
574         case PRID_IMP_4KC:
575                 c->cputype = CPU_4KC;
576                 break;
577         case PRID_IMP_4KEC:
578                 c->cputype = CPU_4KEC;
579                 break;
580         case PRID_IMP_4KECR2:
581                 c->cputype = CPU_4KEC;
582                 break;
583         case PRID_IMP_4KSC:
584         case PRID_IMP_4KSD:
585                 c->cputype = CPU_4KSC;
586                 break;
587         case PRID_IMP_5KC:
588                 c->cputype = CPU_5KC;
589                 break;
590         case PRID_IMP_20KC:
591                 c->cputype = CPU_20KC;
592                 break;
593         case PRID_IMP_24K:
594         case PRID_IMP_24KE:
595                 c->cputype = CPU_24K;
596                 break;
597         case PRID_IMP_25KF:
598                 c->cputype = CPU_25KF;
599                 break;
600         case PRID_IMP_34K:
601                 c->cputype = CPU_34K;
602                 break;
603         case PRID_IMP_74K:
604                 c->cputype = CPU_74K;
605                 break;
606         }
607 }
608
609 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
610 {
611         decode_configs(c);
612         switch (c->processor_id & 0xff00) {
613         case PRID_IMP_AU1_REV1:
614         case PRID_IMP_AU1_REV2:
615                 switch ((c->processor_id >> 24) & 0xff) {
616                 case 0:
617                         c->cputype = CPU_AU1000;
618                         break;
619                 case 1:
620                         c->cputype = CPU_AU1500;
621                         break;
622                 case 2:
623                         c->cputype = CPU_AU1100;
624                         break;
625                 case 3:
626                         c->cputype = CPU_AU1550;
627                         break;
628                 case 4:
629                         c->cputype = CPU_AU1200;
630                         break;
631                 default:
632                         panic("Unknown Au Core!");
633                         break;
634                 }
635                 break;
636         }
637 }
638
639 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
640 {
641         decode_configs(c);
642
643         /*
644          * For historical reasons the SB1 comes with it's own variant of
645          * cache code which eventually will be folded into c-r4k.c.  Until
646          * then we pretend it's got it's own cache architecture.
647          */
648         c->options &= ~MIPS_CPU_4K_CACHE;
649         c->options |= MIPS_CPU_SB1_CACHE;
650
651         switch (c->processor_id & 0xff00) {
652         case PRID_IMP_SB1:
653                 c->cputype = CPU_SB1;
654                 /* FPU in pass1 is known to have issues. */
655                 if ((c->processor_id & 0xff) < 0x02)
656                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
657                 break;
658         case PRID_IMP_SB1A:
659                 c->cputype = CPU_SB1A;
660                 break;
661         }
662 }
663
664 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
665 {
666         decode_configs(c);
667         switch (c->processor_id & 0xff00) {
668         case PRID_IMP_SR71000:
669                 c->cputype = CPU_SR71000;
670                 c->scache.ways = 8;
671                 c->tlbsize = 64;
672                 break;
673         }
674 }
675
676 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
677 {
678         decode_configs(c);
679         switch (c->processor_id & 0xff00) {
680         case PRID_IMP_PR4450:
681                 c->cputype = CPU_PR4450;
682                 c->isa_level = MIPS_CPU_ISA_M32R1;
683                 break;
684         default:
685                 panic("Unknown Philips Core!"); /* REVISIT: die? */
686                 break;
687         }
688 }
689
690
691 __init void cpu_probe(void)
692 {
693         struct cpuinfo_mips *c = &current_cpu_data;
694
695         c->processor_id = PRID_IMP_UNKNOWN;
696         c->fpu_id       = FPIR_IMP_NONE;
697         c->cputype      = CPU_UNKNOWN;
698
699         c->processor_id = read_c0_prid();
700         switch (c->processor_id & 0xff0000) {
701         case PRID_COMP_LEGACY:
702                 cpu_probe_legacy(c);
703                 break;
704         case PRID_COMP_MIPS:
705                 cpu_probe_mips(c);
706                 break;
707         case PRID_COMP_ALCHEMY:
708                 cpu_probe_alchemy(c);
709                 break;
710         case PRID_COMP_SIBYTE:
711                 cpu_probe_sibyte(c);
712                 break;
713         case PRID_COMP_SANDCRAFT:
714                 cpu_probe_sandcraft(c);
715                 break;
716         case PRID_COMP_PHILIPS:
717                 cpu_probe_philips(c);
718                 break;
719         default:
720                 c->cputype = CPU_UNKNOWN;
721         }
722         if (c->options & MIPS_CPU_FPU) {
723                 c->fpu_id = cpu_get_fpu_id();
724
725                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
726                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
727                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
728                     c->isa_level == MIPS_CPU_ISA_M64R2) {
729                         if (c->fpu_id & MIPS_FPIR_3D)
730                                 c->ases |= MIPS_ASE_MIPS3D;
731                 }
732         }
733 }
734
735 __init void cpu_report(void)
736 {
737         struct cpuinfo_mips *c = &current_cpu_data;
738
739         printk("CPU revision is: %08x\n", c->processor_id);
740         if (c->options & MIPS_CPU_FPU)
741                 printk("FPU revision is: %08x\n", c->fpu_id);
742 }