Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
[linux-2.6.git] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
29
30 /*
31  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32  * the implementation of the "wait" feature differs between CPU families. This
33  * points to the function that implements CPU specific wait.
34  * The wait instruction stops the pipeline and reduces the power consumption of
35  * the CPU very much.
36  */
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
39
40 static void r3081_wait(void)
41 {
42         unsigned long cfg = read_c0_conf();
43         write_c0_conf(cfg | R30XX_CONF_HALT);
44 }
45
46 static void r39xx_wait(void)
47 {
48         local_irq_disable();
49         if (!need_resched())
50                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51         local_irq_enable();
52 }
53
54 extern void r4k_wait(void);
55
56 /*
57  * This variant is preferable as it allows testing need_resched and going to
58  * sleep depending on the outcome atomically.  Unfortunately the "It is
59  * implementation-dependent whether the pipeline restarts when a non-enabled
60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61  * using this version a gamble.
62  */
63 void r4k_wait_irqoff(void)
64 {
65         local_irq_disable();
66         if (!need_resched())
67                 __asm__("       .set    push            \n"
68                         "       .set    mips3           \n"
69                         "       wait                    \n"
70                         "       .set    pop             \n");
71         local_irq_enable();
72         __asm__("       .globl __pastwait       \n"
73                 "__pastwait:                    \n");
74 }
75
76 /*
77  * The RM7000 variant has to handle erratum 38.  The workaround is to not
78  * have any pending stores when the WAIT instruction is executed.
79  */
80 static void rm7k_wait_irqoff(void)
81 {
82         local_irq_disable();
83         if (!need_resched())
84                 __asm__(
85                 "       .set    push                                    \n"
86                 "       .set    mips3                                   \n"
87                 "       .set    noat                                    \n"
88                 "       mfc0    $1, $12                                 \n"
89                 "       sync                                            \n"
90                 "       mtc0    $1, $12         # stalls until W stage  \n"
91                 "       wait                                            \n"
92                 "       mtc0    $1, $12         # stalls until W stage  \n"
93                 "       .set    pop                                     \n");
94         local_irq_enable();
95 }
96
97 /*
98  * The Au1xxx wait is available only if using 32khz counter or
99  * external timer source, but specifically not CP0 Counter.
100  * alchemy/common/time.c may override cpu_wait!
101  */
102 static void au1k_wait(void)
103 {
104         __asm__("       .set    mips3                   \n"
105                 "       cache   0x14, 0(%0)             \n"
106                 "       cache   0x14, 32(%0)            \n"
107                 "       sync                            \n"
108                 "       nop                             \n"
109                 "       wait                            \n"
110                 "       nop                             \n"
111                 "       nop                             \n"
112                 "       nop                             \n"
113                 "       nop                             \n"
114                 "       .set    mips0                   \n"
115                 : : "r" (au1k_wait));
116 }
117
118 static int __initdata nowait;
119
120 static int __init wait_disable(char *s)
121 {
122         nowait = 1;
123
124         return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 static int __cpuinitdata mips_fpu_disabled;
130
131 static int __init fpu_disable(char *s)
132 {
133         cpu_data[0].options &= ~MIPS_CPU_FPU;
134         mips_fpu_disabled = 1;
135
136         return 1;
137 }
138
139 __setup("nofpu", fpu_disable);
140
141 int __cpuinitdata mips_dsp_disabled;
142
143 static int __init dsp_disable(char *s)
144 {
145         cpu_data[0].ases &= ~MIPS_ASE_DSP;
146         mips_dsp_disabled = 1;
147
148         return 1;
149 }
150
151 __setup("nodsp", dsp_disable);
152
153 void __init check_wait(void)
154 {
155         struct cpuinfo_mips *c = &current_cpu_data;
156
157         if (nowait) {
158                 printk("Wait instruction disabled.\n");
159                 return;
160         }
161
162         switch (c->cputype) {
163         case CPU_R3081:
164         case CPU_R3081E:
165                 cpu_wait = r3081_wait;
166                 break;
167         case CPU_TX3927:
168                 cpu_wait = r39xx_wait;
169                 break;
170         case CPU_R4200:
171 /*      case CPU_R4300: */
172         case CPU_R4600:
173         case CPU_R4640:
174         case CPU_R4650:
175         case CPU_R4700:
176         case CPU_R5000:
177         case CPU_R5500:
178         case CPU_NEVADA:
179         case CPU_4KC:
180         case CPU_4KEC:
181         case CPU_4KSC:
182         case CPU_5KC:
183         case CPU_25KF:
184         case CPU_PR4450:
185         case CPU_BMIPS3300:
186         case CPU_BMIPS4350:
187         case CPU_BMIPS4380:
188         case CPU_BMIPS5000:
189         case CPU_CAVIUM_OCTEON:
190         case CPU_CAVIUM_OCTEON_PLUS:
191         case CPU_CAVIUM_OCTEON2:
192         case CPU_JZRISC:
193                 cpu_wait = r4k_wait;
194                 break;
195
196         case CPU_RM7000:
197                 cpu_wait = rm7k_wait_irqoff;
198                 break;
199
200         case CPU_24K:
201         case CPU_34K:
202         case CPU_1004K:
203                 cpu_wait = r4k_wait;
204                 if (read_c0_config7() & MIPS_CONF7_WII)
205                         cpu_wait = r4k_wait_irqoff;
206                 break;
207
208         case CPU_74K:
209                 cpu_wait = r4k_wait;
210                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
211                         cpu_wait = r4k_wait_irqoff;
212                 break;
213
214         case CPU_TX49XX:
215                 cpu_wait = r4k_wait_irqoff;
216                 break;
217         case CPU_ALCHEMY:
218                 cpu_wait = au1k_wait;
219                 break;
220         case CPU_20KC:
221                 /*
222                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
223                  * WAIT on Rev2.0 and Rev3.0 has E16.
224                  * Rev3.1 WAIT is nop, why bother
225                  */
226                 if ((c->processor_id & 0xff) <= 0x64)
227                         break;
228
229                 /*
230                  * Another rev is incremeting c0_count at a reduced clock
231                  * rate while in WAIT mode.  So we basically have the choice
232                  * between using the cp0 timer as clocksource or avoiding
233                  * the WAIT instruction.  Until more details are known,
234                  * disable the use of WAIT for 20Kc entirely.
235                    cpu_wait = r4k_wait;
236                  */
237                 break;
238         case CPU_RM9000:
239                 if ((c->processor_id & 0x00ff) >= 0x40)
240                         cpu_wait = r4k_wait;
241                 break;
242         default:
243                 break;
244         }
245 }
246
247 static inline void check_errata(void)
248 {
249         struct cpuinfo_mips *c = &current_cpu_data;
250
251         switch (c->cputype) {
252         case CPU_34K:
253                 /*
254                  * Erratum "RPS May Cause Incorrect Instruction Execution"
255                  * This code only handles VPE0, any SMP/SMTC/RTOS code
256                  * making use of VPE1 will be responsable for that VPE.
257                  */
258                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
259                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
260                 break;
261         default:
262                 break;
263         }
264 }
265
266 void __init check_bugs32(void)
267 {
268         check_errata();
269 }
270
271 /*
272  * Probe whether cpu has config register by trying to play with
273  * alternate cache bit and see whether it matters.
274  * It's used by cpu_probe to distinguish between R3000A and R3081.
275  */
276 static inline int cpu_has_confreg(void)
277 {
278 #ifdef CONFIG_CPU_R3000
279         extern unsigned long r3k_cache_size(unsigned long);
280         unsigned long size1, size2;
281         unsigned long cfg = read_c0_conf();
282
283         size1 = r3k_cache_size(ST0_ISC);
284         write_c0_conf(cfg ^ R30XX_CONF_AC);
285         size2 = r3k_cache_size(ST0_ISC);
286         write_c0_conf(cfg);
287         return size1 != size2;
288 #else
289         return 0;
290 #endif
291 }
292
293 static inline void set_elf_platform(int cpu, const char *plat)
294 {
295         if (cpu == 0)
296                 __elf_platform = plat;
297 }
298
299 /*
300  * Get the FPU Implementation/Revision.
301  */
302 static inline unsigned long cpu_get_fpu_id(void)
303 {
304         unsigned long tmp, fpu_id;
305
306         tmp = read_c0_status();
307         __enable_fpu();
308         fpu_id = read_32bit_cp1_register(CP1_REVISION);
309         write_c0_status(tmp);
310         return fpu_id;
311 }
312
313 /*
314  * Check the CPU has an FPU the official way.
315  */
316 static inline int __cpu_has_fpu(void)
317 {
318         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
319 }
320
321 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
322 {
323 #ifdef __NEED_VMBITS_PROBE
324         write_c0_entryhi(0x3fffffffffffe000ULL);
325         back_to_back_c0_hazard();
326         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
327 #endif
328 }
329
330 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
331                 | MIPS_CPU_COUNTER)
332
333 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
334 {
335         switch (c->processor_id & 0xff00) {
336         case PRID_IMP_R2000:
337                 c->cputype = CPU_R2000;
338                 __cpu_name[cpu] = "R2000";
339                 c->isa_level = MIPS_CPU_ISA_I;
340                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
341                              MIPS_CPU_NOFPUEX;
342                 if (__cpu_has_fpu())
343                         c->options |= MIPS_CPU_FPU;
344                 c->tlbsize = 64;
345                 break;
346         case PRID_IMP_R3000:
347                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
348                         if (cpu_has_confreg()) {
349                                 c->cputype = CPU_R3081E;
350                                 __cpu_name[cpu] = "R3081";
351                         } else {
352                                 c->cputype = CPU_R3000A;
353                                 __cpu_name[cpu] = "R3000A";
354                         }
355                         break;
356                 } else {
357                         c->cputype = CPU_R3000;
358                         __cpu_name[cpu] = "R3000";
359                 }
360                 c->isa_level = MIPS_CPU_ISA_I;
361                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
362                              MIPS_CPU_NOFPUEX;
363                 if (__cpu_has_fpu())
364                         c->options |= MIPS_CPU_FPU;
365                 c->tlbsize = 64;
366                 break;
367         case PRID_IMP_R4000:
368                 if (read_c0_config() & CONF_SC) {
369                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
370                                 c->cputype = CPU_R4400PC;
371                                 __cpu_name[cpu] = "R4400PC";
372                         } else {
373                                 c->cputype = CPU_R4000PC;
374                                 __cpu_name[cpu] = "R4000PC";
375                         }
376                 } else {
377                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
378                                 c->cputype = CPU_R4400SC;
379                                 __cpu_name[cpu] = "R4400SC";
380                         } else {
381                                 c->cputype = CPU_R4000SC;
382                                 __cpu_name[cpu] = "R4000SC";
383                         }
384                 }
385
386                 c->isa_level = MIPS_CPU_ISA_III;
387                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
388                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
389                              MIPS_CPU_LLSC;
390                 c->tlbsize = 48;
391                 break;
392         case PRID_IMP_VR41XX:
393                 switch (c->processor_id & 0xf0) {
394                 case PRID_REV_VR4111:
395                         c->cputype = CPU_VR4111;
396                         __cpu_name[cpu] = "NEC VR4111";
397                         break;
398                 case PRID_REV_VR4121:
399                         c->cputype = CPU_VR4121;
400                         __cpu_name[cpu] = "NEC VR4121";
401                         break;
402                 case PRID_REV_VR4122:
403                         if ((c->processor_id & 0xf) < 0x3) {
404                                 c->cputype = CPU_VR4122;
405                                 __cpu_name[cpu] = "NEC VR4122";
406                         } else {
407                                 c->cputype = CPU_VR4181A;
408                                 __cpu_name[cpu] = "NEC VR4181A";
409                         }
410                         break;
411                 case PRID_REV_VR4130:
412                         if ((c->processor_id & 0xf) < 0x4) {
413                                 c->cputype = CPU_VR4131;
414                                 __cpu_name[cpu] = "NEC VR4131";
415                         } else {
416                                 c->cputype = CPU_VR4133;
417                                 __cpu_name[cpu] = "NEC VR4133";
418                         }
419                         break;
420                 default:
421                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
422                         c->cputype = CPU_VR41XX;
423                         __cpu_name[cpu] = "NEC Vr41xx";
424                         break;
425                 }
426                 c->isa_level = MIPS_CPU_ISA_III;
427                 c->options = R4K_OPTS;
428                 c->tlbsize = 32;
429                 break;
430         case PRID_IMP_R4300:
431                 c->cputype = CPU_R4300;
432                 __cpu_name[cpu] = "R4300";
433                 c->isa_level = MIPS_CPU_ISA_III;
434                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
435                              MIPS_CPU_LLSC;
436                 c->tlbsize = 32;
437                 break;
438         case PRID_IMP_R4600:
439                 c->cputype = CPU_R4600;
440                 __cpu_name[cpu] = "R4600";
441                 c->isa_level = MIPS_CPU_ISA_III;
442                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443                              MIPS_CPU_LLSC;
444                 c->tlbsize = 48;
445                 break;
446         #if 0
447         case PRID_IMP_R4650:
448                 /*
449                  * This processor doesn't have an MMU, so it's not
450                  * "real easy" to run Linux on it. It is left purely
451                  * for documentation.  Commented out because it shares
452                  * it's c0_prid id number with the TX3900.
453                  */
454                 c->cputype = CPU_R4650;
455                 __cpu_name[cpu] = "R4650";
456                 c->isa_level = MIPS_CPU_ISA_III;
457                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
458                 c->tlbsize = 48;
459                 break;
460         #endif
461         case PRID_IMP_TX39:
462                 c->isa_level = MIPS_CPU_ISA_I;
463                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
464
465                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
466                         c->cputype = CPU_TX3927;
467                         __cpu_name[cpu] = "TX3927";
468                         c->tlbsize = 64;
469                 } else {
470                         switch (c->processor_id & 0xff) {
471                         case PRID_REV_TX3912:
472                                 c->cputype = CPU_TX3912;
473                                 __cpu_name[cpu] = "TX3912";
474                                 c->tlbsize = 32;
475                                 break;
476                         case PRID_REV_TX3922:
477                                 c->cputype = CPU_TX3922;
478                                 __cpu_name[cpu] = "TX3922";
479                                 c->tlbsize = 64;
480                                 break;
481                         }
482                 }
483                 break;
484         case PRID_IMP_R4700:
485                 c->cputype = CPU_R4700;
486                 __cpu_name[cpu] = "R4700";
487                 c->isa_level = MIPS_CPU_ISA_III;
488                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
489                              MIPS_CPU_LLSC;
490                 c->tlbsize = 48;
491                 break;
492         case PRID_IMP_TX49:
493                 c->cputype = CPU_TX49XX;
494                 __cpu_name[cpu] = "R49XX";
495                 c->isa_level = MIPS_CPU_ISA_III;
496                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
497                 if (!(c->processor_id & 0x08))
498                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
499                 c->tlbsize = 48;
500                 break;
501         case PRID_IMP_R5000:
502                 c->cputype = CPU_R5000;
503                 __cpu_name[cpu] = "R5000";
504                 c->isa_level = MIPS_CPU_ISA_IV;
505                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506                              MIPS_CPU_LLSC;
507                 c->tlbsize = 48;
508                 break;
509         case PRID_IMP_R5432:
510                 c->cputype = CPU_R5432;
511                 __cpu_name[cpu] = "R5432";
512                 c->isa_level = MIPS_CPU_ISA_IV;
513                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
515                 c->tlbsize = 48;
516                 break;
517         case PRID_IMP_R5500:
518                 c->cputype = CPU_R5500;
519                 __cpu_name[cpu] = "R5500";
520                 c->isa_level = MIPS_CPU_ISA_IV;
521                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
523                 c->tlbsize = 48;
524                 break;
525         case PRID_IMP_NEVADA:
526                 c->cputype = CPU_NEVADA;
527                 __cpu_name[cpu] = "Nevada";
528                 c->isa_level = MIPS_CPU_ISA_IV;
529                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
530                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
531                 c->tlbsize = 48;
532                 break;
533         case PRID_IMP_R6000:
534                 c->cputype = CPU_R6000;
535                 __cpu_name[cpu] = "R6000";
536                 c->isa_level = MIPS_CPU_ISA_II;
537                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
538                              MIPS_CPU_LLSC;
539                 c->tlbsize = 32;
540                 break;
541         case PRID_IMP_R6000A:
542                 c->cputype = CPU_R6000A;
543                 __cpu_name[cpu] = "R6000A";
544                 c->isa_level = MIPS_CPU_ISA_II;
545                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
546                              MIPS_CPU_LLSC;
547                 c->tlbsize = 32;
548                 break;
549         case PRID_IMP_RM7000:
550                 c->cputype = CPU_RM7000;
551                 __cpu_name[cpu] = "RM7000";
552                 c->isa_level = MIPS_CPU_ISA_IV;
553                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
554                              MIPS_CPU_LLSC;
555                 /*
556                  * Undocumented RM7000:  Bit 29 in the info register of
557                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
558                  * entries.
559                  *
560                  * 29      1 =>    64 entry JTLB
561                  *         0 =>    48 entry JTLB
562                  */
563                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
564                 break;
565         case PRID_IMP_RM9000:
566                 c->cputype = CPU_RM9000;
567                 __cpu_name[cpu] = "RM9000";
568                 c->isa_level = MIPS_CPU_ISA_IV;
569                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
570                              MIPS_CPU_LLSC;
571                 /*
572                  * Bit 29 in the info register of the RM9000
573                  * indicates if the TLB has 48 or 64 entries.
574                  *
575                  * 29      1 =>    64 entry JTLB
576                  *         0 =>    48 entry JTLB
577                  */
578                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
579                 break;
580         case PRID_IMP_R8000:
581                 c->cputype = CPU_R8000;
582                 __cpu_name[cpu] = "RM8000";
583                 c->isa_level = MIPS_CPU_ISA_IV;
584                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
585                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
586                              MIPS_CPU_LLSC;
587                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
588                 break;
589         case PRID_IMP_R10000:
590                 c->cputype = CPU_R10000;
591                 __cpu_name[cpu] = "R10000";
592                 c->isa_level = MIPS_CPU_ISA_IV;
593                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
594                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
595                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
596                              MIPS_CPU_LLSC;
597                 c->tlbsize = 64;
598                 break;
599         case PRID_IMP_R12000:
600                 c->cputype = CPU_R12000;
601                 __cpu_name[cpu] = "R12000";
602                 c->isa_level = MIPS_CPU_ISA_IV;
603                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
604                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
605                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
606                              MIPS_CPU_LLSC;
607                 c->tlbsize = 64;
608                 break;
609         case PRID_IMP_R14000:
610                 c->cputype = CPU_R14000;
611                 __cpu_name[cpu] = "R14000";
612                 c->isa_level = MIPS_CPU_ISA_IV;
613                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
614                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
615                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
616                              MIPS_CPU_LLSC;
617                 c->tlbsize = 64;
618                 break;
619         case PRID_IMP_LOONGSON2:
620                 c->cputype = CPU_LOONGSON2;
621                 __cpu_name[cpu] = "ICT Loongson-2";
622
623                 switch (c->processor_id & PRID_REV_MASK) {
624                 case PRID_REV_LOONGSON2E:
625                         set_elf_platform(cpu, "loongson2e");
626                         break;
627                 case PRID_REV_LOONGSON2F:
628                         set_elf_platform(cpu, "loongson2f");
629                         break;
630                 }
631
632                 c->isa_level = MIPS_CPU_ISA_III;
633                 c->options = R4K_OPTS |
634                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
635                              MIPS_CPU_32FPR;
636                 c->tlbsize = 64;
637                 break;
638         }
639 }
640
641 static char unknown_isa[] __cpuinitdata = KERN_ERR \
642         "Unsupported ISA type, c0.config0: %d.";
643
644 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
645 {
646         unsigned int config0;
647         int isa;
648
649         config0 = read_c0_config();
650
651         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
652                 c->options |= MIPS_CPU_TLB;
653         isa = (config0 & MIPS_CONF_AT) >> 13;
654         switch (isa) {
655         case 0:
656                 switch ((config0 & MIPS_CONF_AR) >> 10) {
657                 case 0:
658                         c->isa_level = MIPS_CPU_ISA_M32R1;
659                         break;
660                 case 1:
661                         c->isa_level = MIPS_CPU_ISA_M32R2;
662                         break;
663                 default:
664                         goto unknown;
665                 }
666                 break;
667         case 2:
668                 switch ((config0 & MIPS_CONF_AR) >> 10) {
669                 case 0:
670                         c->isa_level = MIPS_CPU_ISA_M64R1;
671                         break;
672                 case 1:
673                         c->isa_level = MIPS_CPU_ISA_M64R2;
674                         break;
675                 default:
676                         goto unknown;
677                 }
678                 break;
679         default:
680                 goto unknown;
681         }
682
683         return config0 & MIPS_CONF_M;
684
685 unknown:
686         panic(unknown_isa, config0);
687 }
688
689 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
690 {
691         unsigned int config1;
692
693         config1 = read_c0_config1();
694
695         if (config1 & MIPS_CONF1_MD)
696                 c->ases |= MIPS_ASE_MDMX;
697         if (config1 & MIPS_CONF1_WR)
698                 c->options |= MIPS_CPU_WATCH;
699         if (config1 & MIPS_CONF1_CA)
700                 c->ases |= MIPS_ASE_MIPS16;
701         if (config1 & MIPS_CONF1_EP)
702                 c->options |= MIPS_CPU_EJTAG;
703         if (config1 & MIPS_CONF1_FP) {
704                 c->options |= MIPS_CPU_FPU;
705                 c->options |= MIPS_CPU_32FPR;
706         }
707         if (cpu_has_tlb)
708                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
709
710         return config1 & MIPS_CONF_M;
711 }
712
713 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
714 {
715         unsigned int config2;
716
717         config2 = read_c0_config2();
718
719         if (config2 & MIPS_CONF2_SL)
720                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
721
722         return config2 & MIPS_CONF_M;
723 }
724
725 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
726 {
727         unsigned int config3;
728
729         config3 = read_c0_config3();
730
731         if (config3 & MIPS_CONF3_SM)
732                 c->ases |= MIPS_ASE_SMARTMIPS;
733         if (config3 & MIPS_CONF3_DSP)
734                 c->ases |= MIPS_ASE_DSP;
735         if (config3 & MIPS_CONF3_VINT)
736                 c->options |= MIPS_CPU_VINT;
737         if (config3 & MIPS_CONF3_VEIC)
738                 c->options |= MIPS_CPU_VEIC;
739         if (config3 & MIPS_CONF3_MT)
740                 c->ases |= MIPS_ASE_MIPSMT;
741         if (config3 & MIPS_CONF3_ULRI)
742                 c->options |= MIPS_CPU_ULRI;
743
744         return config3 & MIPS_CONF_M;
745 }
746
747 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
748 {
749         unsigned int config4;
750
751         config4 = read_c0_config4();
752
753         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
754             && cpu_has_tlb)
755                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
756
757         c->kscratch_mask = (config4 >> 16) & 0xff;
758
759         return config4 & MIPS_CONF_M;
760 }
761
762 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
763 {
764         int ok;
765
766         /* MIPS32 or MIPS64 compliant CPU.  */
767         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
768                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
769
770         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
771
772         ok = decode_config0(c);                 /* Read Config registers.  */
773         BUG_ON(!ok);                            /* Arch spec violation!  */
774         if (ok)
775                 ok = decode_config1(c);
776         if (ok)
777                 ok = decode_config2(c);
778         if (ok)
779                 ok = decode_config3(c);
780         if (ok)
781                 ok = decode_config4(c);
782
783         mips_probe_watch_registers(c);
784
785         if (cpu_has_mips_r2)
786                 c->core = read_c0_ebase() & 0x3ff;
787 }
788
789 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
790 {
791         decode_configs(c);
792         switch (c->processor_id & 0xff00) {
793         case PRID_IMP_4KC:
794                 c->cputype = CPU_4KC;
795                 __cpu_name[cpu] = "MIPS 4Kc";
796                 break;
797         case PRID_IMP_4KEC:
798         case PRID_IMP_4KECR2:
799                 c->cputype = CPU_4KEC;
800                 __cpu_name[cpu] = "MIPS 4KEc";
801                 break;
802         case PRID_IMP_4KSC:
803         case PRID_IMP_4KSD:
804                 c->cputype = CPU_4KSC;
805                 __cpu_name[cpu] = "MIPS 4KSc";
806                 break;
807         case PRID_IMP_5KC:
808                 c->cputype = CPU_5KC;
809                 __cpu_name[cpu] = "MIPS 5Kc";
810                 break;
811         case PRID_IMP_20KC:
812                 c->cputype = CPU_20KC;
813                 __cpu_name[cpu] = "MIPS 20Kc";
814                 break;
815         case PRID_IMP_24K:
816         case PRID_IMP_24KE:
817                 c->cputype = CPU_24K;
818                 __cpu_name[cpu] = "MIPS 24Kc";
819                 break;
820         case PRID_IMP_25KF:
821                 c->cputype = CPU_25KF;
822                 __cpu_name[cpu] = "MIPS 25Kc";
823                 break;
824         case PRID_IMP_34K:
825                 c->cputype = CPU_34K;
826                 __cpu_name[cpu] = "MIPS 34Kc";
827                 break;
828         case PRID_IMP_74K:
829                 c->cputype = CPU_74K;
830                 __cpu_name[cpu] = "MIPS 74Kc";
831                 break;
832         case PRID_IMP_1004K:
833                 c->cputype = CPU_1004K;
834                 __cpu_name[cpu] = "MIPS 1004Kc";
835                 break;
836         }
837
838         spram_config();
839 }
840
841 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
842 {
843         decode_configs(c);
844         switch (c->processor_id & 0xff00) {
845         case PRID_IMP_AU1_REV1:
846         case PRID_IMP_AU1_REV2:
847                 c->cputype = CPU_ALCHEMY;
848                 switch ((c->processor_id >> 24) & 0xff) {
849                 case 0:
850                         __cpu_name[cpu] = "Au1000";
851                         break;
852                 case 1:
853                         __cpu_name[cpu] = "Au1500";
854                         break;
855                 case 2:
856                         __cpu_name[cpu] = "Au1100";
857                         break;
858                 case 3:
859                         __cpu_name[cpu] = "Au1550";
860                         break;
861                 case 4:
862                         __cpu_name[cpu] = "Au1200";
863                         if ((c->processor_id & 0xff) == 2)
864                                 __cpu_name[cpu] = "Au1250";
865                         break;
866                 case 5:
867                         __cpu_name[cpu] = "Au1210";
868                         break;
869                 default:
870                         __cpu_name[cpu] = "Au1xxx";
871                         break;
872                 }
873                 break;
874         }
875 }
876
877 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
878 {
879         decode_configs(c);
880
881         switch (c->processor_id & 0xff00) {
882         case PRID_IMP_SB1:
883                 c->cputype = CPU_SB1;
884                 __cpu_name[cpu] = "SiByte SB1";
885                 /* FPU in pass1 is known to have issues. */
886                 if ((c->processor_id & 0xff) < 0x02)
887                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
888                 break;
889         case PRID_IMP_SB1A:
890                 c->cputype = CPU_SB1A;
891                 __cpu_name[cpu] = "SiByte SB1A";
892                 break;
893         }
894 }
895
896 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
897 {
898         decode_configs(c);
899         switch (c->processor_id & 0xff00) {
900         case PRID_IMP_SR71000:
901                 c->cputype = CPU_SR71000;
902                 __cpu_name[cpu] = "Sandcraft SR71000";
903                 c->scache.ways = 8;
904                 c->tlbsize = 64;
905                 break;
906         }
907 }
908
909 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
910 {
911         decode_configs(c);
912         switch (c->processor_id & 0xff00) {
913         case PRID_IMP_PR4450:
914                 c->cputype = CPU_PR4450;
915                 __cpu_name[cpu] = "Philips PR4450";
916                 c->isa_level = MIPS_CPU_ISA_M32R1;
917                 break;
918         }
919 }
920
921 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
922 {
923         decode_configs(c);
924         switch (c->processor_id & 0xff00) {
925         case PRID_IMP_BMIPS32_REV4:
926         case PRID_IMP_BMIPS32_REV8:
927                 c->cputype = CPU_BMIPS32;
928                 __cpu_name[cpu] = "Broadcom BMIPS32";
929                 set_elf_platform(cpu, "bmips32");
930                 break;
931         case PRID_IMP_BMIPS3300:
932         case PRID_IMP_BMIPS3300_ALT:
933         case PRID_IMP_BMIPS3300_BUG:
934                 c->cputype = CPU_BMIPS3300;
935                 __cpu_name[cpu] = "Broadcom BMIPS3300";
936                 set_elf_platform(cpu, "bmips3300");
937                 break;
938         case PRID_IMP_BMIPS43XX: {
939                 int rev = c->processor_id & 0xff;
940
941                 if (rev >= PRID_REV_BMIPS4380_LO &&
942                                 rev <= PRID_REV_BMIPS4380_HI) {
943                         c->cputype = CPU_BMIPS4380;
944                         __cpu_name[cpu] = "Broadcom BMIPS4380";
945                         set_elf_platform(cpu, "bmips4380");
946                 } else {
947                         c->cputype = CPU_BMIPS4350;
948                         __cpu_name[cpu] = "Broadcom BMIPS4350";
949                         set_elf_platform(cpu, "bmips4350");
950                 }
951                 break;
952         }
953         case PRID_IMP_BMIPS5000:
954                 c->cputype = CPU_BMIPS5000;
955                 __cpu_name[cpu] = "Broadcom BMIPS5000";
956                 set_elf_platform(cpu, "bmips5000");
957                 c->options |= MIPS_CPU_ULRI;
958                 break;
959         }
960 }
961
962 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
963 {
964         decode_configs(c);
965         switch (c->processor_id & 0xff00) {
966         case PRID_IMP_CAVIUM_CN38XX:
967         case PRID_IMP_CAVIUM_CN31XX:
968         case PRID_IMP_CAVIUM_CN30XX:
969                 c->cputype = CPU_CAVIUM_OCTEON;
970                 __cpu_name[cpu] = "Cavium Octeon";
971                 goto platform;
972         case PRID_IMP_CAVIUM_CN58XX:
973         case PRID_IMP_CAVIUM_CN56XX:
974         case PRID_IMP_CAVIUM_CN50XX:
975         case PRID_IMP_CAVIUM_CN52XX:
976                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
977                 __cpu_name[cpu] = "Cavium Octeon+";
978 platform:
979                 set_elf_platform(cpu, "octeon");
980                 break;
981         case PRID_IMP_CAVIUM_CN63XX:
982                 c->cputype = CPU_CAVIUM_OCTEON2;
983                 __cpu_name[cpu] = "Cavium Octeon II";
984                 set_elf_platform(cpu, "octeon2");
985                 break;
986         default:
987                 printk(KERN_INFO "Unknown Octeon chip!\n");
988                 c->cputype = CPU_UNKNOWN;
989                 break;
990         }
991 }
992
993 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
994 {
995         decode_configs(c);
996         /* JZRISC does not implement the CP0 counter. */
997         c->options &= ~MIPS_CPU_COUNTER;
998         switch (c->processor_id & 0xff00) {
999         case PRID_IMP_JZRISC:
1000                 c->cputype = CPU_JZRISC;
1001                 __cpu_name[cpu] = "Ingenic JZRISC";
1002                 break;
1003         default:
1004                 panic("Unknown Ingenic Processor ID!");
1005                 break;
1006         }
1007 }
1008
1009 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1010 {
1011         decode_configs(c);
1012
1013         c->options = (MIPS_CPU_TLB       |
1014                         MIPS_CPU_4KEX    |
1015                         MIPS_CPU_COUNTER |
1016                         MIPS_CPU_DIVEC   |
1017                         MIPS_CPU_WATCH   |
1018                         MIPS_CPU_EJTAG   |
1019                         MIPS_CPU_LLSC);
1020
1021         switch (c->processor_id & 0xff00) {
1022         case PRID_IMP_NETLOGIC_XLR732:
1023         case PRID_IMP_NETLOGIC_XLR716:
1024         case PRID_IMP_NETLOGIC_XLR532:
1025         case PRID_IMP_NETLOGIC_XLR308:
1026         case PRID_IMP_NETLOGIC_XLR532C:
1027         case PRID_IMP_NETLOGIC_XLR516C:
1028         case PRID_IMP_NETLOGIC_XLR508C:
1029         case PRID_IMP_NETLOGIC_XLR308C:
1030                 c->cputype = CPU_XLR;
1031                 __cpu_name[cpu] = "Netlogic XLR";
1032                 break;
1033
1034         case PRID_IMP_NETLOGIC_XLS608:
1035         case PRID_IMP_NETLOGIC_XLS408:
1036         case PRID_IMP_NETLOGIC_XLS404:
1037         case PRID_IMP_NETLOGIC_XLS208:
1038         case PRID_IMP_NETLOGIC_XLS204:
1039         case PRID_IMP_NETLOGIC_XLS108:
1040         case PRID_IMP_NETLOGIC_XLS104:
1041         case PRID_IMP_NETLOGIC_XLS616B:
1042         case PRID_IMP_NETLOGIC_XLS608B:
1043         case PRID_IMP_NETLOGIC_XLS416B:
1044         case PRID_IMP_NETLOGIC_XLS412B:
1045         case PRID_IMP_NETLOGIC_XLS408B:
1046         case PRID_IMP_NETLOGIC_XLS404B:
1047                 c->cputype = CPU_XLR;
1048                 __cpu_name[cpu] = "Netlogic XLS";
1049                 break;
1050
1051         default:
1052                 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1053                        c->processor_id);
1054                 c->cputype = CPU_XLR;
1055                 break;
1056         }
1057
1058         c->isa_level = MIPS_CPU_ISA_M64R1;
1059         c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1060 }
1061
1062 #ifdef CONFIG_64BIT
1063 /* For use by uaccess.h */
1064 u64 __ua_limit;
1065 EXPORT_SYMBOL(__ua_limit);
1066 #endif
1067
1068 const char *__cpu_name[NR_CPUS];
1069 const char *__elf_platform;
1070
1071 __cpuinit void cpu_probe(void)
1072 {
1073         struct cpuinfo_mips *c = &current_cpu_data;
1074         unsigned int cpu = smp_processor_id();
1075
1076         c->processor_id = PRID_IMP_UNKNOWN;
1077         c->fpu_id       = FPIR_IMP_NONE;
1078         c->cputype      = CPU_UNKNOWN;
1079
1080         c->processor_id = read_c0_prid();
1081         switch (c->processor_id & 0xff0000) {
1082         case PRID_COMP_LEGACY:
1083                 cpu_probe_legacy(c, cpu);
1084                 break;
1085         case PRID_COMP_MIPS:
1086                 cpu_probe_mips(c, cpu);
1087                 break;
1088         case PRID_COMP_ALCHEMY:
1089                 cpu_probe_alchemy(c, cpu);
1090                 break;
1091         case PRID_COMP_SIBYTE:
1092                 cpu_probe_sibyte(c, cpu);
1093                 break;
1094         case PRID_COMP_BROADCOM:
1095                 cpu_probe_broadcom(c, cpu);
1096                 break;
1097         case PRID_COMP_SANDCRAFT:
1098                 cpu_probe_sandcraft(c, cpu);
1099                 break;
1100         case PRID_COMP_NXP:
1101                 cpu_probe_nxp(c, cpu);
1102                 break;
1103         case PRID_COMP_CAVIUM:
1104                 cpu_probe_cavium(c, cpu);
1105                 break;
1106         case PRID_COMP_INGENIC:
1107                 cpu_probe_ingenic(c, cpu);
1108                 break;
1109         case PRID_COMP_NETLOGIC:
1110                 cpu_probe_netlogic(c, cpu);
1111                 break;
1112         }
1113
1114         BUG_ON(!__cpu_name[cpu]);
1115         BUG_ON(c->cputype == CPU_UNKNOWN);
1116
1117         /*
1118          * Platform code can force the cpu type to optimize code
1119          * generation. In that case be sure the cpu type is correctly
1120          * manually setup otherwise it could trigger some nasty bugs.
1121          */
1122         BUG_ON(current_cpu_type() != c->cputype);
1123
1124         if (mips_fpu_disabled)
1125                 c->options &= ~MIPS_CPU_FPU;
1126
1127         if (mips_dsp_disabled)
1128                 c->ases &= ~MIPS_ASE_DSP;
1129
1130         if (c->options & MIPS_CPU_FPU) {
1131                 c->fpu_id = cpu_get_fpu_id();
1132
1133                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1134                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1135                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1136                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1137                         if (c->fpu_id & MIPS_FPIR_3D)
1138                                 c->ases |= MIPS_ASE_MIPS3D;
1139                 }
1140         }
1141
1142         if (cpu_has_mips_r2)
1143                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1144         else
1145                 c->srsets = 1;
1146
1147         cpu_probe_vmbits(c);
1148
1149 #ifdef CONFIG_64BIT
1150         if (cpu == 0)
1151                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1152 #endif
1153 }
1154
1155 __cpuinit void cpu_report(void)
1156 {
1157         struct cpuinfo_mips *c = &current_cpu_data;
1158
1159         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1160                c->processor_id, cpu_name_string());
1161         if (c->options & MIPS_CPU_FPU)
1162                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1163 }