MIPS: Netlogic XLR/XLS processor IDs.
[linux-2.6.git] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
29
30 /*
31  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32  * the implementation of the "wait" feature differs between CPU families. This
33  * points to the function that implements CPU specific wait.
34  * The wait instruction stops the pipeline and reduces the power consumption of
35  * the CPU very much.
36  */
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
39
40 static void r3081_wait(void)
41 {
42         unsigned long cfg = read_c0_conf();
43         write_c0_conf(cfg | R30XX_CONF_HALT);
44 }
45
46 static void r39xx_wait(void)
47 {
48         local_irq_disable();
49         if (!need_resched())
50                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51         local_irq_enable();
52 }
53
54 extern void r4k_wait(void);
55
56 /*
57  * This variant is preferable as it allows testing need_resched and going to
58  * sleep depending on the outcome atomically.  Unfortunately the "It is
59  * implementation-dependent whether the pipeline restarts when a non-enabled
60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61  * using this version a gamble.
62  */
63 void r4k_wait_irqoff(void)
64 {
65         local_irq_disable();
66         if (!need_resched())
67                 __asm__("       .set    push            \n"
68                         "       .set    mips3           \n"
69                         "       wait                    \n"
70                         "       .set    pop             \n");
71         local_irq_enable();
72         __asm__("       .globl __pastwait       \n"
73                 "__pastwait:                    \n");
74         return;
75 }
76
77 /*
78  * The RM7000 variant has to handle erratum 38.  The workaround is to not
79  * have any pending stores when the WAIT instruction is executed.
80  */
81 static void rm7k_wait_irqoff(void)
82 {
83         local_irq_disable();
84         if (!need_resched())
85                 __asm__(
86                 "       .set    push                                    \n"
87                 "       .set    mips3                                   \n"
88                 "       .set    noat                                    \n"
89                 "       mfc0    $1, $12                                 \n"
90                 "       sync                                            \n"
91                 "       mtc0    $1, $12         # stalls until W stage  \n"
92                 "       wait                                            \n"
93                 "       mtc0    $1, $12         # stalls until W stage  \n"
94                 "       .set    pop                                     \n");
95         local_irq_enable();
96 }
97
98 /*
99  * The Au1xxx wait is available only if using 32khz counter or
100  * external timer source, but specifically not CP0 Counter.
101  * alchemy/common/time.c may override cpu_wait!
102  */
103 static void au1k_wait(void)
104 {
105         __asm__("       .set    mips3                   \n"
106                 "       cache   0x14, 0(%0)             \n"
107                 "       cache   0x14, 32(%0)            \n"
108                 "       sync                            \n"
109                 "       nop                             \n"
110                 "       wait                            \n"
111                 "       nop                             \n"
112                 "       nop                             \n"
113                 "       nop                             \n"
114                 "       nop                             \n"
115                 "       .set    mips0                   \n"
116                 : : "r" (au1k_wait));
117 }
118
119 static int __initdata nowait;
120
121 static int __init wait_disable(char *s)
122 {
123         nowait = 1;
124
125         return 1;
126 }
127
128 __setup("nowait", wait_disable);
129
130 static int __cpuinitdata mips_fpu_disabled;
131
132 static int __init fpu_disable(char *s)
133 {
134         cpu_data[0].options &= ~MIPS_CPU_FPU;
135         mips_fpu_disabled = 1;
136
137         return 1;
138 }
139
140 __setup("nofpu", fpu_disable);
141
142 int __cpuinitdata mips_dsp_disabled;
143
144 static int __init dsp_disable(char *s)
145 {
146         cpu_data[0].ases &= ~MIPS_ASE_DSP;
147         mips_dsp_disabled = 1;
148
149         return 1;
150 }
151
152 __setup("nodsp", dsp_disable);
153
154 void __init check_wait(void)
155 {
156         struct cpuinfo_mips *c = &current_cpu_data;
157
158         if (nowait) {
159                 printk("Wait instruction disabled.\n");
160                 return;
161         }
162
163         switch (c->cputype) {
164         case CPU_R3081:
165         case CPU_R3081E:
166                 cpu_wait = r3081_wait;
167                 break;
168         case CPU_TX3927:
169                 cpu_wait = r39xx_wait;
170                 break;
171         case CPU_R4200:
172 /*      case CPU_R4300: */
173         case CPU_R4600:
174         case CPU_R4640:
175         case CPU_R4650:
176         case CPU_R4700:
177         case CPU_R5000:
178         case CPU_R5500:
179         case CPU_NEVADA:
180         case CPU_4KC:
181         case CPU_4KEC:
182         case CPU_4KSC:
183         case CPU_5KC:
184         case CPU_25KF:
185         case CPU_PR4450:
186         case CPU_BMIPS3300:
187         case CPU_BMIPS4350:
188         case CPU_BMIPS4380:
189         case CPU_BMIPS5000:
190         case CPU_CAVIUM_OCTEON:
191         case CPU_CAVIUM_OCTEON_PLUS:
192         case CPU_CAVIUM_OCTEON2:
193         case CPU_JZRISC:
194                 cpu_wait = r4k_wait;
195                 break;
196
197         case CPU_RM7000:
198                 cpu_wait = rm7k_wait_irqoff;
199                 break;
200
201         case CPU_24K:
202         case CPU_34K:
203         case CPU_1004K:
204                 cpu_wait = r4k_wait;
205                 if (read_c0_config7() & MIPS_CONF7_WII)
206                         cpu_wait = r4k_wait_irqoff;
207                 break;
208
209         case CPU_74K:
210                 cpu_wait = r4k_wait;
211                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
212                         cpu_wait = r4k_wait_irqoff;
213                 break;
214
215         case CPU_TX49XX:
216                 cpu_wait = r4k_wait_irqoff;
217                 break;
218         case CPU_ALCHEMY:
219                 cpu_wait = au1k_wait;
220                 break;
221         case CPU_20KC:
222                 /*
223                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
224                  * WAIT on Rev2.0 and Rev3.0 has E16.
225                  * Rev3.1 WAIT is nop, why bother
226                  */
227                 if ((c->processor_id & 0xff) <= 0x64)
228                         break;
229
230                 /*
231                  * Another rev is incremeting c0_count at a reduced clock
232                  * rate while in WAIT mode.  So we basically have the choice
233                  * between using the cp0 timer as clocksource or avoiding
234                  * the WAIT instruction.  Until more details are known,
235                  * disable the use of WAIT for 20Kc entirely.
236                    cpu_wait = r4k_wait;
237                  */
238                 break;
239         case CPU_RM9000:
240                 if ((c->processor_id & 0x00ff) >= 0x40)
241                         cpu_wait = r4k_wait;
242                 break;
243         default:
244                 break;
245         }
246 }
247
248 static inline void check_errata(void)
249 {
250         struct cpuinfo_mips *c = &current_cpu_data;
251
252         switch (c->cputype) {
253         case CPU_34K:
254                 /*
255                  * Erratum "RPS May Cause Incorrect Instruction Execution"
256                  * This code only handles VPE0, any SMP/SMTC/RTOS code
257                  * making use of VPE1 will be responsable for that VPE.
258                  */
259                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261                 break;
262         default:
263                 break;
264         }
265 }
266
267 void __init check_bugs32(void)
268 {
269         check_errata();
270 }
271
272 /*
273  * Probe whether cpu has config register by trying to play with
274  * alternate cache bit and see whether it matters.
275  * It's used by cpu_probe to distinguish between R3000A and R3081.
276  */
277 static inline int cpu_has_confreg(void)
278 {
279 #ifdef CONFIG_CPU_R3000
280         extern unsigned long r3k_cache_size(unsigned long);
281         unsigned long size1, size2;
282         unsigned long cfg = read_c0_conf();
283
284         size1 = r3k_cache_size(ST0_ISC);
285         write_c0_conf(cfg ^ R30XX_CONF_AC);
286         size2 = r3k_cache_size(ST0_ISC);
287         write_c0_conf(cfg);
288         return size1 != size2;
289 #else
290         return 0;
291 #endif
292 }
293
294 /*
295  * Get the FPU Implementation/Revision.
296  */
297 static inline unsigned long cpu_get_fpu_id(void)
298 {
299         unsigned long tmp, fpu_id;
300
301         tmp = read_c0_status();
302         __enable_fpu();
303         fpu_id = read_32bit_cp1_register(CP1_REVISION);
304         write_c0_status(tmp);
305         return fpu_id;
306 }
307
308 /*
309  * Check the CPU has an FPU the official way.
310  */
311 static inline int __cpu_has_fpu(void)
312 {
313         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
314 }
315
316 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
317 {
318 #ifdef __NEED_VMBITS_PROBE
319         write_c0_entryhi(0x3fffffffffffe000ULL);
320         back_to_back_c0_hazard();
321         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
322 #endif
323 }
324
325 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
326                 | MIPS_CPU_COUNTER)
327
328 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
329 {
330         switch (c->processor_id & 0xff00) {
331         case PRID_IMP_R2000:
332                 c->cputype = CPU_R2000;
333                 __cpu_name[cpu] = "R2000";
334                 c->isa_level = MIPS_CPU_ISA_I;
335                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
336                              MIPS_CPU_NOFPUEX;
337                 if (__cpu_has_fpu())
338                         c->options |= MIPS_CPU_FPU;
339                 c->tlbsize = 64;
340                 break;
341         case PRID_IMP_R3000:
342                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
343                         if (cpu_has_confreg()) {
344                                 c->cputype = CPU_R3081E;
345                                 __cpu_name[cpu] = "R3081";
346                         } else {
347                                 c->cputype = CPU_R3000A;
348                                 __cpu_name[cpu] = "R3000A";
349                         }
350                         break;
351                 } else {
352                         c->cputype = CPU_R3000;
353                         __cpu_name[cpu] = "R3000";
354                 }
355                 c->isa_level = MIPS_CPU_ISA_I;
356                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
357                              MIPS_CPU_NOFPUEX;
358                 if (__cpu_has_fpu())
359                         c->options |= MIPS_CPU_FPU;
360                 c->tlbsize = 64;
361                 break;
362         case PRID_IMP_R4000:
363                 if (read_c0_config() & CONF_SC) {
364                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
365                                 c->cputype = CPU_R4400PC;
366                                 __cpu_name[cpu] = "R4400PC";
367                         } else {
368                                 c->cputype = CPU_R4000PC;
369                                 __cpu_name[cpu] = "R4000PC";
370                         }
371                 } else {
372                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
373                                 c->cputype = CPU_R4400SC;
374                                 __cpu_name[cpu] = "R4400SC";
375                         } else {
376                                 c->cputype = CPU_R4000SC;
377                                 __cpu_name[cpu] = "R4000SC";
378                         }
379                 }
380
381                 c->isa_level = MIPS_CPU_ISA_III;
382                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
383                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
384                              MIPS_CPU_LLSC;
385                 c->tlbsize = 48;
386                 break;
387         case PRID_IMP_VR41XX:
388                 switch (c->processor_id & 0xf0) {
389                 case PRID_REV_VR4111:
390                         c->cputype = CPU_VR4111;
391                         __cpu_name[cpu] = "NEC VR4111";
392                         break;
393                 case PRID_REV_VR4121:
394                         c->cputype = CPU_VR4121;
395                         __cpu_name[cpu] = "NEC VR4121";
396                         break;
397                 case PRID_REV_VR4122:
398                         if ((c->processor_id & 0xf) < 0x3) {
399                                 c->cputype = CPU_VR4122;
400                                 __cpu_name[cpu] = "NEC VR4122";
401                         } else {
402                                 c->cputype = CPU_VR4181A;
403                                 __cpu_name[cpu] = "NEC VR4181A";
404                         }
405                         break;
406                 case PRID_REV_VR4130:
407                         if ((c->processor_id & 0xf) < 0x4) {
408                                 c->cputype = CPU_VR4131;
409                                 __cpu_name[cpu] = "NEC VR4131";
410                         } else {
411                                 c->cputype = CPU_VR4133;
412                                 __cpu_name[cpu] = "NEC VR4133";
413                         }
414                         break;
415                 default:
416                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
417                         c->cputype = CPU_VR41XX;
418                         __cpu_name[cpu] = "NEC Vr41xx";
419                         break;
420                 }
421                 c->isa_level = MIPS_CPU_ISA_III;
422                 c->options = R4K_OPTS;
423                 c->tlbsize = 32;
424                 break;
425         case PRID_IMP_R4300:
426                 c->cputype = CPU_R4300;
427                 __cpu_name[cpu] = "R4300";
428                 c->isa_level = MIPS_CPU_ISA_III;
429                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
430                              MIPS_CPU_LLSC;
431                 c->tlbsize = 32;
432                 break;
433         case PRID_IMP_R4600:
434                 c->cputype = CPU_R4600;
435                 __cpu_name[cpu] = "R4600";
436                 c->isa_level = MIPS_CPU_ISA_III;
437                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
438                              MIPS_CPU_LLSC;
439                 c->tlbsize = 48;
440                 break;
441         #if 0
442         case PRID_IMP_R4650:
443                 /*
444                  * This processor doesn't have an MMU, so it's not
445                  * "real easy" to run Linux on it. It is left purely
446                  * for documentation.  Commented out because it shares
447                  * it's c0_prid id number with the TX3900.
448                  */
449                 c->cputype = CPU_R4650;
450                 __cpu_name[cpu] = "R4650";
451                 c->isa_level = MIPS_CPU_ISA_III;
452                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
453                 c->tlbsize = 48;
454                 break;
455         #endif
456         case PRID_IMP_TX39:
457                 c->isa_level = MIPS_CPU_ISA_I;
458                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
459
460                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
461                         c->cputype = CPU_TX3927;
462                         __cpu_name[cpu] = "TX3927";
463                         c->tlbsize = 64;
464                 } else {
465                         switch (c->processor_id & 0xff) {
466                         case PRID_REV_TX3912:
467                                 c->cputype = CPU_TX3912;
468                                 __cpu_name[cpu] = "TX3912";
469                                 c->tlbsize = 32;
470                                 break;
471                         case PRID_REV_TX3922:
472                                 c->cputype = CPU_TX3922;
473                                 __cpu_name[cpu] = "TX3922";
474                                 c->tlbsize = 64;
475                                 break;
476                         }
477                 }
478                 break;
479         case PRID_IMP_R4700:
480                 c->cputype = CPU_R4700;
481                 __cpu_name[cpu] = "R4700";
482                 c->isa_level = MIPS_CPU_ISA_III;
483                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
484                              MIPS_CPU_LLSC;
485                 c->tlbsize = 48;
486                 break;
487         case PRID_IMP_TX49:
488                 c->cputype = CPU_TX49XX;
489                 __cpu_name[cpu] = "R49XX";
490                 c->isa_level = MIPS_CPU_ISA_III;
491                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
492                 if (!(c->processor_id & 0x08))
493                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
494                 c->tlbsize = 48;
495                 break;
496         case PRID_IMP_R5000:
497                 c->cputype = CPU_R5000;
498                 __cpu_name[cpu] = "R5000";
499                 c->isa_level = MIPS_CPU_ISA_IV;
500                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
501                              MIPS_CPU_LLSC;
502                 c->tlbsize = 48;
503                 break;
504         case PRID_IMP_R5432:
505                 c->cputype = CPU_R5432;
506                 __cpu_name[cpu] = "R5432";
507                 c->isa_level = MIPS_CPU_ISA_IV;
508                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
509                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
510                 c->tlbsize = 48;
511                 break;
512         case PRID_IMP_R5500:
513                 c->cputype = CPU_R5500;
514                 __cpu_name[cpu] = "R5500";
515                 c->isa_level = MIPS_CPU_ISA_IV;
516                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
517                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
518                 c->tlbsize = 48;
519                 break;
520         case PRID_IMP_NEVADA:
521                 c->cputype = CPU_NEVADA;
522                 __cpu_name[cpu] = "Nevada";
523                 c->isa_level = MIPS_CPU_ISA_IV;
524                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
525                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
526                 c->tlbsize = 48;
527                 break;
528         case PRID_IMP_R6000:
529                 c->cputype = CPU_R6000;
530                 __cpu_name[cpu] = "R6000";
531                 c->isa_level = MIPS_CPU_ISA_II;
532                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
533                              MIPS_CPU_LLSC;
534                 c->tlbsize = 32;
535                 break;
536         case PRID_IMP_R6000A:
537                 c->cputype = CPU_R6000A;
538                 __cpu_name[cpu] = "R6000A";
539                 c->isa_level = MIPS_CPU_ISA_II;
540                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
541                              MIPS_CPU_LLSC;
542                 c->tlbsize = 32;
543                 break;
544         case PRID_IMP_RM7000:
545                 c->cputype = CPU_RM7000;
546                 __cpu_name[cpu] = "RM7000";
547                 c->isa_level = MIPS_CPU_ISA_IV;
548                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
549                              MIPS_CPU_LLSC;
550                 /*
551                  * Undocumented RM7000:  Bit 29 in the info register of
552                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
553                  * entries.
554                  *
555                  * 29      1 =>    64 entry JTLB
556                  *         0 =>    48 entry JTLB
557                  */
558                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
559                 break;
560         case PRID_IMP_RM9000:
561                 c->cputype = CPU_RM9000;
562                 __cpu_name[cpu] = "RM9000";
563                 c->isa_level = MIPS_CPU_ISA_IV;
564                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
565                              MIPS_CPU_LLSC;
566                 /*
567                  * Bit 29 in the info register of the RM9000
568                  * indicates if the TLB has 48 or 64 entries.
569                  *
570                  * 29      1 =>    64 entry JTLB
571                  *         0 =>    48 entry JTLB
572                  */
573                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
574                 break;
575         case PRID_IMP_R8000:
576                 c->cputype = CPU_R8000;
577                 __cpu_name[cpu] = "RM8000";
578                 c->isa_level = MIPS_CPU_ISA_IV;
579                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
580                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
581                              MIPS_CPU_LLSC;
582                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
583                 break;
584         case PRID_IMP_R10000:
585                 c->cputype = CPU_R10000;
586                 __cpu_name[cpu] = "R10000";
587                 c->isa_level = MIPS_CPU_ISA_IV;
588                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
589                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
590                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
591                              MIPS_CPU_LLSC;
592                 c->tlbsize = 64;
593                 break;
594         case PRID_IMP_R12000:
595                 c->cputype = CPU_R12000;
596                 __cpu_name[cpu] = "R12000";
597                 c->isa_level = MIPS_CPU_ISA_IV;
598                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
599                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
600                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
601                              MIPS_CPU_LLSC;
602                 c->tlbsize = 64;
603                 break;
604         case PRID_IMP_R14000:
605                 c->cputype = CPU_R14000;
606                 __cpu_name[cpu] = "R14000";
607                 c->isa_level = MIPS_CPU_ISA_IV;
608                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
609                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
610                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
611                              MIPS_CPU_LLSC;
612                 c->tlbsize = 64;
613                 break;
614         case PRID_IMP_LOONGSON2:
615                 c->cputype = CPU_LOONGSON2;
616                 __cpu_name[cpu] = "ICT Loongson-2";
617                 c->isa_level = MIPS_CPU_ISA_III;
618                 c->options = R4K_OPTS |
619                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
620                              MIPS_CPU_32FPR;
621                 c->tlbsize = 64;
622                 break;
623         }
624 }
625
626 static char unknown_isa[] __cpuinitdata = KERN_ERR \
627         "Unsupported ISA type, c0.config0: %d.";
628
629 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
630 {
631         unsigned int config0;
632         int isa;
633
634         config0 = read_c0_config();
635
636         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
637                 c->options |= MIPS_CPU_TLB;
638         isa = (config0 & MIPS_CONF_AT) >> 13;
639         switch (isa) {
640         case 0:
641                 switch ((config0 & MIPS_CONF_AR) >> 10) {
642                 case 0:
643                         c->isa_level = MIPS_CPU_ISA_M32R1;
644                         break;
645                 case 1:
646                         c->isa_level = MIPS_CPU_ISA_M32R2;
647                         break;
648                 default:
649                         goto unknown;
650                 }
651                 break;
652         case 2:
653                 switch ((config0 & MIPS_CONF_AR) >> 10) {
654                 case 0:
655                         c->isa_level = MIPS_CPU_ISA_M64R1;
656                         break;
657                 case 1:
658                         c->isa_level = MIPS_CPU_ISA_M64R2;
659                         break;
660                 default:
661                         goto unknown;
662                 }
663                 break;
664         default:
665                 goto unknown;
666         }
667
668         return config0 & MIPS_CONF_M;
669
670 unknown:
671         panic(unknown_isa, config0);
672 }
673
674 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
675 {
676         unsigned int config1;
677
678         config1 = read_c0_config1();
679
680         if (config1 & MIPS_CONF1_MD)
681                 c->ases |= MIPS_ASE_MDMX;
682         if (config1 & MIPS_CONF1_WR)
683                 c->options |= MIPS_CPU_WATCH;
684         if (config1 & MIPS_CONF1_CA)
685                 c->ases |= MIPS_ASE_MIPS16;
686         if (config1 & MIPS_CONF1_EP)
687                 c->options |= MIPS_CPU_EJTAG;
688         if (config1 & MIPS_CONF1_FP) {
689                 c->options |= MIPS_CPU_FPU;
690                 c->options |= MIPS_CPU_32FPR;
691         }
692         if (cpu_has_tlb)
693                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
694
695         return config1 & MIPS_CONF_M;
696 }
697
698 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
699 {
700         unsigned int config2;
701
702         config2 = read_c0_config2();
703
704         if (config2 & MIPS_CONF2_SL)
705                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
706
707         return config2 & MIPS_CONF_M;
708 }
709
710 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
711 {
712         unsigned int config3;
713
714         config3 = read_c0_config3();
715
716         if (config3 & MIPS_CONF3_SM)
717                 c->ases |= MIPS_ASE_SMARTMIPS;
718         if (config3 & MIPS_CONF3_DSP)
719                 c->ases |= MIPS_ASE_DSP;
720         if (config3 & MIPS_CONF3_VINT)
721                 c->options |= MIPS_CPU_VINT;
722         if (config3 & MIPS_CONF3_VEIC)
723                 c->options |= MIPS_CPU_VEIC;
724         if (config3 & MIPS_CONF3_MT)
725                 c->ases |= MIPS_ASE_MIPSMT;
726         if (config3 & MIPS_CONF3_ULRI)
727                 c->options |= MIPS_CPU_ULRI;
728
729         return config3 & MIPS_CONF_M;
730 }
731
732 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
733 {
734         unsigned int config4;
735
736         config4 = read_c0_config4();
737
738         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
739             && cpu_has_tlb)
740                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
741
742         c->kscratch_mask = (config4 >> 16) & 0xff;
743
744         return config4 & MIPS_CONF_M;
745 }
746
747 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
748 {
749         int ok;
750
751         /* MIPS32 or MIPS64 compliant CPU.  */
752         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
753                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
754
755         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
756
757         ok = decode_config0(c);                 /* Read Config registers.  */
758         BUG_ON(!ok);                            /* Arch spec violation!  */
759         if (ok)
760                 ok = decode_config1(c);
761         if (ok)
762                 ok = decode_config2(c);
763         if (ok)
764                 ok = decode_config3(c);
765         if (ok)
766                 ok = decode_config4(c);
767
768         mips_probe_watch_registers(c);
769
770         if (cpu_has_mips_r2)
771                 c->core = read_c0_ebase() & 0x3ff;
772 }
773
774 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
775 {
776         decode_configs(c);
777         switch (c->processor_id & 0xff00) {
778         case PRID_IMP_4KC:
779                 c->cputype = CPU_4KC;
780                 __cpu_name[cpu] = "MIPS 4Kc";
781                 break;
782         case PRID_IMP_4KEC:
783         case PRID_IMP_4KECR2:
784                 c->cputype = CPU_4KEC;
785                 __cpu_name[cpu] = "MIPS 4KEc";
786                 break;
787         case PRID_IMP_4KSC:
788         case PRID_IMP_4KSD:
789                 c->cputype = CPU_4KSC;
790                 __cpu_name[cpu] = "MIPS 4KSc";
791                 break;
792         case PRID_IMP_5KC:
793                 c->cputype = CPU_5KC;
794                 __cpu_name[cpu] = "MIPS 5Kc";
795                 break;
796         case PRID_IMP_20KC:
797                 c->cputype = CPU_20KC;
798                 __cpu_name[cpu] = "MIPS 20Kc";
799                 break;
800         case PRID_IMP_24K:
801         case PRID_IMP_24KE:
802                 c->cputype = CPU_24K;
803                 __cpu_name[cpu] = "MIPS 24Kc";
804                 break;
805         case PRID_IMP_25KF:
806                 c->cputype = CPU_25KF;
807                 __cpu_name[cpu] = "MIPS 25Kc";
808                 break;
809         case PRID_IMP_34K:
810                 c->cputype = CPU_34K;
811                 __cpu_name[cpu] = "MIPS 34Kc";
812                 break;
813         case PRID_IMP_74K:
814                 c->cputype = CPU_74K;
815                 __cpu_name[cpu] = "MIPS 74Kc";
816                 break;
817         case PRID_IMP_1004K:
818                 c->cputype = CPU_1004K;
819                 __cpu_name[cpu] = "MIPS 1004Kc";
820                 break;
821         }
822
823         spram_config();
824 }
825
826 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
827 {
828         decode_configs(c);
829         switch (c->processor_id & 0xff00) {
830         case PRID_IMP_AU1_REV1:
831         case PRID_IMP_AU1_REV2:
832                 c->cputype = CPU_ALCHEMY;
833                 switch ((c->processor_id >> 24) & 0xff) {
834                 case 0:
835                         __cpu_name[cpu] = "Au1000";
836                         break;
837                 case 1:
838                         __cpu_name[cpu] = "Au1500";
839                         break;
840                 case 2:
841                         __cpu_name[cpu] = "Au1100";
842                         break;
843                 case 3:
844                         __cpu_name[cpu] = "Au1550";
845                         break;
846                 case 4:
847                         __cpu_name[cpu] = "Au1200";
848                         if ((c->processor_id & 0xff) == 2)
849                                 __cpu_name[cpu] = "Au1250";
850                         break;
851                 case 5:
852                         __cpu_name[cpu] = "Au1210";
853                         break;
854                 default:
855                         __cpu_name[cpu] = "Au1xxx";
856                         break;
857                 }
858                 break;
859         }
860 }
861
862 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
863 {
864         decode_configs(c);
865
866         switch (c->processor_id & 0xff00) {
867         case PRID_IMP_SB1:
868                 c->cputype = CPU_SB1;
869                 __cpu_name[cpu] = "SiByte SB1";
870                 /* FPU in pass1 is known to have issues. */
871                 if ((c->processor_id & 0xff) < 0x02)
872                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
873                 break;
874         case PRID_IMP_SB1A:
875                 c->cputype = CPU_SB1A;
876                 __cpu_name[cpu] = "SiByte SB1A";
877                 break;
878         }
879 }
880
881 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
882 {
883         decode_configs(c);
884         switch (c->processor_id & 0xff00) {
885         case PRID_IMP_SR71000:
886                 c->cputype = CPU_SR71000;
887                 __cpu_name[cpu] = "Sandcraft SR71000";
888                 c->scache.ways = 8;
889                 c->tlbsize = 64;
890                 break;
891         }
892 }
893
894 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
895 {
896         decode_configs(c);
897         switch (c->processor_id & 0xff00) {
898         case PRID_IMP_PR4450:
899                 c->cputype = CPU_PR4450;
900                 __cpu_name[cpu] = "Philips PR4450";
901                 c->isa_level = MIPS_CPU_ISA_M32R1;
902                 break;
903         }
904 }
905
906 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
907 {
908         decode_configs(c);
909         switch (c->processor_id & 0xff00) {
910         case PRID_IMP_BMIPS32_REV4:
911         case PRID_IMP_BMIPS32_REV8:
912                 c->cputype = CPU_BMIPS32;
913                 __cpu_name[cpu] = "Broadcom BMIPS32";
914                 break;
915         case PRID_IMP_BMIPS3300:
916         case PRID_IMP_BMIPS3300_ALT:
917         case PRID_IMP_BMIPS3300_BUG:
918                 c->cputype = CPU_BMIPS3300;
919                 __cpu_name[cpu] = "Broadcom BMIPS3300";
920                 break;
921         case PRID_IMP_BMIPS43XX: {
922                 int rev = c->processor_id & 0xff;
923
924                 if (rev >= PRID_REV_BMIPS4380_LO &&
925                                 rev <= PRID_REV_BMIPS4380_HI) {
926                         c->cputype = CPU_BMIPS4380;
927                         __cpu_name[cpu] = "Broadcom BMIPS4380";
928                 } else {
929                         c->cputype = CPU_BMIPS4350;
930                         __cpu_name[cpu] = "Broadcom BMIPS4350";
931                 }
932                 break;
933         }
934         case PRID_IMP_BMIPS5000:
935                 c->cputype = CPU_BMIPS5000;
936                 __cpu_name[cpu] = "Broadcom BMIPS5000";
937                 c->options |= MIPS_CPU_ULRI;
938                 break;
939         }
940 }
941
942 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
943 {
944         decode_configs(c);
945         switch (c->processor_id & 0xff00) {
946         case PRID_IMP_CAVIUM_CN38XX:
947         case PRID_IMP_CAVIUM_CN31XX:
948         case PRID_IMP_CAVIUM_CN30XX:
949                 c->cputype = CPU_CAVIUM_OCTEON;
950                 __cpu_name[cpu] = "Cavium Octeon";
951                 goto platform;
952         case PRID_IMP_CAVIUM_CN58XX:
953         case PRID_IMP_CAVIUM_CN56XX:
954         case PRID_IMP_CAVIUM_CN50XX:
955         case PRID_IMP_CAVIUM_CN52XX:
956                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
957                 __cpu_name[cpu] = "Cavium Octeon+";
958 platform:
959                 if (cpu == 0)
960                         __elf_platform = "octeon";
961                 break;
962         case PRID_IMP_CAVIUM_CN63XX:
963                 c->cputype = CPU_CAVIUM_OCTEON2;
964                 __cpu_name[cpu] = "Cavium Octeon II";
965                 if (cpu == 0)
966                         __elf_platform = "octeon2";
967                 break;
968         default:
969                 printk(KERN_INFO "Unknown Octeon chip!\n");
970                 c->cputype = CPU_UNKNOWN;
971                 break;
972         }
973 }
974
975 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
976 {
977         decode_configs(c);
978         /* JZRISC does not implement the CP0 counter. */
979         c->options &= ~MIPS_CPU_COUNTER;
980         switch (c->processor_id & 0xff00) {
981         case PRID_IMP_JZRISC:
982                 c->cputype = CPU_JZRISC;
983                 __cpu_name[cpu] = "Ingenic JZRISC";
984                 break;
985         default:
986                 panic("Unknown Ingenic Processor ID!");
987                 break;
988         }
989 }
990
991 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
992 {
993         decode_configs(c);
994
995         c->options = (MIPS_CPU_TLB       |
996                         MIPS_CPU_4KEX    |
997                         MIPS_CPU_COUNTER |
998                         MIPS_CPU_DIVEC   |
999                         MIPS_CPU_WATCH   |
1000                         MIPS_CPU_EJTAG   |
1001                         MIPS_CPU_LLSC);
1002
1003         switch (c->processor_id & 0xff00) {
1004         case PRID_IMP_NETLOGIC_XLR732:
1005         case PRID_IMP_NETLOGIC_XLR716:
1006         case PRID_IMP_NETLOGIC_XLR532:
1007         case PRID_IMP_NETLOGIC_XLR308:
1008         case PRID_IMP_NETLOGIC_XLR532C:
1009         case PRID_IMP_NETLOGIC_XLR516C:
1010         case PRID_IMP_NETLOGIC_XLR508C:
1011         case PRID_IMP_NETLOGIC_XLR308C:
1012                 c->cputype = CPU_XLR;
1013                 __cpu_name[cpu] = "Netlogic XLR";
1014                 break;
1015
1016         case PRID_IMP_NETLOGIC_XLS608:
1017         case PRID_IMP_NETLOGIC_XLS408:
1018         case PRID_IMP_NETLOGIC_XLS404:
1019         case PRID_IMP_NETLOGIC_XLS208:
1020         case PRID_IMP_NETLOGIC_XLS204:
1021         case PRID_IMP_NETLOGIC_XLS108:
1022         case PRID_IMP_NETLOGIC_XLS104:
1023         case PRID_IMP_NETLOGIC_XLS616B:
1024         case PRID_IMP_NETLOGIC_XLS608B:
1025         case PRID_IMP_NETLOGIC_XLS416B:
1026         case PRID_IMP_NETLOGIC_XLS412B:
1027         case PRID_IMP_NETLOGIC_XLS408B:
1028         case PRID_IMP_NETLOGIC_XLS404B:
1029                 c->cputype = CPU_XLR;
1030                 __cpu_name[cpu] = "Netlogic XLS";
1031                 break;
1032
1033         default:
1034                 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1035                        c->processor_id);
1036                 c->cputype = CPU_XLR;
1037                 break;
1038         }
1039
1040         c->isa_level = MIPS_CPU_ISA_M64R1;
1041         c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1042 }
1043
1044 #ifdef CONFIG_64BIT
1045 /* For use by uaccess.h */
1046 u64 __ua_limit;
1047 EXPORT_SYMBOL(__ua_limit);
1048 #endif
1049
1050 const char *__cpu_name[NR_CPUS];
1051 const char *__elf_platform;
1052
1053 __cpuinit void cpu_probe(void)
1054 {
1055         struct cpuinfo_mips *c = &current_cpu_data;
1056         unsigned int cpu = smp_processor_id();
1057
1058         c->processor_id = PRID_IMP_UNKNOWN;
1059         c->fpu_id       = FPIR_IMP_NONE;
1060         c->cputype      = CPU_UNKNOWN;
1061
1062         c->processor_id = read_c0_prid();
1063         switch (c->processor_id & 0xff0000) {
1064         case PRID_COMP_LEGACY:
1065                 cpu_probe_legacy(c, cpu);
1066                 break;
1067         case PRID_COMP_MIPS:
1068                 cpu_probe_mips(c, cpu);
1069                 break;
1070         case PRID_COMP_ALCHEMY:
1071                 cpu_probe_alchemy(c, cpu);
1072                 break;
1073         case PRID_COMP_SIBYTE:
1074                 cpu_probe_sibyte(c, cpu);
1075                 break;
1076         case PRID_COMP_BROADCOM:
1077                 cpu_probe_broadcom(c, cpu);
1078                 break;
1079         case PRID_COMP_SANDCRAFT:
1080                 cpu_probe_sandcraft(c, cpu);
1081                 break;
1082         case PRID_COMP_NXP:
1083                 cpu_probe_nxp(c, cpu);
1084                 break;
1085         case PRID_COMP_CAVIUM:
1086                 cpu_probe_cavium(c, cpu);
1087                 break;
1088         case PRID_COMP_INGENIC:
1089                 cpu_probe_ingenic(c, cpu);
1090                 break;
1091         case PRID_COMP_NETLOGIC:
1092                 cpu_probe_netlogic(c, cpu);
1093                 break;
1094         }
1095
1096         BUG_ON(!__cpu_name[cpu]);
1097         BUG_ON(c->cputype == CPU_UNKNOWN);
1098
1099         /*
1100          * Platform code can force the cpu type to optimize code
1101          * generation. In that case be sure the cpu type is correctly
1102          * manually setup otherwise it could trigger some nasty bugs.
1103          */
1104         BUG_ON(current_cpu_type() != c->cputype);
1105
1106         if (mips_fpu_disabled)
1107                 c->options &= ~MIPS_CPU_FPU;
1108
1109         if (mips_dsp_disabled)
1110                 c->ases &= ~MIPS_ASE_DSP;
1111
1112         if (c->options & MIPS_CPU_FPU) {
1113                 c->fpu_id = cpu_get_fpu_id();
1114
1115                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1116                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1117                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1118                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1119                         if (c->fpu_id & MIPS_FPIR_3D)
1120                                 c->ases |= MIPS_ASE_MIPS3D;
1121                 }
1122         }
1123
1124         if (cpu_has_mips_r2)
1125                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1126         else
1127                 c->srsets = 1;
1128
1129         cpu_probe_vmbits(c);
1130
1131 #ifdef CONFIG_64BIT
1132         if (cpu == 0)
1133                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1134 #endif
1135 }
1136
1137 __cpuinit void cpu_report(void)
1138 {
1139         struct cpuinfo_mips *c = &current_cpu_data;
1140
1141         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1142                c->processor_id, cpu_name_string());
1143         if (c->options & MIPS_CPU_FPU)
1144                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1145 }