758ad426c57fedb3f71c8f6ae24544323817670e
[linux-2.6.git] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
28 /*
29  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
30  * the implementation of the "wait" feature differs between CPU families. This
31  * points to the function that implements CPU specific wait.
32  * The wait instruction stops the pipeline and reduces the power consumption of
33  * the CPU very much.
34  */
35 void (*cpu_wait)(void);
36 EXPORT_SYMBOL(cpu_wait);
37
38 static void r3081_wait(void)
39 {
40         unsigned long cfg = read_c0_conf();
41         write_c0_conf(cfg | R30XX_CONF_HALT);
42 }
43
44 static void r39xx_wait(void)
45 {
46         local_irq_disable();
47         if (!need_resched())
48                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
49         local_irq_enable();
50 }
51
52 extern void r4k_wait(void);
53
54 /*
55  * This variant is preferable as it allows testing need_resched and going to
56  * sleep depending on the outcome atomically.  Unfortunately the "It is
57  * implementation-dependent whether the pipeline restarts when a non-enabled
58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59  * using this version a gamble.
60  */
61 void r4k_wait_irqoff(void)
62 {
63         local_irq_disable();
64         if (!need_resched())
65                 __asm__("       .set    push            \n"
66                         "       .set    mips3           \n"
67                         "       wait                    \n"
68                         "       .set    pop             \n");
69         local_irq_enable();
70         __asm__("       .globl __pastwait       \n"
71                 "__pastwait:                    \n");
72         return;
73 }
74
75 /*
76  * The RM7000 variant has to handle erratum 38.  The workaround is to not
77  * have any pending stores when the WAIT instruction is executed.
78  */
79 static void rm7k_wait_irqoff(void)
80 {
81         local_irq_disable();
82         if (!need_resched())
83                 __asm__(
84                 "       .set    push                                    \n"
85                 "       .set    mips3                                   \n"
86                 "       .set    noat                                    \n"
87                 "       mfc0    $1, $12                                 \n"
88                 "       sync                                            \n"
89                 "       mtc0    $1, $12         # stalls until W stage  \n"
90                 "       wait                                            \n"
91                 "       mtc0    $1, $12         # stalls until W stage  \n"
92                 "       .set    pop                                     \n");
93         local_irq_enable();
94 }
95
96 /*
97  * The Au1xxx wait is available only if using 32khz counter or
98  * external timer source, but specifically not CP0 Counter.
99  * alchemy/common/time.c may override cpu_wait!
100  */
101 static void au1k_wait(void)
102 {
103         __asm__("       .set    mips3                   \n"
104                 "       cache   0x14, 0(%0)             \n"
105                 "       cache   0x14, 32(%0)            \n"
106                 "       sync                            \n"
107                 "       nop                             \n"
108                 "       wait                            \n"
109                 "       nop                             \n"
110                 "       nop                             \n"
111                 "       nop                             \n"
112                 "       nop                             \n"
113                 "       .set    mips0                   \n"
114                 : : "r" (au1k_wait));
115 }
116
117 static int __initdata nowait;
118
119 static int __init wait_disable(char *s)
120 {
121         nowait = 1;
122
123         return 1;
124 }
125
126 __setup("nowait", wait_disable);
127
128 void __init check_wait(void)
129 {
130         struct cpuinfo_mips *c = &current_cpu_data;
131
132         if (nowait) {
133                 printk("Wait instruction disabled.\n");
134                 return;
135         }
136
137         switch (c->cputype) {
138         case CPU_R3081:
139         case CPU_R3081E:
140                 cpu_wait = r3081_wait;
141                 break;
142         case CPU_TX3927:
143                 cpu_wait = r39xx_wait;
144                 break;
145         case CPU_R4200:
146 /*      case CPU_R4300: */
147         case CPU_R4600:
148         case CPU_R4640:
149         case CPU_R4650:
150         case CPU_R4700:
151         case CPU_R5000:
152         case CPU_R5500:
153         case CPU_NEVADA:
154         case CPU_4KC:
155         case CPU_4KEC:
156         case CPU_4KSC:
157         case CPU_5KC:
158         case CPU_25KF:
159         case CPU_PR4450:
160         case CPU_BCM3302:
161         case CPU_BCM6338:
162         case CPU_BCM6348:
163         case CPU_BCM6358:
164         case CPU_CAVIUM_OCTEON:
165                 cpu_wait = r4k_wait;
166                 break;
167
168         case CPU_RM7000:
169                 cpu_wait = rm7k_wait_irqoff;
170                 break;
171
172         case CPU_24K:
173         case CPU_34K:
174         case CPU_1004K:
175                 cpu_wait = r4k_wait;
176                 if (read_c0_config7() & MIPS_CONF7_WII)
177                         cpu_wait = r4k_wait_irqoff;
178                 break;
179
180         case CPU_74K:
181                 cpu_wait = r4k_wait;
182                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
183                         cpu_wait = r4k_wait_irqoff;
184                 break;
185
186         case CPU_TX49XX:
187                 cpu_wait = r4k_wait_irqoff;
188                 break;
189         case CPU_ALCHEMY:
190                 cpu_wait = au1k_wait;
191                 break;
192         case CPU_20KC:
193                 /*
194                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
195                  * WAIT on Rev2.0 and Rev3.0 has E16.
196                  * Rev3.1 WAIT is nop, why bother
197                  */
198                 if ((c->processor_id & 0xff) <= 0x64)
199                         break;
200
201                 /*
202                  * Another rev is incremeting c0_count at a reduced clock
203                  * rate while in WAIT mode.  So we basically have the choice
204                  * between using the cp0 timer as clocksource or avoiding
205                  * the WAIT instruction.  Until more details are known,
206                  * disable the use of WAIT for 20Kc entirely.
207                    cpu_wait = r4k_wait;
208                  */
209                 break;
210         case CPU_RM9000:
211                 if ((c->processor_id & 0x00ff) >= 0x40)
212                         cpu_wait = r4k_wait;
213                 break;
214         default:
215                 break;
216         }
217 }
218
219 static inline void check_errata(void)
220 {
221         struct cpuinfo_mips *c = &current_cpu_data;
222
223         switch (c->cputype) {
224         case CPU_34K:
225                 /*
226                  * Erratum "RPS May Cause Incorrect Instruction Execution"
227                  * This code only handles VPE0, any SMP/SMTC/RTOS code
228                  * making use of VPE1 will be responsable for that VPE.
229                  */
230                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
231                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
232                 break;
233         default:
234                 break;
235         }
236 }
237
238 void __init check_bugs32(void)
239 {
240         check_errata();
241 }
242
243 /*
244  * Probe whether cpu has config register by trying to play with
245  * alternate cache bit and see whether it matters.
246  * It's used by cpu_probe to distinguish between R3000A and R3081.
247  */
248 static inline int cpu_has_confreg(void)
249 {
250 #ifdef CONFIG_CPU_R3000
251         extern unsigned long r3k_cache_size(unsigned long);
252         unsigned long size1, size2;
253         unsigned long cfg = read_c0_conf();
254
255         size1 = r3k_cache_size(ST0_ISC);
256         write_c0_conf(cfg ^ R30XX_CONF_AC);
257         size2 = r3k_cache_size(ST0_ISC);
258         write_c0_conf(cfg);
259         return size1 != size2;
260 #else
261         return 0;
262 #endif
263 }
264
265 /*
266  * Get the FPU Implementation/Revision.
267  */
268 static inline unsigned long cpu_get_fpu_id(void)
269 {
270         unsigned long tmp, fpu_id;
271
272         tmp = read_c0_status();
273         __enable_fpu();
274         fpu_id = read_32bit_cp1_register(CP1_REVISION);
275         write_c0_status(tmp);
276         return fpu_id;
277 }
278
279 /*
280  * Check the CPU has an FPU the official way.
281  */
282 static inline int __cpu_has_fpu(void)
283 {
284         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
285 }
286
287 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
288 {
289 #ifdef __NEED_VMBITS_PROBE
290         write_c0_entryhi(0x3fffffffffffe000ULL);
291         back_to_back_c0_hazard();
292         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
293 #endif
294 }
295
296 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
297                 | MIPS_CPU_COUNTER)
298
299 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
300 {
301         switch (c->processor_id & 0xff00) {
302         case PRID_IMP_R2000:
303                 c->cputype = CPU_R2000;
304                 __cpu_name[cpu] = "R2000";
305                 c->isa_level = MIPS_CPU_ISA_I;
306                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
307                              MIPS_CPU_NOFPUEX;
308                 if (__cpu_has_fpu())
309                         c->options |= MIPS_CPU_FPU;
310                 c->tlbsize = 64;
311                 break;
312         case PRID_IMP_R3000:
313                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
314                         if (cpu_has_confreg()) {
315                                 c->cputype = CPU_R3081E;
316                                 __cpu_name[cpu] = "R3081";
317                         } else {
318                                 c->cputype = CPU_R3000A;
319                                 __cpu_name[cpu] = "R3000A";
320                         }
321                         break;
322                 } else {
323                         c->cputype = CPU_R3000;
324                         __cpu_name[cpu] = "R3000";
325                 }
326                 c->isa_level = MIPS_CPU_ISA_I;
327                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
328                              MIPS_CPU_NOFPUEX;
329                 if (__cpu_has_fpu())
330                         c->options |= MIPS_CPU_FPU;
331                 c->tlbsize = 64;
332                 break;
333         case PRID_IMP_R4000:
334                 if (read_c0_config() & CONF_SC) {
335                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
336                                 c->cputype = CPU_R4400PC;
337                                 __cpu_name[cpu] = "R4400PC";
338                         } else {
339                                 c->cputype = CPU_R4000PC;
340                                 __cpu_name[cpu] = "R4000PC";
341                         }
342                 } else {
343                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
344                                 c->cputype = CPU_R4400SC;
345                                 __cpu_name[cpu] = "R4400SC";
346                         } else {
347                                 c->cputype = CPU_R4000SC;
348                                 __cpu_name[cpu] = "R4000SC";
349                         }
350                 }
351
352                 c->isa_level = MIPS_CPU_ISA_III;
353                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
354                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
355                              MIPS_CPU_LLSC;
356                 c->tlbsize = 48;
357                 break;
358         case PRID_IMP_VR41XX:
359                 switch (c->processor_id & 0xf0) {
360                 case PRID_REV_VR4111:
361                         c->cputype = CPU_VR4111;
362                         __cpu_name[cpu] = "NEC VR4111";
363                         break;
364                 case PRID_REV_VR4121:
365                         c->cputype = CPU_VR4121;
366                         __cpu_name[cpu] = "NEC VR4121";
367                         break;
368                 case PRID_REV_VR4122:
369                         if ((c->processor_id & 0xf) < 0x3) {
370                                 c->cputype = CPU_VR4122;
371                                 __cpu_name[cpu] = "NEC VR4122";
372                         } else {
373                                 c->cputype = CPU_VR4181A;
374                                 __cpu_name[cpu] = "NEC VR4181A";
375                         }
376                         break;
377                 case PRID_REV_VR4130:
378                         if ((c->processor_id & 0xf) < 0x4) {
379                                 c->cputype = CPU_VR4131;
380                                 __cpu_name[cpu] = "NEC VR4131";
381                         } else {
382                                 c->cputype = CPU_VR4133;
383                                 __cpu_name[cpu] = "NEC VR4133";
384                         }
385                         break;
386                 default:
387                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
388                         c->cputype = CPU_VR41XX;
389                         __cpu_name[cpu] = "NEC Vr41xx";
390                         break;
391                 }
392                 c->isa_level = MIPS_CPU_ISA_III;
393                 c->options = R4K_OPTS;
394                 c->tlbsize = 32;
395                 break;
396         case PRID_IMP_R4300:
397                 c->cputype = CPU_R4300;
398                 __cpu_name[cpu] = "R4300";
399                 c->isa_level = MIPS_CPU_ISA_III;
400                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
401                              MIPS_CPU_LLSC;
402                 c->tlbsize = 32;
403                 break;
404         case PRID_IMP_R4600:
405                 c->cputype = CPU_R4600;
406                 __cpu_name[cpu] = "R4600";
407                 c->isa_level = MIPS_CPU_ISA_III;
408                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
409                              MIPS_CPU_LLSC;
410                 c->tlbsize = 48;
411                 break;
412         #if 0
413         case PRID_IMP_R4650:
414                 /*
415                  * This processor doesn't have an MMU, so it's not
416                  * "real easy" to run Linux on it. It is left purely
417                  * for documentation.  Commented out because it shares
418                  * it's c0_prid id number with the TX3900.
419                  */
420                 c->cputype = CPU_R4650;
421                 __cpu_name[cpu] = "R4650";
422                 c->isa_level = MIPS_CPU_ISA_III;
423                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
424                 c->tlbsize = 48;
425                 break;
426         #endif
427         case PRID_IMP_TX39:
428                 c->isa_level = MIPS_CPU_ISA_I;
429                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
430
431                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
432                         c->cputype = CPU_TX3927;
433                         __cpu_name[cpu] = "TX3927";
434                         c->tlbsize = 64;
435                 } else {
436                         switch (c->processor_id & 0xff) {
437                         case PRID_REV_TX3912:
438                                 c->cputype = CPU_TX3912;
439                                 __cpu_name[cpu] = "TX3912";
440                                 c->tlbsize = 32;
441                                 break;
442                         case PRID_REV_TX3922:
443                                 c->cputype = CPU_TX3922;
444                                 __cpu_name[cpu] = "TX3922";
445                                 c->tlbsize = 64;
446                                 break;
447                         }
448                 }
449                 break;
450         case PRID_IMP_R4700:
451                 c->cputype = CPU_R4700;
452                 __cpu_name[cpu] = "R4700";
453                 c->isa_level = MIPS_CPU_ISA_III;
454                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
455                              MIPS_CPU_LLSC;
456                 c->tlbsize = 48;
457                 break;
458         case PRID_IMP_TX49:
459                 c->cputype = CPU_TX49XX;
460                 __cpu_name[cpu] = "R49XX";
461                 c->isa_level = MIPS_CPU_ISA_III;
462                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
463                 if (!(c->processor_id & 0x08))
464                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
465                 c->tlbsize = 48;
466                 break;
467         case PRID_IMP_R5000:
468                 c->cputype = CPU_R5000;
469                 __cpu_name[cpu] = "R5000";
470                 c->isa_level = MIPS_CPU_ISA_IV;
471                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
472                              MIPS_CPU_LLSC;
473                 c->tlbsize = 48;
474                 break;
475         case PRID_IMP_R5432:
476                 c->cputype = CPU_R5432;
477                 __cpu_name[cpu] = "R5432";
478                 c->isa_level = MIPS_CPU_ISA_IV;
479                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
480                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
481                 c->tlbsize = 48;
482                 break;
483         case PRID_IMP_R5500:
484                 c->cputype = CPU_R5500;
485                 __cpu_name[cpu] = "R5500";
486                 c->isa_level = MIPS_CPU_ISA_IV;
487                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
488                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
489                 c->tlbsize = 48;
490                 break;
491         case PRID_IMP_NEVADA:
492                 c->cputype = CPU_NEVADA;
493                 __cpu_name[cpu] = "Nevada";
494                 c->isa_level = MIPS_CPU_ISA_IV;
495                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
496                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
497                 c->tlbsize = 48;
498                 break;
499         case PRID_IMP_R6000:
500                 c->cputype = CPU_R6000;
501                 __cpu_name[cpu] = "R6000";
502                 c->isa_level = MIPS_CPU_ISA_II;
503                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
504                              MIPS_CPU_LLSC;
505                 c->tlbsize = 32;
506                 break;
507         case PRID_IMP_R6000A:
508                 c->cputype = CPU_R6000A;
509                 __cpu_name[cpu] = "R6000A";
510                 c->isa_level = MIPS_CPU_ISA_II;
511                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
512                              MIPS_CPU_LLSC;
513                 c->tlbsize = 32;
514                 break;
515         case PRID_IMP_RM7000:
516                 c->cputype = CPU_RM7000;
517                 __cpu_name[cpu] = "RM7000";
518                 c->isa_level = MIPS_CPU_ISA_IV;
519                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
520                              MIPS_CPU_LLSC;
521                 /*
522                  * Undocumented RM7000:  Bit 29 in the info register of
523                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
524                  * entries.
525                  *
526                  * 29      1 =>    64 entry JTLB
527                  *         0 =>    48 entry JTLB
528                  */
529                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
530                 break;
531         case PRID_IMP_RM9000:
532                 c->cputype = CPU_RM9000;
533                 __cpu_name[cpu] = "RM9000";
534                 c->isa_level = MIPS_CPU_ISA_IV;
535                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
536                              MIPS_CPU_LLSC;
537                 /*
538                  * Bit 29 in the info register of the RM9000
539                  * indicates if the TLB has 48 or 64 entries.
540                  *
541                  * 29      1 =>    64 entry JTLB
542                  *         0 =>    48 entry JTLB
543                  */
544                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
545                 break;
546         case PRID_IMP_R8000:
547                 c->cputype = CPU_R8000;
548                 __cpu_name[cpu] = "RM8000";
549                 c->isa_level = MIPS_CPU_ISA_IV;
550                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
551                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
552                              MIPS_CPU_LLSC;
553                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
554                 break;
555         case PRID_IMP_R10000:
556                 c->cputype = CPU_R10000;
557                 __cpu_name[cpu] = "R10000";
558                 c->isa_level = MIPS_CPU_ISA_IV;
559                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
560                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
561                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
562                              MIPS_CPU_LLSC;
563                 c->tlbsize = 64;
564                 break;
565         case PRID_IMP_R12000:
566                 c->cputype = CPU_R12000;
567                 __cpu_name[cpu] = "R12000";
568                 c->isa_level = MIPS_CPU_ISA_IV;
569                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
570                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
571                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
572                              MIPS_CPU_LLSC;
573                 c->tlbsize = 64;
574                 break;
575         case PRID_IMP_R14000:
576                 c->cputype = CPU_R14000;
577                 __cpu_name[cpu] = "R14000";
578                 c->isa_level = MIPS_CPU_ISA_IV;
579                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
580                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
581                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
582                              MIPS_CPU_LLSC;
583                 c->tlbsize = 64;
584                 break;
585         case PRID_IMP_LOONGSON2:
586                 c->cputype = CPU_LOONGSON2;
587                 __cpu_name[cpu] = "ICT Loongson-2";
588                 c->isa_level = MIPS_CPU_ISA_III;
589                 c->options = R4K_OPTS |
590                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
591                              MIPS_CPU_32FPR;
592                 c->tlbsize = 64;
593                 break;
594         }
595 }
596
597 static char unknown_isa[] __cpuinitdata = KERN_ERR \
598         "Unsupported ISA type, c0.config0: %d.";
599
600 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
601 {
602         unsigned int config0;
603         int isa;
604
605         config0 = read_c0_config();
606
607         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
608                 c->options |= MIPS_CPU_TLB;
609         isa = (config0 & MIPS_CONF_AT) >> 13;
610         switch (isa) {
611         case 0:
612                 switch ((config0 & MIPS_CONF_AR) >> 10) {
613                 case 0:
614                         c->isa_level = MIPS_CPU_ISA_M32R1;
615                         break;
616                 case 1:
617                         c->isa_level = MIPS_CPU_ISA_M32R2;
618                         break;
619                 default:
620                         goto unknown;
621                 }
622                 break;
623         case 2:
624                 switch ((config0 & MIPS_CONF_AR) >> 10) {
625                 case 0:
626                         c->isa_level = MIPS_CPU_ISA_M64R1;
627                         break;
628                 case 1:
629                         c->isa_level = MIPS_CPU_ISA_M64R2;
630                         break;
631                 default:
632                         goto unknown;
633                 }
634                 break;
635         default:
636                 goto unknown;
637         }
638
639         return config0 & MIPS_CONF_M;
640
641 unknown:
642         panic(unknown_isa, config0);
643 }
644
645 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
646 {
647         unsigned int config1;
648
649         config1 = read_c0_config1();
650
651         if (config1 & MIPS_CONF1_MD)
652                 c->ases |= MIPS_ASE_MDMX;
653         if (config1 & MIPS_CONF1_WR)
654                 c->options |= MIPS_CPU_WATCH;
655         if (config1 & MIPS_CONF1_CA)
656                 c->ases |= MIPS_ASE_MIPS16;
657         if (config1 & MIPS_CONF1_EP)
658                 c->options |= MIPS_CPU_EJTAG;
659         if (config1 & MIPS_CONF1_FP) {
660                 c->options |= MIPS_CPU_FPU;
661                 c->options |= MIPS_CPU_32FPR;
662         }
663         if (cpu_has_tlb)
664                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
665
666         return config1 & MIPS_CONF_M;
667 }
668
669 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
670 {
671         unsigned int config2;
672
673         config2 = read_c0_config2();
674
675         if (config2 & MIPS_CONF2_SL)
676                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
677
678         return config2 & MIPS_CONF_M;
679 }
680
681 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
682 {
683         unsigned int config3;
684
685         config3 = read_c0_config3();
686
687         if (config3 & MIPS_CONF3_SM)
688                 c->ases |= MIPS_ASE_SMARTMIPS;
689         if (config3 & MIPS_CONF3_DSP)
690                 c->ases |= MIPS_ASE_DSP;
691         if (config3 & MIPS_CONF3_VINT)
692                 c->options |= MIPS_CPU_VINT;
693         if (config3 & MIPS_CONF3_VEIC)
694                 c->options |= MIPS_CPU_VEIC;
695         if (config3 & MIPS_CONF3_MT)
696                 c->ases |= MIPS_ASE_MIPSMT;
697         if (config3 & MIPS_CONF3_ULRI)
698                 c->options |= MIPS_CPU_ULRI;
699
700         return config3 & MIPS_CONF_M;
701 }
702
703 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
704 {
705         int ok;
706
707         /* MIPS32 or MIPS64 compliant CPU.  */
708         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
709                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
710
711         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
712
713         ok = decode_config0(c);                 /* Read Config registers.  */
714         BUG_ON(!ok);                            /* Arch spec violation!  */
715         if (ok)
716                 ok = decode_config1(c);
717         if (ok)
718                 ok = decode_config2(c);
719         if (ok)
720                 ok = decode_config3(c);
721
722         mips_probe_watch_registers(c);
723 }
724
725 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
726 {
727         decode_configs(c);
728         switch (c->processor_id & 0xff00) {
729         case PRID_IMP_4KC:
730                 c->cputype = CPU_4KC;
731                 __cpu_name[cpu] = "MIPS 4Kc";
732                 break;
733         case PRID_IMP_4KEC:
734                 c->cputype = CPU_4KEC;
735                 __cpu_name[cpu] = "MIPS 4KEc";
736                 break;
737         case PRID_IMP_4KECR2:
738                 c->cputype = CPU_4KEC;
739                 __cpu_name[cpu] = "MIPS 4KEc";
740                 break;
741         case PRID_IMP_4KSC:
742         case PRID_IMP_4KSD:
743                 c->cputype = CPU_4KSC;
744                 __cpu_name[cpu] = "MIPS 4KSc";
745                 break;
746         case PRID_IMP_5KC:
747                 c->cputype = CPU_5KC;
748                 __cpu_name[cpu] = "MIPS 5Kc";
749                 break;
750         case PRID_IMP_20KC:
751                 c->cputype = CPU_20KC;
752                 __cpu_name[cpu] = "MIPS 20Kc";
753                 break;
754         case PRID_IMP_24K:
755         case PRID_IMP_24KE:
756                 c->cputype = CPU_24K;
757                 __cpu_name[cpu] = "MIPS 24Kc";
758                 break;
759         case PRID_IMP_25KF:
760                 c->cputype = CPU_25KF;
761                 __cpu_name[cpu] = "MIPS 25Kc";
762                 break;
763         case PRID_IMP_34K:
764                 c->cputype = CPU_34K;
765                 __cpu_name[cpu] = "MIPS 34Kc";
766                 break;
767         case PRID_IMP_74K:
768                 c->cputype = CPU_74K;
769                 __cpu_name[cpu] = "MIPS 74Kc";
770                 break;
771         case PRID_IMP_1004K:
772                 c->cputype = CPU_1004K;
773                 __cpu_name[cpu] = "MIPS 1004Kc";
774                 break;
775         }
776
777         spram_config();
778 }
779
780 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
781 {
782         decode_configs(c);
783         switch (c->processor_id & 0xff00) {
784         case PRID_IMP_AU1_REV1:
785         case PRID_IMP_AU1_REV2:
786                 c->cputype = CPU_ALCHEMY;
787                 switch ((c->processor_id >> 24) & 0xff) {
788                 case 0:
789                         __cpu_name[cpu] = "Au1000";
790                         break;
791                 case 1:
792                         __cpu_name[cpu] = "Au1500";
793                         break;
794                 case 2:
795                         __cpu_name[cpu] = "Au1100";
796                         break;
797                 case 3:
798                         __cpu_name[cpu] = "Au1550";
799                         break;
800                 case 4:
801                         __cpu_name[cpu] = "Au1200";
802                         if ((c->processor_id & 0xff) == 2)
803                                 __cpu_name[cpu] = "Au1250";
804                         break;
805                 case 5:
806                         __cpu_name[cpu] = "Au1210";
807                         break;
808                 default:
809                         __cpu_name[cpu] = "Au1xxx";
810                         break;
811                 }
812                 break;
813         }
814 }
815
816 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
817 {
818         decode_configs(c);
819
820         switch (c->processor_id & 0xff00) {
821         case PRID_IMP_SB1:
822                 c->cputype = CPU_SB1;
823                 __cpu_name[cpu] = "SiByte SB1";
824                 /* FPU in pass1 is known to have issues. */
825                 if ((c->processor_id & 0xff) < 0x02)
826                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
827                 break;
828         case PRID_IMP_SB1A:
829                 c->cputype = CPU_SB1A;
830                 __cpu_name[cpu] = "SiByte SB1A";
831                 break;
832         }
833 }
834
835 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
836 {
837         decode_configs(c);
838         switch (c->processor_id & 0xff00) {
839         case PRID_IMP_SR71000:
840                 c->cputype = CPU_SR71000;
841                 __cpu_name[cpu] = "Sandcraft SR71000";
842                 c->scache.ways = 8;
843                 c->tlbsize = 64;
844                 break;
845         }
846 }
847
848 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
849 {
850         decode_configs(c);
851         switch (c->processor_id & 0xff00) {
852         case PRID_IMP_PR4450:
853                 c->cputype = CPU_PR4450;
854                 __cpu_name[cpu] = "Philips PR4450";
855                 c->isa_level = MIPS_CPU_ISA_M32R1;
856                 break;
857         }
858 }
859
860 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
861 {
862         decode_configs(c);
863         switch (c->processor_id & 0xff00) {
864         case PRID_IMP_BCM3302:
865          /* same as PRID_IMP_BCM6338 */
866                 c->cputype = CPU_BCM3302;
867                 __cpu_name[cpu] = "Broadcom BCM3302";
868                 break;
869         case PRID_IMP_BCM4710:
870                 c->cputype = CPU_BCM4710;
871                 __cpu_name[cpu] = "Broadcom BCM4710";
872                 break;
873         case PRID_IMP_BCM6345:
874                 c->cputype = CPU_BCM6345;
875                 __cpu_name[cpu] = "Broadcom BCM6345";
876                 break;
877         case PRID_IMP_BCM6348:
878                 c->cputype = CPU_BCM6348;
879                 __cpu_name[cpu] = "Broadcom BCM6348";
880                 break;
881         case PRID_IMP_BCM4350:
882                 switch (c->processor_id & 0xf0) {
883                 case PRID_REV_BCM6358:
884                         c->cputype = CPU_BCM6358;
885                         __cpu_name[cpu] = "Broadcom BCM6358";
886                         break;
887                 default:
888                         c->cputype = CPU_UNKNOWN;
889                         break;
890                 }
891                 break;
892         }
893 }
894
895 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
896 {
897         decode_configs(c);
898         switch (c->processor_id & 0xff00) {
899         case PRID_IMP_CAVIUM_CN38XX:
900         case PRID_IMP_CAVIUM_CN31XX:
901         case PRID_IMP_CAVIUM_CN30XX:
902         case PRID_IMP_CAVIUM_CN58XX:
903         case PRID_IMP_CAVIUM_CN56XX:
904         case PRID_IMP_CAVIUM_CN50XX:
905         case PRID_IMP_CAVIUM_CN52XX:
906                 c->cputype = CPU_CAVIUM_OCTEON;
907                 __cpu_name[cpu] = "Cavium Octeon";
908                 break;
909         default:
910                 printk(KERN_INFO "Unknown Octeon chip!\n");
911                 c->cputype = CPU_UNKNOWN;
912                 break;
913         }
914 }
915
916 const char *__cpu_name[NR_CPUS];
917
918 __cpuinit void cpu_probe(void)
919 {
920         struct cpuinfo_mips *c = &current_cpu_data;
921         unsigned int cpu = smp_processor_id();
922
923         c->processor_id = PRID_IMP_UNKNOWN;
924         c->fpu_id       = FPIR_IMP_NONE;
925         c->cputype      = CPU_UNKNOWN;
926
927         c->processor_id = read_c0_prid();
928         switch (c->processor_id & 0xff0000) {
929         case PRID_COMP_LEGACY:
930                 cpu_probe_legacy(c, cpu);
931                 break;
932         case PRID_COMP_MIPS:
933                 cpu_probe_mips(c, cpu);
934                 break;
935         case PRID_COMP_ALCHEMY:
936                 cpu_probe_alchemy(c, cpu);
937                 break;
938         case PRID_COMP_SIBYTE:
939                 cpu_probe_sibyte(c, cpu);
940                 break;
941         case PRID_COMP_BROADCOM:
942                 cpu_probe_broadcom(c, cpu);
943                 break;
944         case PRID_COMP_SANDCRAFT:
945                 cpu_probe_sandcraft(c, cpu);
946                 break;
947         case PRID_COMP_NXP:
948                 cpu_probe_nxp(c, cpu);
949                 break;
950         case PRID_COMP_CAVIUM:
951                 cpu_probe_cavium(c, cpu);
952                 break;
953         }
954
955         BUG_ON(!__cpu_name[cpu]);
956         BUG_ON(c->cputype == CPU_UNKNOWN);
957
958         /*
959          * Platform code can force the cpu type to optimize code
960          * generation. In that case be sure the cpu type is correctly
961          * manually setup otherwise it could trigger some nasty bugs.
962          */
963         BUG_ON(current_cpu_type() != c->cputype);
964
965         if (c->options & MIPS_CPU_FPU) {
966                 c->fpu_id = cpu_get_fpu_id();
967
968                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
969                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
970                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
971                     c->isa_level == MIPS_CPU_ISA_M64R2) {
972                         if (c->fpu_id & MIPS_FPIR_3D)
973                                 c->ases |= MIPS_ASE_MIPS3D;
974                 }
975         }
976
977         if (cpu_has_mips_r2)
978                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
979         else
980                 c->srsets = 1;
981
982         cpu_probe_vmbits(c);
983 }
984
985 __cpuinit void cpu_report(void)
986 {
987         struct cpuinfo_mips *c = &current_cpu_data;
988
989         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
990                c->processor_id, cpu_name_string());
991         if (c->options & MIPS_CPU_FPU)
992                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
993 }