Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-2.6.git] / arch / mips / cavium-octeon / smp.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
7  */
8 #include <linux/cpu.h>
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/sched.h>
15 #include <linux/module.h>
16
17 #include <asm/mmu_context.h>
18 #include <asm/system.h>
19 #include <asm/time.h>
20
21 #include <asm/octeon/octeon.h>
22
23 #include "octeon_boot.h"
24
25 volatile unsigned long octeon_processor_boot = 0xff;
26 volatile unsigned long octeon_processor_sp;
27 volatile unsigned long octeon_processor_gp;
28
29 #ifdef CONFIG_HOTPLUG_CPU
30 uint64_t octeon_bootloader_entry_addr;
31 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
32 #endif
33
34 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
35 {
36         const int coreid = cvmx_get_core_num();
37         uint64_t action;
38
39         /* Load the mailbox register to figure out what we're supposed to do */
40         action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
41
42         /* Clear the mailbox to clear the interrupt */
43         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44
45         if (action & SMP_CALL_FUNCTION)
46                 smp_call_function_interrupt();
47
48         /* Check if we've been told to flush the icache */
49         if (action & SMP_ICACHE_FLUSH)
50                 asm volatile ("synci 0($0)\n");
51         return IRQ_HANDLED;
52 }
53
54 /**
55  * Cause the function described by call_data to be executed on the passed
56  * cpu.  When the function has finished, increment the finished field of
57  * call_data.
58  */
59 void octeon_send_ipi_single(int cpu, unsigned int action)
60 {
61         int coreid = cpu_logical_map(cpu);
62         /*
63         pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
64                coreid, action);
65         */
66         cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
67 }
68
69 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
70                                         unsigned int action)
71 {
72         unsigned int i;
73
74         for_each_cpu_mask(i, *mask)
75                 octeon_send_ipi_single(i, action);
76 }
77
78 /**
79  * Detect available CPUs, populate cpu_possible_map
80  */
81 static void octeon_smp_hotplug_setup(void)
82 {
83 #ifdef CONFIG_HOTPLUG_CPU
84         struct linux_app_boot_info *labi;
85
86         labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
87         if (labi->labi_signature != LABI_SIGNATURE)
88                 panic("The bootloader version on this board is incorrect.");
89
90         octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
91 #endif
92 }
93
94 static void octeon_smp_setup(void)
95 {
96         const int coreid = cvmx_get_core_num();
97         int cpus;
98         int id;
99         int core_mask = octeon_get_boot_coremask();
100 #ifdef CONFIG_HOTPLUG_CPU
101         unsigned int num_cores = cvmx_octeon_num_cores();
102 #endif
103
104         /* The present CPUs are initially just the boot cpu (CPU 0). */
105         for (id = 0; id < NR_CPUS; id++) {
106                 set_cpu_possible(id, id == 0);
107                 set_cpu_present(id, id == 0);
108         }
109
110         __cpu_number_map[coreid] = 0;
111         __cpu_logical_map[0] = coreid;
112
113         /* The present CPUs get the lowest CPU numbers. */
114         cpus = 1;
115         for (id = 0; id < NR_CPUS; id++) {
116                 if ((id != coreid) && (core_mask & (1 << id))) {
117                         set_cpu_possible(cpus, true);
118                         set_cpu_present(cpus, true);
119                         __cpu_number_map[id] = cpus;
120                         __cpu_logical_map[cpus] = id;
121                         cpus++;
122                 }
123         }
124
125 #ifdef CONFIG_HOTPLUG_CPU
126         /*
127          * The possible CPUs are all those present on the chip.  We
128          * will assign CPU numbers for possible cores as well.  Cores
129          * are always consecutively numberd from 0.
130          */
131         for (id = 0; id < num_cores && id < NR_CPUS; id++) {
132                 if (!(core_mask & (1 << id))) {
133                         set_cpu_possible(cpus, true);
134                         __cpu_number_map[id] = cpus;
135                         __cpu_logical_map[cpus] = id;
136                         cpus++;
137                 }
138         }
139 #endif
140
141         octeon_smp_hotplug_setup();
142 }
143
144 /**
145  * Firmware CPU startup hook
146  *
147  */
148 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
149 {
150         int count;
151
152         pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
153                 cpu_logical_map(cpu));
154
155         octeon_processor_sp = __KSTK_TOS(idle);
156         octeon_processor_gp = (unsigned long)(task_thread_info(idle));
157         octeon_processor_boot = cpu_logical_map(cpu);
158         mb();
159
160         count = 10000;
161         while (octeon_processor_sp && count) {
162                 /* Waiting for processor to get the SP and GP */
163                 udelay(1);
164                 count--;
165         }
166         if (count == 0)
167                 pr_err("Secondary boot timeout\n");
168 }
169
170 /**
171  * After we've done initial boot, this function is called to allow the
172  * board code to clean up state, if needed
173  */
174 static void __cpuinit octeon_init_secondary(void)
175 {
176         unsigned int sr;
177
178         sr = set_c0_status(ST0_BEV);
179         write_c0_ebase((u32)ebase);
180         write_c0_status(sr);
181
182         octeon_check_cpu_bist();
183         octeon_init_cvmcount();
184
185         octeon_irq_setup_secondary();
186         raw_local_irq_enable();
187 }
188
189 /**
190  * Callout to firmware before smp_init
191  *
192  */
193 void octeon_prepare_cpus(unsigned int max_cpus)
194 {
195 #ifdef CONFIG_HOTPLUG_CPU
196         struct linux_app_boot_info *labi;
197
198         labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
199
200         if (labi->labi_signature != LABI_SIGNATURE)
201                 panic("The bootloader version on this board is incorrect.");
202 #endif
203         /*
204          * Only the low order mailbox bits are used for IPIs, leave
205          * the other bits alone.
206          */
207         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
208         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
209                         "SMP-IPI", mailbox_interrupt)) {
210                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
211         }
212 }
213
214 /**
215  * Last chance for the board code to finish SMP initialization before
216  * the CPU is "online".
217  */
218 static void octeon_smp_finish(void)
219 {
220 #ifdef CONFIG_CAVIUM_GDB
221         unsigned long tmp;
222         /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
223            to be not masked by this core so we know the signal is received by
224            someone */
225         asm volatile ("dmfc0 %0, $22\n"
226                       "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
227 #endif
228
229         octeon_user_io_init();
230
231         /* to generate the first CPU timer interrupt */
232         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
233 }
234
235 /**
236  * Hook for after all CPUs are online
237  */
238 static void octeon_cpus_done(void)
239 {
240 #ifdef CONFIG_CAVIUM_GDB
241         unsigned long tmp;
242         /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
243            to be not masked by this core so we know the signal is received by
244            someone */
245         asm volatile ("dmfc0 %0, $22\n"
246                       "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
247 #endif
248 }
249
250 #ifdef CONFIG_HOTPLUG_CPU
251
252 /* State of each CPU. */
253 DEFINE_PER_CPU(int, cpu_state);
254
255 extern void fixup_irqs(void);
256
257 static DEFINE_SPINLOCK(smp_reserve_lock);
258
259 static int octeon_cpu_disable(void)
260 {
261         unsigned int cpu = smp_processor_id();
262
263         if (cpu == 0)
264                 return -EBUSY;
265
266         spin_lock(&smp_reserve_lock);
267
268         cpu_clear(cpu, cpu_online_map);
269         cpu_clear(cpu, cpu_callin_map);
270         local_irq_disable();
271         fixup_irqs();
272         local_irq_enable();
273
274         flush_cache_all();
275         local_flush_tlb_all();
276
277         spin_unlock(&smp_reserve_lock);
278
279         return 0;
280 }
281
282 static void octeon_cpu_die(unsigned int cpu)
283 {
284         int coreid = cpu_logical_map(cpu);
285         uint32_t mask, new_mask;
286         const struct cvmx_bootmem_named_block_desc *block_desc;
287
288         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
289                 cpu_relax();
290
291         /*
292          * This is a bit complicated strategics of getting/settig available
293          * cores mask, copied from bootloader
294          */
295
296         mask = 1 << coreid;
297         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
298         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
299
300         if (!block_desc) {
301                 struct linux_app_boot_info *labi;
302
303                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
304
305                 labi->avail_coremask |= mask;
306                 new_mask = labi->avail_coremask;
307         } else {                       /* alternative, already initialized */
308                 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
309                                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
310                 *p |= mask;
311                 new_mask = *p;
312         }
313
314         pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
315         mb();
316         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
317         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
318 }
319
320 void play_dead(void)
321 {
322         int cpu = cpu_number_map(cvmx_get_core_num());
323
324         idle_task_exit();
325         octeon_processor_boot = 0xff;
326         per_cpu(cpu_state, cpu) = CPU_DEAD;
327
328         mb();
329
330         while (1)       /* core will be reset here */
331                 ;
332 }
333
334 extern void kernel_entry(unsigned long arg1, ...);
335
336 static void start_after_reset(void)
337 {
338         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
339 }
340
341 static int octeon_update_boot_vector(unsigned int cpu)
342 {
343
344         int coreid = cpu_logical_map(cpu);
345         uint32_t avail_coremask;
346         const struct cvmx_bootmem_named_block_desc *block_desc;
347         struct boot_init_vector *boot_vect =
348                 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
349
350         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
351
352         if (!block_desc) {
353                 struct linux_app_boot_info *labi;
354
355                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
356
357                 avail_coremask = labi->avail_coremask;
358                 labi->avail_coremask &= ~(1 << coreid);
359         } else {                       /* alternative, already initialized */
360                 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
361                         block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
362         }
363
364         if (!(avail_coremask & (1 << coreid))) {
365                 /* core not available, assume, that catched by simple-executive */
366                 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
367                 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
368         }
369
370         boot_vect[coreid].app_start_func_addr =
371                 (uint32_t) (unsigned long) start_after_reset;
372         boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
373
374         mb();
375
376         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
377
378         return 0;
379 }
380
381 static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
382         unsigned long action, void *hcpu)
383 {
384         unsigned int cpu = (unsigned long)hcpu;
385
386         switch (action) {
387         case CPU_UP_PREPARE:
388                 octeon_update_boot_vector(cpu);
389                 break;
390         case CPU_ONLINE:
391                 pr_info("Cpu %d online\n", cpu);
392                 break;
393         case CPU_DEAD:
394                 break;
395         }
396
397         return NOTIFY_OK;
398 }
399
400 static int __cpuinit register_cavium_notifier(void)
401 {
402         hotcpu_notifier(octeon_cpu_callback, 0);
403         return 0;
404 }
405 late_initcall(register_cavium_notifier);
406
407 #endif  /* CONFIG_HOTPLUG_CPU */
408
409 struct plat_smp_ops octeon_smp_ops = {
410         .send_ipi_single        = octeon_send_ipi_single,
411         .send_ipi_mask          = octeon_send_ipi_mask,
412         .init_secondary         = octeon_init_secondary,
413         .smp_finish             = octeon_smp_finish,
414         .cpus_done              = octeon_cpus_done,
415         .boot_secondary         = octeon_boot_secondary,
416         .smp_setup              = octeon_smp_setup,
417         .prepare_cpus           = octeon_prepare_cpus,
418 #ifdef CONFIG_HOTPLUG_CPU
419         .cpu_disable            = octeon_cpu_disable,
420         .cpu_die                = octeon_cpu_die,
421 #endif
422 };