MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
[linux-2.6.git] / arch / mips / cavium-octeon / octeon-irq.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2008 Cavium Networks
7  */
8 #include <linux/irq.h>
9 #include <linux/interrupt.h>
10 #include <linux/smp.h>
11
12 #include <asm/octeon/octeon.h>
13 #include <asm/octeon/cvmx-pexp-defs.h>
14 #include <asm/octeon/cvmx-npi-defs.h>
15
16 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
17 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
18 DEFINE_SPINLOCK(octeon_irq_msi_lock);
19
20 static void octeon_irq_core_ack(unsigned int irq)
21 {
22         unsigned int bit = irq - OCTEON_IRQ_SW0;
23         /*
24          * We don't need to disable IRQs to make these atomic since
25          * they are already disabled earlier in the low level
26          * interrupt code.
27          */
28         clear_c0_status(0x100 << bit);
29         /* The two user interrupts must be cleared manually. */
30         if (bit < 2)
31                 clear_c0_cause(0x100 << bit);
32 }
33
34 static void octeon_irq_core_eoi(unsigned int irq)
35 {
36         struct irq_desc *desc = irq_desc + irq;
37         unsigned int bit = irq - OCTEON_IRQ_SW0;
38         /*
39          * If an IRQ is being processed while we are disabling it the
40          * handler will attempt to unmask the interrupt after it has
41          * been disabled.
42          */
43         if (desc->status & IRQ_DISABLED)
44                 return;
45
46         /* There is a race here.  We should fix it.  */
47
48         /*
49          * We don't need to disable IRQs to make these atomic since
50          * they are already disabled earlier in the low level
51          * interrupt code.
52          */
53         set_c0_status(0x100 << bit);
54 }
55
56 static void octeon_irq_core_enable(unsigned int irq)
57 {
58         unsigned long flags;
59         unsigned int bit = irq - OCTEON_IRQ_SW0;
60
61         /*
62          * We need to disable interrupts to make sure our updates are
63          * atomic.
64          */
65         local_irq_save(flags);
66         set_c0_status(0x100 << bit);
67         local_irq_restore(flags);
68 }
69
70 static void octeon_irq_core_disable_local(unsigned int irq)
71 {
72         unsigned long flags;
73         unsigned int bit = irq - OCTEON_IRQ_SW0;
74         /*
75          * We need to disable interrupts to make sure our updates are
76          * atomic.
77          */
78         local_irq_save(flags);
79         clear_c0_status(0x100 << bit);
80         local_irq_restore(flags);
81 }
82
83 static void octeon_irq_core_disable(unsigned int irq)
84 {
85 #ifdef CONFIG_SMP
86         on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
87                     (void *) (long) irq, 1);
88 #else
89         octeon_irq_core_disable_local(irq);
90 #endif
91 }
92
93 static struct irq_chip octeon_irq_chip_core = {
94         .name = "Core",
95         .enable = octeon_irq_core_enable,
96         .disable = octeon_irq_core_disable,
97         .ack = octeon_irq_core_ack,
98         .eoi = octeon_irq_core_eoi,
99 };
100
101
102 static void octeon_irq_ciu0_ack(unsigned int irq)
103 {
104         /*
105          * In order to avoid any locking accessing the CIU, we
106          * acknowledge CIU interrupts by disabling all of them.  This
107          * way we can use a per core register and avoid any out of
108          * core locking requirements.  This has the side affect that
109          * CIU interrupts can't be processed recursively.
110          *
111          * We don't need to disable IRQs to make these atomic since
112          * they are already disabled earlier in the low level
113          * interrupt code.
114          */
115         clear_c0_status(0x100 << 2);
116 }
117
118 static void octeon_irq_ciu0_eoi(unsigned int irq)
119 {
120         /*
121          * Enable all CIU interrupts again.  We don't need to disable
122          * IRQs to make these atomic since they are already disabled
123          * earlier in the low level interrupt code.
124          */
125         set_c0_status(0x100 << 2);
126 }
127
128 static void octeon_irq_ciu0_enable(unsigned int irq)
129 {
130         int coreid = cvmx_get_core_num();
131         unsigned long flags;
132         uint64_t en0;
133         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
134
135         /*
136          * A read lock is used here to make sure only one core is ever
137          * updating the CIU enable bits at a time. During an enable
138          * the cores don't interfere with each other. During a disable
139          * the write lock stops any enables that might cause a
140          * problem.
141          */
142         read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
143         en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
144         en0 |= 1ull << bit;
145         cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
146         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
147         read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
148 }
149
150 static void octeon_irq_ciu0_disable(unsigned int irq)
151 {
152         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
153         unsigned long flags;
154         uint64_t en0;
155 #ifdef CONFIG_SMP
156         int cpu;
157         write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
158         for_each_online_cpu(cpu) {
159                 int coreid = cpu_logical_map(cpu);
160                 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
161                 en0 &= ~(1ull << bit);
162                 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
163         }
164         /*
165          * We need to do a read after the last update to make sure all
166          * of them are done.
167          */
168         cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
169         write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
170 #else
171         int coreid = cvmx_get_core_num();
172         local_irq_save(flags);
173         en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
174         en0 &= ~(1ull << bit);
175         cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
176         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
177         local_irq_restore(flags);
178 #endif
179 }
180
181 #ifdef CONFIG_SMP
182 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
183 {
184         int cpu;
185         unsigned long flags;
186         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
187
188         write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
189         for_each_online_cpu(cpu) {
190                 int coreid = cpu_logical_map(cpu);
191                 uint64_t en0 =
192                         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
193                 if (cpumask_test_cpu(cpu, dest))
194                         en0 |= 1ull << bit;
195                 else
196                         en0 &= ~(1ull << bit);
197                 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
198         }
199         /*
200          * We need to do a read after the last update to make sure all
201          * of them are done.
202          */
203         cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
204         write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
205
206         return 0;
207 }
208 #endif
209
210 static struct irq_chip octeon_irq_chip_ciu0 = {
211         .name = "CIU0",
212         .enable = octeon_irq_ciu0_enable,
213         .disable = octeon_irq_ciu0_disable,
214         .ack = octeon_irq_ciu0_ack,
215         .eoi = octeon_irq_ciu0_eoi,
216 #ifdef CONFIG_SMP
217         .set_affinity = octeon_irq_ciu0_set_affinity,
218 #endif
219 };
220
221
222 static void octeon_irq_ciu1_ack(unsigned int irq)
223 {
224         /*
225          * In order to avoid any locking accessing the CIU, we
226          * acknowledge CIU interrupts by disabling all of them.  This
227          * way we can use a per core register and avoid any out of
228          * core locking requirements.  This has the side affect that
229          * CIU interrupts can't be processed recursively.  We don't
230          * need to disable IRQs to make these atomic since they are
231          * already disabled earlier in the low level interrupt code.
232          */
233         clear_c0_status(0x100 << 3);
234 }
235
236 static void octeon_irq_ciu1_eoi(unsigned int irq)
237 {
238         /*
239          * Enable all CIU interrupts again.  We don't need to disable
240          * IRQs to make these atomic since they are already disabled
241          * earlier in the low level interrupt code.
242          */
243         set_c0_status(0x100 << 3);
244 }
245
246 static void octeon_irq_ciu1_enable(unsigned int irq)
247 {
248         int coreid = cvmx_get_core_num();
249         unsigned long flags;
250         uint64_t en1;
251         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
252
253         /*
254          * A read lock is used here to make sure only one core is ever
255          * updating the CIU enable bits at a time.  During an enable
256          * the cores don't interfere with each other.  During a disable
257          * the write lock stops any enables that might cause a
258          * problem.
259          */
260         read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
261         en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
262         en1 |= 1ull << bit;
263         cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
264         cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
265         read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
266 }
267
268 static void octeon_irq_ciu1_disable(unsigned int irq)
269 {
270         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
271         unsigned long flags;
272         uint64_t en1;
273 #ifdef CONFIG_SMP
274         int cpu;
275         write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
276         for_each_online_cpu(cpu) {
277                 int coreid = cpu_logical_map(cpu);
278                 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
279                 en1 &= ~(1ull << bit);
280                 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
281         }
282         /*
283          * We need to do a read after the last update to make sure all
284          * of them are done.
285          */
286         cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
287         write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
288 #else
289         int coreid = cvmx_get_core_num();
290         local_irq_save(flags);
291         en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
292         en1 &= ~(1ull << bit);
293         cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
294         cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
295         local_irq_restore(flags);
296 #endif
297 }
298
299 #ifdef CONFIG_SMP
300 static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
301 {
302         int cpu;
303         unsigned long flags;
304         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
305
306         write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
307         for_each_online_cpu(cpu) {
308                 int coreid = cpu_logical_map(cpu);
309                 uint64_t en1 =
310                         cvmx_read_csr(CVMX_CIU_INTX_EN1
311                                 (coreid * 2 + 1));
312                 if (cpumask_test_cpu(cpu, dest))
313                         en1 |= 1ull << bit;
314                 else
315                         en1 &= ~(1ull << bit);
316                 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
317         }
318         /*
319          * We need to do a read after the last update to make sure all
320          * of them are done.
321          */
322         cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
323         write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
324
325         return 0;
326 }
327 #endif
328
329 static struct irq_chip octeon_irq_chip_ciu1 = {
330         .name = "CIU1",
331         .enable = octeon_irq_ciu1_enable,
332         .disable = octeon_irq_ciu1_disable,
333         .ack = octeon_irq_ciu1_ack,
334         .eoi = octeon_irq_ciu1_eoi,
335 #ifdef CONFIG_SMP
336         .set_affinity = octeon_irq_ciu1_set_affinity,
337 #endif
338 };
339
340 #ifdef CONFIG_PCI_MSI
341
342 static void octeon_irq_msi_ack(unsigned int irq)
343 {
344         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
345                 /* These chips have PCI */
346                 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
347                                1ull << (irq - OCTEON_IRQ_MSI_BIT0));
348         } else {
349                 /*
350                  * These chips have PCIe. Thankfully the ACK doesn't
351                  * need any locking.
352                  */
353                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
354                                1ull << (irq - OCTEON_IRQ_MSI_BIT0));
355         }
356 }
357
358 static void octeon_irq_msi_eoi(unsigned int irq)
359 {
360         /* Nothing needed */
361 }
362
363 static void octeon_irq_msi_enable(unsigned int irq)
364 {
365         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
366                 /*
367                  * Octeon PCI doesn't have the ability to mask/unmask
368                  * MSI interrupts individually.  Instead of
369                  * masking/unmasking them in groups of 16, we simple
370                  * assume MSI devices are well behaved.  MSI
371                  * interrupts are always enable and the ACK is assumed
372                  * to be enough.
373                  */
374         } else {
375                 /* These chips have PCIe.  Note that we only support
376                  * the first 64 MSI interrupts.  Unfortunately all the
377                  * MSI enables are in the same register.  We use
378                  * MSI0's lock to control access to them all.
379                  */
380                 uint64_t en;
381                 unsigned long flags;
382                 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
383                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
384                 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
385                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
386                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
387                 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
388         }
389 }
390
391 static void octeon_irq_msi_disable(unsigned int irq)
392 {
393         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
394                 /* See comment in enable */
395         } else {
396                 /*
397                  * These chips have PCIe.  Note that we only support
398                  * the first 64 MSI interrupts.  Unfortunately all the
399                  * MSI enables are in the same register.  We use
400                  * MSI0's lock to control access to them all.
401                  */
402                 uint64_t en;
403                 unsigned long flags;
404                 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
405                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
406                 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
407                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
408                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
409                 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
410         }
411 }
412
413 static struct irq_chip octeon_irq_chip_msi = {
414         .name = "MSI",
415         .enable = octeon_irq_msi_enable,
416         .disable = octeon_irq_msi_disable,
417         .ack = octeon_irq_msi_ack,
418         .eoi = octeon_irq_msi_eoi,
419 };
420 #endif
421
422 void __init arch_init_irq(void)
423 {
424         int irq;
425
426 #ifdef CONFIG_SMP
427         /* Set the default affinity to the boot cpu. */
428         cpumask_clear(irq_default_affinity);
429         cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
430 #endif
431
432         if (NR_IRQS < OCTEON_IRQ_LAST)
433                 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
434
435         /* 0 - 15 reserved for i8259 master and slave controller. */
436
437         /* 17 - 23 Mips internal */
438         for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
439                 set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
440                                          handle_percpu_irq);
441         }
442
443         /* 24 - 87 CIU_INT_SUM0 */
444         for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
445                 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
446                                          handle_percpu_irq);
447         }
448
449         /* 88 - 151 CIU_INT_SUM1 */
450         for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
451                 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
452                                          handle_percpu_irq);
453         }
454
455 #ifdef CONFIG_PCI_MSI
456         /* 152 - 215 PCI/PCIe MSI interrupts */
457         for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
458                 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
459                                          handle_percpu_irq);
460         }
461 #endif
462         set_c0_status(0x300 << 2);
463 }
464
465 asmlinkage void plat_irq_dispatch(void)
466 {
467         const unsigned long core_id = cvmx_get_core_num();
468         const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
469         const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
470         const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
471         const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
472         unsigned long cop0_cause;
473         unsigned long cop0_status;
474         uint64_t ciu_en;
475         uint64_t ciu_sum;
476
477         while (1) {
478                 cop0_cause = read_c0_cause();
479                 cop0_status = read_c0_status();
480                 cop0_cause &= cop0_status;
481                 cop0_cause &= ST0_IM;
482
483                 if (unlikely(cop0_cause & STATUSF_IP2)) {
484                         ciu_sum = cvmx_read_csr(ciu_sum0_address);
485                         ciu_en = cvmx_read_csr(ciu_en0_address);
486                         ciu_sum &= ciu_en;
487                         if (likely(ciu_sum))
488                                 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
489                         else
490                                 spurious_interrupt();
491                 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
492                         ciu_sum = cvmx_read_csr(ciu_sum1_address);
493                         ciu_en = cvmx_read_csr(ciu_en1_address);
494                         ciu_sum &= ciu_en;
495                         if (likely(ciu_sum))
496                                 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
497                         else
498                                 spurious_interrupt();
499                 } else if (likely(cop0_cause)) {
500                         do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
501                 } else {
502                         break;
503                 }
504         }
505 }
506
507 #ifdef CONFIG_HOTPLUG_CPU
508 static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
509 {
510        unsigned int isset;
511 #ifdef CONFIG_SMP
512        int coreid = cpu_logical_map(cpu);
513 #else
514         int coreid = cvmx_get_core_num();
515 #endif
516         int bit = (irq < OCTEON_IRQ_WDOG0) ?
517                 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
518        if (irq < 64) {
519                 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
520                         (1ull << bit)) >> bit;
521        } else {
522                isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
523                         (1ull << bit)) >> bit;
524        }
525        return isset;
526 }
527
528 void fixup_irqs(void)
529 {
530        int irq;
531
532         for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
533                 octeon_irq_core_disable_local(irq);
534
535         for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
536                 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
537                         /* ciu irq migrates to next cpu */
538                         octeon_irq_chip_ciu0.disable(irq);
539                         octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
540                 }
541         }
542
543 #if 0
544         for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
545                 octeon_irq_mailbox_mask(irq);
546 #endif
547         for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
548                 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
549                         /* ciu irq migrates to next cpu */
550                         octeon_irq_chip_ciu0.disable(irq);
551                         octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
552                 }
553         }
554
555         for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
556                 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
557                         /* ciu irq migrates to next cpu */
558                         octeon_irq_chip_ciu1.disable(irq);
559                         octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
560                 }
561         }
562 }
563
564 #endif /* CONFIG_HOTPLUG_CPU */