Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-next-2.6
[linux-2.6.git] / arch / mips / bcm63xx / cpu.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8  */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/cpu.h>
13 #include <asm/cpu-info.h>
14 #include <bcm63xx_cpu.h>
15 #include <bcm63xx_regs.h>
16 #include <bcm63xx_io.h>
17 #include <bcm63xx_irq.h>
18
19 const unsigned long *bcm63xx_regs_base;
20 EXPORT_SYMBOL(bcm63xx_regs_base);
21
22 const int *bcm63xx_irqs;
23 EXPORT_SYMBOL(bcm63xx_irqs);
24
25 static u16 bcm63xx_cpu_id;
26 static u16 bcm63xx_cpu_rev;
27 static unsigned int bcm63xx_cpu_freq;
28 static unsigned int bcm63xx_memory_size;
29
30 /*
31  * 6338 register sets and irqs
32  */
33 static const unsigned long bcm96338_regs_base[] = {
34         [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
35         [RSET_PERF]             = BCM_6338_PERF_BASE,
36         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
37         [RSET_WDT]              = BCM_6338_WDT_BASE,
38         [RSET_UART0]            = BCM_6338_UART0_BASE,
39         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
40         [RSET_SPI]              = BCM_6338_SPI_BASE,
41         [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
42         [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
43         [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
44         [RSET_UDC0]             = BCM_6338_UDC0_BASE,
45         [RSET_MPI]              = BCM_6338_MPI_BASE,
46         [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
47         [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
48         [RSET_DSL]              = BCM_6338_DSL_BASE,
49         [RSET_ENET0]            = BCM_6338_ENET0_BASE,
50         [RSET_ENET1]            = BCM_6338_ENET1_BASE,
51         [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
52         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
53         [RSET_DDR]              = BCM_6338_DDR_BASE,
54 };
55
56 static const int bcm96338_irqs[] = {
57         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
58         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
59         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
60         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
61         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
62         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
63         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
64 };
65
66 /*
67  * 6345 register sets and irqs
68  */
69 static const unsigned long bcm96345_regs_base[] = {
70         [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
71         [RSET_PERF]             = BCM_6345_PERF_BASE,
72         [RSET_TIMER]            = BCM_6345_TIMER_BASE,
73         [RSET_WDT]              = BCM_6345_WDT_BASE,
74         [RSET_UART0]            = BCM_6345_UART0_BASE,
75         [RSET_GPIO]             = BCM_6345_GPIO_BASE,
76         [RSET_SPI]              = BCM_6345_SPI_BASE,
77         [RSET_UDC0]             = BCM_6345_UDC0_BASE,
78         [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
79         [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
80         [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
81         [RSET_MPI]              = BCM_6345_MPI_BASE,
82         [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
83         [RSET_DSL]              = BCM_6345_DSL_BASE,
84         [RSET_ENET0]            = BCM_6345_ENET0_BASE,
85         [RSET_ENET1]            = BCM_6345_ENET1_BASE,
86         [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
87         [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
88         [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
89         [RSET_MEMC]             = BCM_6345_MEMC_BASE,
90         [RSET_DDR]              = BCM_6345_DDR_BASE,
91 };
92
93 static const int bcm96345_irqs[] = {
94         [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
95         [IRQ_UART0]             = BCM_6345_UART0_IRQ,
96         [IRQ_DSL]               = BCM_6345_DSL_IRQ,
97         [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
98         [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
99         [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
100         [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
101 };
102
103 /*
104  * 6348 register sets and irqs
105  */
106 static const unsigned long bcm96348_regs_base[] = {
107         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
108         [RSET_PERF]             = BCM_6348_PERF_BASE,
109         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
110         [RSET_WDT]              = BCM_6348_WDT_BASE,
111         [RSET_UART0]            = BCM_6348_UART0_BASE,
112         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
113         [RSET_SPI]              = BCM_6348_SPI_BASE,
114         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
115         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
116         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
117         [RSET_MPI]              = BCM_6348_MPI_BASE,
118         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
119         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
120         [RSET_DSL]              = BCM_6348_DSL_BASE,
121         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
122         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
123         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
124         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
125         [RSET_DDR]              = BCM_6348_DDR_BASE,
126 };
127
128 static const int bcm96348_irqs[] = {
129         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
130         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
131         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
132         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
133         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
134         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
135         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
136         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
137         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
138         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
139         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
140         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
141         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
142 };
143
144 /*
145  * 6358 register sets and irqs
146  */
147 static const unsigned long bcm96358_regs_base[] = {
148         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
149         [RSET_PERF]             = BCM_6358_PERF_BASE,
150         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
151         [RSET_WDT]              = BCM_6358_WDT_BASE,
152         [RSET_UART0]            = BCM_6358_UART0_BASE,
153         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
154         [RSET_SPI]              = BCM_6358_SPI_BASE,
155         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
156         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
157         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
158         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
159         [RSET_MPI]              = BCM_6358_MPI_BASE,
160         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
161         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
162         [RSET_DSL]              = BCM_6358_DSL_BASE,
163         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
164         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
165         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
166         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
167         [RSET_DDR]              = BCM_6358_DDR_BASE,
168 };
169
170 static const int bcm96358_irqs[] = {
171         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
172         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
173         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
174         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
175         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
176         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
177         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
178         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
179         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
180         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
181         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
182         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
183         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
184         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
185 };
186
187 u16 __bcm63xx_get_cpu_id(void)
188 {
189         return bcm63xx_cpu_id;
190 }
191
192 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
193
194 u16 bcm63xx_get_cpu_rev(void)
195 {
196         return bcm63xx_cpu_rev;
197 }
198
199 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
200
201 unsigned int bcm63xx_get_cpu_freq(void)
202 {
203         return bcm63xx_cpu_freq;
204 }
205
206 unsigned int bcm63xx_get_memory_size(void)
207 {
208         return bcm63xx_memory_size;
209 }
210
211 static unsigned int detect_cpu_clock(void)
212 {
213         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
214
215         /* BCM6338 has a fixed 240 Mhz frequency */
216         if (BCMCPU_IS_6338())
217                 return 240000000;
218
219         /* BCM6345 has a fixed 140Mhz frequency */
220         if (BCMCPU_IS_6345())
221                 return 140000000;
222
223         /*
224          * frequency depends on PLL configuration:
225          */
226         if (BCMCPU_IS_6348()) {
227                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
228                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
229                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
230                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
231                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
232                 n1 += 1;
233                 n2 += 2;
234                 m1 += 1;
235         }
236
237         if (BCMCPU_IS_6358()) {
238                 /* 16MHz * N1 * N2 / M1_CPU */
239                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
240                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
241                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
242                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
243         }
244
245         return (16 * 1000000 * n1 * n2) / m1;
246 }
247
248 /*
249  * attempt to detect the amount of memory installed
250  */
251 static unsigned int detect_memory_size(void)
252 {
253         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
254         u32 val;
255
256         if (BCMCPU_IS_6345())
257                 return (8 * 1024 * 1024);
258
259         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
260                 val = bcm_sdram_readl(SDRAM_CFG_REG);
261                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
262                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
263                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
264                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
265         }
266
267         if (BCMCPU_IS_6358()) {
268                 val = bcm_memc_readl(MEMC_CFG_REG);
269                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
270                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
271                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
272                 banks = 2;
273         }
274
275         /* 0 => 11 address bits ... 2 => 13 address bits */
276         rows += 11;
277
278         /* 0 => 8 address bits ... 2 => 10 address bits */
279         cols += 8;
280
281         return 1 << (cols + rows + (is_32bits + 1) + banks);
282 }
283
284 void __init bcm63xx_cpu_init(void)
285 {
286         unsigned int tmp, expected_cpu_id;
287         struct cpuinfo_mips *c = &current_cpu_data;
288         unsigned int cpu = smp_processor_id();
289
290         /* soc registers location depends on cpu type */
291         expected_cpu_id = 0;
292
293         switch (c->cputype) {
294         /*
295          * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
296          */
297         case CPU_BCM3302:
298                 __cpu_name[cpu] = "Broadcom BCM6338";
299                 expected_cpu_id = BCM6338_CPU_ID;
300                 bcm63xx_regs_base = bcm96338_regs_base;
301                 bcm63xx_irqs = bcm96338_irqs;
302                 break;
303         case CPU_BCM6345:
304                 expected_cpu_id = BCM6345_CPU_ID;
305                 bcm63xx_regs_base = bcm96345_regs_base;
306                 bcm63xx_irqs = bcm96345_irqs;
307                 break;
308         case CPU_BCM6348:
309                 expected_cpu_id = BCM6348_CPU_ID;
310                 bcm63xx_regs_base = bcm96348_regs_base;
311                 bcm63xx_irqs = bcm96348_irqs;
312                 break;
313         case CPU_BCM6358:
314                 expected_cpu_id = BCM6358_CPU_ID;
315                 bcm63xx_regs_base = bcm96358_regs_base;
316                 bcm63xx_irqs = bcm96358_irqs;
317                 break;
318         }
319
320         /*
321          * really early to panic, but delaying panic would not help since we
322          * will never get any working console
323          */
324         if (!expected_cpu_id)
325                 panic("unsupported Broadcom CPU");
326
327         /*
328          * bcm63xx_regs_base is set, we can access soc registers
329          */
330
331         /* double check CPU type */
332         tmp = bcm_perf_readl(PERF_REV_REG);
333         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
334         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
335
336         if (bcm63xx_cpu_id != expected_cpu_id)
337                 panic("bcm63xx CPU id mismatch");
338
339         bcm63xx_cpu_freq = detect_cpu_clock();
340         bcm63xx_memory_size = detect_memory_size();
341
342         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
343                bcm63xx_cpu_id, bcm63xx_cpu_rev);
344         printk(KERN_INFO "CPU frequency is %u MHz\n",
345                bcm63xx_cpu_freq / 1000000);
346         printk(KERN_INFO "%uMB of RAM installed\n",
347                bcm63xx_memory_size >> 20);
348 }