[MIPS] Simple patch to power off DBAU1200
[linux-2.6.git] / arch / mips / au1000 / common / reset.c
1 /*
2  *
3  * BRIEF MODULE DESCRIPTION
4  *      Au1000 reset routines.
5  *
6  * Copyright 2001 MontaVista Software Inc.
7  * Author: MontaVista Software, Inc.
8  *              ppopov@mvista.com or source@mvista.com
9  *
10  *  This program is free software; you can redistribute  it and/or modify it
11  *  under  the terms of  the GNU General  Public License as published by the
12  *  Free Software Foundation;  either version 2 of the  License, or (at your
13  *  option) any later version.
14  *
15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  *  You should have received a copy of the  GNU General Public License along
27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
28  *  675 Mass Ave, Cambridge, MA 02139, USA.
29  */
30 #include <linux/config.h>
31 #include <linux/sched.h>
32 #include <linux/mm.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/processor.h>
36 #include <asm/reboot.h>
37 #include <asm/system.h>
38 #include <asm/mach-au1x00/au1000.h>
39
40 extern int au_sleep(void);
41 extern void (*flush_cache_all)(void);
42
43 void au1000_restart(char *command)
44 {
45         /* Set all integrated peripherals to disabled states */
46         extern void board_reset (void);
47         u32 prid = read_c0_prid();
48
49         printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
50         switch (prid & 0xFF000000)
51         {
52         case 0x00000000: /* Au1000 */
53                 au_writel(0x02, 0xb0000010); /* ac97_enable */
54                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
55                 asm("sync");
56                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
57                 au_writel(0x00, 0xb0200058); /* usbd_enable */
58                 au_writel(0x00, 0xb0300040); /* ir_enable */
59                 au_writel(0x00, 0xb4004104); /* mac dma */
60                 au_writel(0x00, 0xb4004114); /* mac dma */
61                 au_writel(0x00, 0xb4004124); /* mac dma */
62                 au_writel(0x00, 0xb4004134); /* mac dma */
63                 au_writel(0x00, 0xb0520000); /* macen0 */
64                 au_writel(0x00, 0xb0520004); /* macen1 */
65                 au_writel(0x00, 0xb1000008); /* i2s_enable  */
66                 au_writel(0x00, 0xb1100100); /* uart0_enable */
67                 au_writel(0x00, 0xb1200100); /* uart1_enable */
68                 au_writel(0x00, 0xb1300100); /* uart2_enable */
69                 au_writel(0x00, 0xb1400100); /* uart3_enable */
70                 au_writel(0x02, 0xb1600100); /* ssi0_enable */
71                 au_writel(0x02, 0xb1680100); /* ssi1_enable */
72                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
73                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
74                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
75                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
76                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
77                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
78                 break;
79         case 0x01000000: /* Au1500 */
80                 au_writel(0x02, 0xb0000010); /* ac97_enable */
81                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
82                 asm("sync");
83                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
84                 au_writel(0x00, 0xb0200058); /* usbd_enable */
85                 au_writel(0x00, 0xb4004104); /* mac dma */
86                 au_writel(0x00, 0xb4004114); /* mac dma */
87                 au_writel(0x00, 0xb4004124); /* mac dma */
88                 au_writel(0x00, 0xb4004134); /* mac dma */
89                 au_writel(0x00, 0xb1520000); /* macen0 */
90                 au_writel(0x00, 0xb1520004); /* macen1 */
91                 au_writel(0x00, 0xb1100100); /* uart0_enable */
92                 au_writel(0x00, 0xb1400100); /* uart3_enable */
93                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
94                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
95                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
96                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
97                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
98                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
99                 break;
100         case 0x02000000: /* Au1100 */
101                 au_writel(0x02, 0xb0000010); /* ac97_enable */
102                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
103                 asm("sync");
104                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
105                 au_writel(0x00, 0xb0200058); /* usbd_enable */
106                 au_writel(0x00, 0xb0300040); /* ir_enable */
107                 au_writel(0x00, 0xb4004104); /* mac dma */
108                 au_writel(0x00, 0xb4004114); /* mac dma */
109                 au_writel(0x00, 0xb4004124); /* mac dma */
110                 au_writel(0x00, 0xb4004134); /* mac dma */
111                 au_writel(0x00, 0xb0520000); /* macen0 */
112                 au_writel(0x00, 0xb1000008); /* i2s_enable  */
113                 au_writel(0x00, 0xb1100100); /* uart0_enable */
114                 au_writel(0x00, 0xb1200100); /* uart1_enable */
115                 au_writel(0x00, 0xb1400100); /* uart3_enable */
116                 au_writel(0x02, 0xb1600100); /* ssi0_enable */
117                 au_writel(0x02, 0xb1680100); /* ssi1_enable */
118                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
119                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
120                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
121                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
122                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
123                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
124                 break;
125         case 0x03000000: /* Au1550 */
126                 au_writel(0x00, 0xb1a00004); /* psc 0 */
127                 au_writel(0x00, 0xb1b00004); /* psc 1 */
128                 au_writel(0x00, 0xb0a00004); /* psc 2 */
129                 au_writel(0x00, 0xb0b00004); /* psc 3 */
130                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
131                 au_writel(0x00, 0xb0200058); /* usbd_enable */
132                 au_writel(0x00, 0xb4004104); /* mac dma */
133                 au_writel(0x00, 0xb4004114); /* mac dma */
134                 au_writel(0x00, 0xb4004124); /* mac dma */
135                 au_writel(0x00, 0xb4004134); /* mac dma */
136                 au_writel(0x00, 0xb1520000); /* macen0 */
137                 au_writel(0x00, 0xb1520004); /* macen1 */
138                 au_writel(0x00, 0xb1100100); /* uart0_enable */
139                 au_writel(0x00, 0xb1200100); /* uart1_enable */
140                 au_writel(0x00, 0xb1400100); /* uart3_enable */
141                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
142                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
143                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
144                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
145                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
146                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
147                 break;
148
149         default:
150                 break;
151         }
152
153         set_c0_status(ST0_BEV | ST0_ERL);
154         change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
155         flush_cache_all();
156         write_c0_wired(0);
157
158         /* Give board a chance to do a hardware reset */
159         board_reset();
160
161         /* Jump to the beggining in case board_reset() is empty */
162         __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
163 }
164
165 void au1000_halt(void)
166 {
167 #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
168         /* power off system */
169         printk("\n** Powering off...\n");
170         au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
171         au_sync();
172         while(1); /* should not get here */
173 #else
174         printk(KERN_NOTICE "\n** You can safely turn off the power\n");
175 #ifdef CONFIG_MIPS_MIRAGE
176         au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
177 #endif
178 #ifdef CONFIG_MIPS_DB1200
179         au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
180 #endif
181 #ifdef CONFIG_PM
182         au_sleep();
183
184         /* should not get here */
185         printk(KERN_ERR "Unable to put cpu in sleep mode\n");
186         while(1);
187 #else
188         while (1)
189                 __asm__(".set\tmips3\n\t"
190                         "wait\n\t"
191                         ".set\tmips0");
192 #endif
193 #endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
194 }
195
196 void au1000_power_off(void)
197 {
198         au1000_halt();
199 }