2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/delay.h>
27 #include <linux/gpio.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <asm/mach-au1x00/au1000.h>
32 #include <asm/mach-db1x00/bcsr.h>
37 char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
43 const char *get_system_type(void)
45 return "Alchemy Pb1500";
48 void board_reset(void)
50 bcsr_write(BCSR_SYSTEM, 0);
53 void __init board_setup(void)
56 u32 sys_freqctrl, sys_clksrc;
58 bcsr_init(DB1000_BCSR_PHYS_ADDR,
59 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
61 sys_clksrc = sys_freqctrl = pin_func = 0;
62 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
63 au_writel(8, SYS_AUXPLL);
64 au_writel(0, SYS_PINSTATERD);
67 /* GPIO201 is input for PCMCIA card detect */
68 /* GPIO203 is input for PCMCIA interrupt request */
69 alchemy_gpio_direction_input(201);
70 alchemy_gpio_direction_input(203);
72 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
74 /* Zero and disable FREQ2 */
75 sys_freqctrl = au_readl(SYS_FREQCTRL0);
76 sys_freqctrl &= ~0xFFF00000;
77 au_writel(sys_freqctrl, SYS_FREQCTRL0);
79 /* zero and disable USBH/USBD clocks */
80 sys_clksrc = au_readl(SYS_CLKSRC);
81 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
82 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
83 au_writel(sys_clksrc, SYS_CLKSRC);
85 sys_freqctrl = au_readl(SYS_FREQCTRL0);
86 sys_freqctrl &= ~0xFFF00000;
88 sys_clksrc = au_readl(SYS_CLKSRC);
89 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
90 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
92 /* FREQ2 = aux/2 = 48 MHz */
93 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
94 au_writel(sys_freqctrl, SYS_FREQCTRL0);
97 * Route 48MHz FREQ2 into USB Host and/or Device
99 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
100 au_writel(sys_clksrc, SYS_CLKSRC);
102 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
103 /* 2nd USB port is USB host */
104 pin_func |= SYS_PF_USB;
105 au_writel(pin_func, SYS_PINFUNC);
106 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
109 /* Setup PCI bus controller */
110 au_writel(0, Au1500_PCI_CMEM);
111 au_writel(0x00003fff, Au1500_CFG_BASE);
112 #if defined(__MIPSEB__)
113 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
115 au_writel(0xf, Au1500_PCI_CFG);
117 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
118 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
119 au_writel(0x02a00356, Au1500_PCI_STATCMD);
120 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
121 au_writel(0x00000008, Au1500_PCI_MBAR);
125 /* Enable sys bus clock divider when IDLE state or no bus activity. */
126 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
128 /* Enable the RTC if not already enabled */
129 if (!(au_readl(0xac000028) & 0x20)) {
130 printk(KERN_INFO "enabling clock ...\n");
131 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
133 /* Put the clock in BCD mode */
134 if (au_readl(0xac00002c) & 0x4) { /* reg B */
135 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
140 static int __init pb1500_init_irq(void)
142 set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
143 set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
144 set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
145 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
146 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
147 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
148 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
149 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
153 arch_initcall(pb1500_init_irq);