Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / arch / m32r / platforms / m32700ut / setup.c
1 /*
2  *  linux/arch/m32r/platforms/m32700ut/setup.c
3  *
4  *  Setup routines for Renesas M32700UT Board
5  *
6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto, Takeo Takahashi
8  *
9  *  This file is subject to the terms and conditions of the GNU General
10  *  Public License.  See the file "COPYING" in the main directory of this
11  *  archive for more details.
12  */
13
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18
19 #include <asm/system.h>
20 #include <asm/m32r.h>
21 #include <asm/io.h>
22
23 /*
24  * M32700 Interrupt Control Unit (Level 1)
25  */
26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
27
28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
29
30 static void disable_m32700ut_irq(unsigned int irq)
31 {
32         unsigned long port, data;
33
34         port = irq2port(irq);
35         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
36         outl(data, port);
37 }
38
39 static void enable_m32700ut_irq(unsigned int irq)
40 {
41         unsigned long port, data;
42
43         port = irq2port(irq);
44         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
45         outl(data, port);
46 }
47
48 static void mask_and_ack_m32700ut(unsigned int irq)
49 {
50         disable_m32700ut_irq(irq);
51 }
52
53 static void end_m32700ut_irq(unsigned int irq)
54 {
55         enable_m32700ut_irq(irq);
56 }
57
58 static unsigned int startup_m32700ut_irq(unsigned int irq)
59 {
60         enable_m32700ut_irq(irq);
61         return (0);
62 }
63
64 static void shutdown_m32700ut_irq(unsigned int irq)
65 {
66         unsigned long port;
67
68         port = irq2port(irq);
69         outl(M32R_ICUCR_ILEVEL7, port);
70 }
71
72 static struct irq_chip m32700ut_irq_type =
73 {
74         .typename = "M32700UT-IRQ",
75         .startup = startup_m32700ut_irq,
76         .shutdown = shutdown_m32700ut_irq,
77         .enable = enable_m32700ut_irq,
78         .disable = disable_m32700ut_irq,
79         .ack = mask_and_ack_m32700ut,
80         .end = end_m32700ut_irq
81 };
82
83 /*
84  * Interrupt Control Unit of PLD on M32700UT (Level 2)
85  */
86 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
87 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
88                                  (((x) - 1) * sizeof(unsigned short)))
89
90 typedef struct {
91         unsigned short icucr;  /* ICU Control Register */
92 } pld_icu_data_t;
93
94 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
95
96 static void disable_m32700ut_pld_irq(unsigned int irq)
97 {
98         unsigned long port, data;
99         unsigned int pldirq;
100
101         pldirq = irq2pldirq(irq);
102 //      disable_m32700ut_irq(M32R_IRQ_INT1);
103         port = pldirq2port(pldirq);
104         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
105         outw(data, port);
106 }
107
108 static void enable_m32700ut_pld_irq(unsigned int irq)
109 {
110         unsigned long port, data;
111         unsigned int pldirq;
112
113         pldirq = irq2pldirq(irq);
114 //      enable_m32700ut_irq(M32R_IRQ_INT1);
115         port = pldirq2port(pldirq);
116         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
117         outw(data, port);
118 }
119
120 static void mask_and_ack_m32700ut_pld(unsigned int irq)
121 {
122         disable_m32700ut_pld_irq(irq);
123 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
124 }
125
126 static void end_m32700ut_pld_irq(unsigned int irq)
127 {
128         enable_m32700ut_pld_irq(irq);
129         end_m32700ut_irq(M32R_IRQ_INT1);
130 }
131
132 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
133 {
134         enable_m32700ut_pld_irq(irq);
135         return (0);
136 }
137
138 static void shutdown_m32700ut_pld_irq(unsigned int irq)
139 {
140         unsigned long port;
141         unsigned int pldirq;
142
143         pldirq = irq2pldirq(irq);
144 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
145         port = pldirq2port(pldirq);
146         outw(PLD_ICUCR_ILEVEL7, port);
147 }
148
149 static struct irq_chip m32700ut_pld_irq_type =
150 {
151         .typename = "M32700UT-PLD-IRQ",
152         .startup = startup_m32700ut_pld_irq,
153         .shutdown = shutdown_m32700ut_pld_irq,
154         .enable = enable_m32700ut_pld_irq,
155         .disable = disable_m32700ut_pld_irq,
156         .ack = mask_and_ack_m32700ut_pld,
157         .end = end_m32700ut_pld_irq
158 };
159
160 /*
161  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
162  */
163 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
164 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
165                                  (((x) - 1) * sizeof(unsigned short)))
166
167 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
168
169 static void disable_m32700ut_lanpld_irq(unsigned int irq)
170 {
171         unsigned long port, data;
172         unsigned int pldirq;
173
174         pldirq = irq2lanpldirq(irq);
175         port = lanpldirq2port(pldirq);
176         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
177         outw(data, port);
178 }
179
180 static void enable_m32700ut_lanpld_irq(unsigned int irq)
181 {
182         unsigned long port, data;
183         unsigned int pldirq;
184
185         pldirq = irq2lanpldirq(irq);
186         port = lanpldirq2port(pldirq);
187         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
188         outw(data, port);
189 }
190
191 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
192 {
193         disable_m32700ut_lanpld_irq(irq);
194 }
195
196 static void end_m32700ut_lanpld_irq(unsigned int irq)
197 {
198         enable_m32700ut_lanpld_irq(irq);
199         end_m32700ut_irq(M32R_IRQ_INT0);
200 }
201
202 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
203 {
204         enable_m32700ut_lanpld_irq(irq);
205         return (0);
206 }
207
208 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
209 {
210         unsigned long port;
211         unsigned int pldirq;
212
213         pldirq = irq2lanpldirq(irq);
214         port = lanpldirq2port(pldirq);
215         outw(PLD_ICUCR_ILEVEL7, port);
216 }
217
218 static struct irq_chip m32700ut_lanpld_irq_type =
219 {
220         .typename = "M32700UT-PLD-LAN-IRQ",
221         .startup = startup_m32700ut_lanpld_irq,
222         .shutdown = shutdown_m32700ut_lanpld_irq,
223         .enable = enable_m32700ut_lanpld_irq,
224         .disable = disable_m32700ut_lanpld_irq,
225         .ack = mask_and_ack_m32700ut_lanpld,
226         .end = end_m32700ut_lanpld_irq
227 };
228
229 /*
230  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
231  */
232 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
233 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
234                                  (((x) - 1) * sizeof(unsigned short)))
235
236 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
237
238 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
239 {
240         unsigned long port, data;
241         unsigned int pldirq;
242
243         pldirq = irq2lcdpldirq(irq);
244         port = lcdpldirq2port(pldirq);
245         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
246         outw(data, port);
247 }
248
249 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
250 {
251         unsigned long port, data;
252         unsigned int pldirq;
253
254         pldirq = irq2lcdpldirq(irq);
255         port = lcdpldirq2port(pldirq);
256         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
257         outw(data, port);
258 }
259
260 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
261 {
262         disable_m32700ut_lcdpld_irq(irq);
263 }
264
265 static void end_m32700ut_lcdpld_irq(unsigned int irq)
266 {
267         enable_m32700ut_lcdpld_irq(irq);
268         end_m32700ut_irq(M32R_IRQ_INT2);
269 }
270
271 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
272 {
273         enable_m32700ut_lcdpld_irq(irq);
274         return (0);
275 }
276
277 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
278 {
279         unsigned long port;
280         unsigned int pldirq;
281
282         pldirq = irq2lcdpldirq(irq);
283         port = lcdpldirq2port(pldirq);
284         outw(PLD_ICUCR_ILEVEL7, port);
285 }
286
287 static struct irq_chip m32700ut_lcdpld_irq_type =
288 {
289         .typename = "M32700UT-PLD-LCD-IRQ",
290         .startup = startup_m32700ut_lcdpld_irq,
291         .shutdown = shutdown_m32700ut_lcdpld_irq,
292         .enable = enable_m32700ut_lcdpld_irq,
293         .disable = disable_m32700ut_lcdpld_irq,
294         .ack = mask_and_ack_m32700ut_lcdpld,
295         .end = end_m32700ut_lcdpld_irq
296 };
297
298 void __init init_IRQ(void)
299 {
300 #if defined(CONFIG_SMC91X)
301         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
302         irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
303         irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
304         irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
305         irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;       /* disable nested irq */
306         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
307         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
308 #endif  /* CONFIG_SMC91X */
309
310         /* MFT2 : system timer */
311         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
312         irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
313         irq_desc[M32R_IRQ_MFT2].action = 0;
314         irq_desc[M32R_IRQ_MFT2].depth = 1;
315         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
316         disable_m32700ut_irq(M32R_IRQ_MFT2);
317
318         /* SIO0 : receive */
319         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
320         irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
321         irq_desc[M32R_IRQ_SIO0_R].action = 0;
322         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
323         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
324         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
325
326         /* SIO0 : send */
327         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
328         irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
329         irq_desc[M32R_IRQ_SIO0_S].action = 0;
330         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
331         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
332         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
333
334         /* SIO1 : receive */
335         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
336         irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
337         irq_desc[M32R_IRQ_SIO1_R].action = 0;
338         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
339         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
340         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
341
342         /* SIO1 : send */
343         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
344         irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
345         irq_desc[M32R_IRQ_SIO1_S].action = 0;
346         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
347         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
348         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
349
350         /* DMA1 : */
351         irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
352         irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
353         irq_desc[M32R_IRQ_DMA1].action = 0;
354         irq_desc[M32R_IRQ_DMA1].depth = 1;
355         icu_data[M32R_IRQ_DMA1].icucr = 0;
356         disable_m32700ut_irq(M32R_IRQ_DMA1);
357
358 #ifdef CONFIG_SERIAL_M32R_PLDSIO
359         /* INT#1: SIO0 Receive on PLD */
360         irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
361         irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
362         irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
363         irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;   /* disable nested irq */
364         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
365         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
366
367         /* INT#1: SIO0 Send on PLD */
368         irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
369         irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
370         irq_desc[PLD_IRQ_SIO0_SND].action = 0;
371         irq_desc[PLD_IRQ_SIO0_SND].depth = 1;   /* disable nested irq */
372         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
373         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
374 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
375
376         /* INT#1: CFC IREQ on PLD */
377         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
378         irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
379         irq_desc[PLD_IRQ_CFIREQ].action = 0;
380         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
381         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
382         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
383
384         /* INT#1: CFC Insert on PLD */
385         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
386         irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
387         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
388         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
389         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
390         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
391
392         /* INT#1: CFC Eject on PLD */
393         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
394         irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
395         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
396         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
397         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
398         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
399
400         /*
401          * INT0# is used for LAN, DIO
402          * We enable it here.
403          */
404         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
405         enable_m32700ut_irq(M32R_IRQ_INT0);
406
407         /*
408          * INT1# is used for UART, MMC, CF Controller in FPGA.
409          * We enable it here.
410          */
411         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
412         enable_m32700ut_irq(M32R_IRQ_INT1);
413
414 #if defined(CONFIG_USB)
415         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
416
417     irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
418     irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
419     irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
420     irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
421     lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;  /* "L" level sense */
422     disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
423 #endif
424         /*
425          * INT2# is used for BAT, USB, AUDIO
426          * We enable it here.
427          */
428         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
429         enable_m32700ut_irq(M32R_IRQ_INT2);
430
431 #if defined(CONFIG_VIDEO_M32R_AR)
432         /*
433          * INT3# is used for AR
434          */
435         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
436         irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
437         irq_desc[M32R_IRQ_INT3].action = 0;
438         irq_desc[M32R_IRQ_INT3].depth = 1;
439         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
440         disable_m32700ut_irq(M32R_IRQ_INT3);
441 #endif  /* CONFIG_VIDEO_M32R_AR */
442 }
443
444 #if defined(CONFIG_SMC91X)
445
446 #define LAN_IOSTART     0x300
447 #define LAN_IOEND       0x320
448 static struct resource smc91x_resources[] = {
449         [0] = {
450                 .start  = (LAN_IOSTART),
451                 .end    = (LAN_IOEND),
452                 .flags  = IORESOURCE_MEM,
453         },
454         [1] = {
455                 .start  = M32700UT_LAN_IRQ_LAN,
456                 .end    = M32700UT_LAN_IRQ_LAN,
457                 .flags  = IORESOURCE_IRQ,
458         }
459 };
460
461 static struct platform_device smc91x_device = {
462         .name           = "smc91x",
463         .id             = 0,
464         .num_resources  = ARRAY_SIZE(smc91x_resources),
465         .resource       = smc91x_resources,
466 };
467 #endif
468
469 #if defined(CONFIG_FB_S1D13XXX)
470
471 #include <video/s1d13xxxfb.h>
472 #include <asm/s1d13806.h>
473
474 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
475         .initregs               = s1d13xxxfb_initregs,
476         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
477         .platform_init_video    = NULL,
478 #ifdef CONFIG_PM
479         .platform_suspend_video = NULL,
480         .platform_resume_video  = NULL,
481 #endif
482 };
483
484 static struct resource s1d13xxxfb_resources[] = {
485         [0] = {
486                 .start  = 0x10600000UL,
487                 .end    = 0x1073FFFFUL,
488                 .flags  = IORESOURCE_MEM,
489         },
490         [1] = {
491                 .start  = 0x10400000UL,
492                 .end    = 0x104001FFUL,
493                 .flags  = IORESOURCE_MEM,
494         }
495 };
496
497 static struct platform_device s1d13xxxfb_device = {
498         .name           = S1D_DEVICENAME,
499         .id             = 0,
500         .dev            = {
501                 .platform_data  = &s1d13xxxfb_data,
502         },
503         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
504         .resource       = s1d13xxxfb_resources,
505 };
506 #endif
507
508 static int __init platform_init(void)
509 {
510 #if defined(CONFIG_SMC91X)
511         platform_device_register(&smc91x_device);
512 #endif
513 #if defined(CONFIG_FB_S1D13XXX)
514         platform_device_register(&s1d13xxxfb_device);
515 #endif
516         return 0;
517 }
518 arch_initcall(platform_init);