m32r: Convert m32700ut pld irq chip
[linux-2.6.git] / arch / m32r / platforms / m32700ut / setup.c
1 /*
2  *  linux/arch/m32r/platforms/m32700ut/setup.c
3  *
4  *  Setup routines for Renesas M32700UT Board
5  *
6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto, Takeo Takahashi
8  *
9  *  This file is subject to the terms and conditions of the GNU General
10  *  Public License.  See the file "COPYING" in the main directory of this
11  *  archive for more details.
12  */
13
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18
19 #include <asm/system.h>
20 #include <asm/m32r.h>
21 #include <asm/io.h>
22
23 /*
24  * M32700 Interrupt Control Unit (Level 1)
25  */
26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
27
28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
29
30 static void disable_m32700ut_irq(unsigned int irq)
31 {
32         unsigned long port, data;
33
34         port = irq2port(irq);
35         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
36         outl(data, port);
37 }
38
39 static void enable_m32700ut_irq(unsigned int irq)
40 {
41         unsigned long port, data;
42
43         port = irq2port(irq);
44         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
45         outl(data, port);
46 }
47
48 static void mask_m32700ut(struct irq_data *data)
49 {
50         disable_m32700ut_irq(data->irq);
51 }
52
53 static void unmask_m32700ut(struct irq_data *data)
54 {
55         enable_m32700ut_irq(data->irq);
56 }
57
58 static void shutdown_m32700ut(struct irq_data *data)
59 {
60         unsigned long port;
61
62         port = irq2port(data->irq);
63         outl(M32R_ICUCR_ILEVEL7, port);
64 }
65
66 static struct irq_chip m32700ut_irq_type =
67 {
68         .name           = "M32700UT-IRQ",
69         .irq_shutdown   = shutdown_m32700ut,
70         .irq_mask       = mask_m32700ut,
71         .irq_unmask     = unmask_m32700ut
72 };
73
74 /*
75  * Interrupt Control Unit of PLD on M32700UT (Level 2)
76  */
77 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
78 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
79                                  (((x) - 1) * sizeof(unsigned short)))
80
81 typedef struct {
82         unsigned short icucr;  /* ICU Control Register */
83 } pld_icu_data_t;
84
85 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
86
87 static void disable_m32700ut_pld_irq(unsigned int irq)
88 {
89         unsigned long port, data;
90         unsigned int pldirq;
91
92         pldirq = irq2pldirq(irq);
93         port = pldirq2port(pldirq);
94         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
95         outw(data, port);
96 }
97
98 static void enable_m32700ut_pld_irq(unsigned int irq)
99 {
100         unsigned long port, data;
101         unsigned int pldirq;
102
103         pldirq = irq2pldirq(irq);
104         port = pldirq2port(pldirq);
105         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
106         outw(data, port);
107 }
108
109 static void mask_m32700ut_pld(struct irq_data *data)
110 {
111         disable_m32700ut_pld_irq(data->irq);
112 }
113
114 static void unmask_m32700ut_pld(struct irq_data *data)
115 {
116         enable_m32700ut_pld_irq(data->irq);
117         enable_m32700ut_irq(M32R_IRQ_INT1);
118 }
119
120 static void shutdown_m32700ut_pld_irq(struct irq_data *data)
121 {
122         unsigned long port;
123         unsigned int pldirq;
124
125         pldirq = irq2pldirq(data->irq);
126         port = pldirq2port(pldirq);
127         outw(PLD_ICUCR_ILEVEL7, port);
128 }
129
130 static struct irq_chip m32700ut_pld_irq_type =
131 {
132         .name           = "M32700UT-PLD-IRQ",
133         .irq_shutdown   = shutdown_m32700ut_pld_irq,
134         .irq_mask       = mask_m32700ut_pld,
135         .irq_unmask     = unmask_m32700ut_pld,
136 };
137
138 /*
139  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
140  */
141 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
142 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
143                                  (((x) - 1) * sizeof(unsigned short)))
144
145 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
146
147 static void disable_m32700ut_lanpld_irq(unsigned int irq)
148 {
149         unsigned long port, data;
150         unsigned int pldirq;
151
152         pldirq = irq2lanpldirq(irq);
153         port = lanpldirq2port(pldirq);
154         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
155         outw(data, port);
156 }
157
158 static void enable_m32700ut_lanpld_irq(unsigned int irq)
159 {
160         unsigned long port, data;
161         unsigned int pldirq;
162
163         pldirq = irq2lanpldirq(irq);
164         port = lanpldirq2port(pldirq);
165         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
166         outw(data, port);
167 }
168
169 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
170 {
171         disable_m32700ut_lanpld_irq(irq);
172 }
173
174 static void end_m32700ut_lanpld_irq(unsigned int irq)
175 {
176         enable_m32700ut_lanpld_irq(irq);
177         enable_m32700ut_irq(M32R_IRQ_INT0);
178 }
179
180 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
181 {
182         enable_m32700ut_lanpld_irq(irq);
183         return (0);
184 }
185
186 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
187 {
188         unsigned long port;
189         unsigned int pldirq;
190
191         pldirq = irq2lanpldirq(irq);
192         port = lanpldirq2port(pldirq);
193         outw(PLD_ICUCR_ILEVEL7, port);
194 }
195
196 static struct irq_chip m32700ut_lanpld_irq_type =
197 {
198         .name = "M32700UT-PLD-LAN-IRQ",
199         .startup = startup_m32700ut_lanpld_irq,
200         .shutdown = shutdown_m32700ut_lanpld_irq,
201         .enable = enable_m32700ut_lanpld_irq,
202         .disable = disable_m32700ut_lanpld_irq,
203         .ack = mask_and_ack_m32700ut_lanpld,
204         .end = end_m32700ut_lanpld_irq
205 };
206
207 /*
208  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
209  */
210 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
211 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
212                                  (((x) - 1) * sizeof(unsigned short)))
213
214 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
215
216 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
217 {
218         unsigned long port, data;
219         unsigned int pldirq;
220
221         pldirq = irq2lcdpldirq(irq);
222         port = lcdpldirq2port(pldirq);
223         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
224         outw(data, port);
225 }
226
227 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
228 {
229         unsigned long port, data;
230         unsigned int pldirq;
231
232         pldirq = irq2lcdpldirq(irq);
233         port = lcdpldirq2port(pldirq);
234         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
235         outw(data, port);
236 }
237
238 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
239 {
240         disable_m32700ut_lcdpld_irq(irq);
241 }
242
243 static void end_m32700ut_lcdpld_irq(unsigned int irq)
244 {
245         enable_m32700ut_lcdpld_irq(irq);
246         enable_m32700ut_irq(M32R_IRQ_INT2);
247 }
248
249 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
250 {
251         enable_m32700ut_lcdpld_irq(irq);
252         return (0);
253 }
254
255 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
256 {
257         unsigned long port;
258         unsigned int pldirq;
259
260         pldirq = irq2lcdpldirq(irq);
261         port = lcdpldirq2port(pldirq);
262         outw(PLD_ICUCR_ILEVEL7, port);
263 }
264
265 static struct irq_chip m32700ut_lcdpld_irq_type =
266 {
267         .name = "M32700UT-PLD-LCD-IRQ",
268         .startup = startup_m32700ut_lcdpld_irq,
269         .shutdown = shutdown_m32700ut_lcdpld_irq,
270         .enable = enable_m32700ut_lcdpld_irq,
271         .disable = disable_m32700ut_lcdpld_irq,
272         .ack = mask_and_ack_m32700ut_lcdpld,
273         .end = end_m32700ut_lcdpld_irq
274 };
275
276 void __init init_IRQ(void)
277 {
278 #if defined(CONFIG_SMC91X)
279         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
280         set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type);
281         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
282         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
283 #endif  /* CONFIG_SMC91X */
284
285         /* MFT2 : system timer */
286         set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
287                                  handle_level_irq);
288         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
289         disable_m32700ut_irq(M32R_IRQ_MFT2);
290
291         /* SIO0 : receive */
292         set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
293                                  handle_level_irq);
294         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
295         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
296
297         /* SIO0 : send */
298         set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
299                                  handle_level_irq);
300         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
301         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
302
303         /* SIO1 : receive */
304         set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
305                                  handle_level_irq);
306         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
307         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
308
309         /* SIO1 : send */
310         set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
311                                  handle_level_irq);
312         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
313         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
314
315         /* DMA1 : */
316         set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
317                                  handle_level_irq);
318         icu_data[M32R_IRQ_DMA1].icucr = 0;
319         disable_m32700ut_irq(M32R_IRQ_DMA1);
320
321 #ifdef CONFIG_SERIAL_M32R_PLDSIO
322         /* INT#1: SIO0 Receive on PLD */
323         set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
324                                  handle_level_irq);
325         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
326         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
327
328         /* INT#1: SIO0 Send on PLD */
329         set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
330                                  handle_level_irq);
331         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
332         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
333 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
334
335         /* INT#1: CFC IREQ on PLD */
336         set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
337                                  handle_level_irq);
338         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
339         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
340
341         /* INT#1: CFC Insert on PLD */
342         set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
343                                  handle_level_irq);
344         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
345         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
346
347         /* INT#1: CFC Eject on PLD */
348         set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
349                                  handle_level_irq);
350         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
351         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
352
353         /*
354          * INT0# is used for LAN, DIO
355          * We enable it here.
356          */
357         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
358         enable_m32700ut_irq(M32R_IRQ_INT0);
359
360         /*
361          * INT1# is used for UART, MMC, CF Controller in FPGA.
362          * We enable it here.
363          */
364         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
365         enable_m32700ut_irq(M32R_IRQ_INT1);
366
367 #if defined(CONFIG_USB)
368         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
369         set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
370
371         lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;      /* "L" level sense */
372         disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
373 #endif
374         /*
375          * INT2# is used for BAT, USB, AUDIO
376          * We enable it here.
377          */
378         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
379         enable_m32700ut_irq(M32R_IRQ_INT2);
380
381 #if defined(CONFIG_VIDEO_M32R_AR)
382         /*
383          * INT3# is used for AR
384          */
385         set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
386                                  handle_level_irq);
387         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
388         disable_m32700ut_irq(M32R_IRQ_INT3);
389 #endif  /* CONFIG_VIDEO_M32R_AR */
390 }
391
392 #if defined(CONFIG_SMC91X)
393
394 #define LAN_IOSTART     0x300
395 #define LAN_IOEND       0x320
396 static struct resource smc91x_resources[] = {
397         [0] = {
398                 .start  = (LAN_IOSTART),
399                 .end    = (LAN_IOEND),
400                 .flags  = IORESOURCE_MEM,
401         },
402         [1] = {
403                 .start  = M32700UT_LAN_IRQ_LAN,
404                 .end    = M32700UT_LAN_IRQ_LAN,
405                 .flags  = IORESOURCE_IRQ,
406         }
407 };
408
409 static struct platform_device smc91x_device = {
410         .name           = "smc91x",
411         .id             = 0,
412         .num_resources  = ARRAY_SIZE(smc91x_resources),
413         .resource       = smc91x_resources,
414 };
415 #endif
416
417 #if defined(CONFIG_FB_S1D13XXX)
418
419 #include <video/s1d13xxxfb.h>
420 #include <asm/s1d13806.h>
421
422 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
423         .initregs               = s1d13xxxfb_initregs,
424         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
425         .platform_init_video    = NULL,
426 #ifdef CONFIG_PM
427         .platform_suspend_video = NULL,
428         .platform_resume_video  = NULL,
429 #endif
430 };
431
432 static struct resource s1d13xxxfb_resources[] = {
433         [0] = {
434                 .start  = 0x10600000UL,
435                 .end    = 0x1073FFFFUL,
436                 .flags  = IORESOURCE_MEM,
437         },
438         [1] = {
439                 .start  = 0x10400000UL,
440                 .end    = 0x104001FFUL,
441                 .flags  = IORESOURCE_MEM,
442         }
443 };
444
445 static struct platform_device s1d13xxxfb_device = {
446         .name           = S1D_DEVICENAME,
447         .id             = 0,
448         .dev            = {
449                 .platform_data  = &s1d13xxxfb_data,
450         },
451         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
452         .resource       = s1d13xxxfb_resources,
453 };
454 #endif
455
456 static int __init platform_init(void)
457 {
458 #if defined(CONFIG_SMC91X)
459         platform_device_register(&smc91x_device);
460 #endif
461 #if defined(CONFIG_FB_S1D13XXX)
462         platform_device_register(&s1d13xxxfb_device);
463 #endif
464         return 0;
465 }
466 arch_initcall(platform_init);