Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / m32r / lib / delay.c
1 /*
2  * linux/arch/m32r/lib/delay.c
3  *
4  * Copyright (c) 2002  Hitoshi Yamamoto, Hirokazu Takata
5  * Copyright (c) 2004  Hirokazu Takata
6  */
7
8 #include <linux/param.h>
9 #include <linux/module.h>
10 #ifdef CONFIG_SMP
11 #include <linux/sched.h>
12 #include <asm/current.h>
13 #include <asm/smp.h>
14 #endif  /* CONFIG_SMP */
15 #include <asm/processor.h>
16
17 void __delay(unsigned long loops)
18 {
19 #ifdef CONFIG_ISA_DUAL_ISSUE
20         __asm__ __volatile__ (
21                 "beqz   %0, 2f                  \n\t"
22                 "addi   %0, #-1                 \n\t"
23
24                 " .fillinsn                     \n\t"
25                 "1:                             \n\t"
26                 "cmpz   %0  ||  addi  %0, #-1   \n\t"
27                 "bc     2f  ||  cmpz  %0        \n\t"
28                 "bc     2f  ||  addi  %0, #-1   \n\t"
29                 "cmpz   %0  ||  addi  %0, #-1   \n\t"
30                 "bc     2f  ||  cmpz  %0        \n\t"
31                 "bnc    1b  ||  addi  %0, #-1   \n\t"
32                 " .fillinsn                     \n\t"
33                 "2:                             \n\t"
34                 : "+r" (loops)
35                 : "r" (0)
36                 : "cbit"
37         );
38 #else
39         __asm__ __volatile__ (
40                 "beqz   %0, 2f                  \n\t"
41                 " .fillinsn                     \n\t"
42                 "1:                             \n\t"
43                 "addi   %0, #-1                 \n\t"
44                 "blez   %0, 2f                  \n\t"
45                 "addi   %0, #-1                 \n\t"
46                 "blez   %0, 2f                  \n\t"
47                 "addi   %0, #-1                 \n\t"
48                 "blez   %0, 2f                  \n\t"
49                 "addi   %0, #-1                 \n\t"
50                 "bgtz   %0, 1b                  \n\t"
51                 " .fillinsn                     \n\t"
52                 "2:                             \n\t"
53                 : "+r" (loops)
54                 : "r" (0)
55         );
56 #endif
57 }
58
59 void __const_udelay(unsigned long xloops)
60 {
61 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
62         /*
63          * loops [1] = (xloops >> 32) [sec] * loops_per_jiffy [1/jiffy]
64          *            * HZ [jiffy/sec]
65          *          = (xloops >> 32) [sec] * (loops_per_jiffy * HZ) [1/sec]
66          *          = (((xloops * loops_per_jiffy) >> 32) * HZ) [1]
67          *
68          * NOTE:
69          *   - '[]' depicts variable's dimension in the above equation.
70          *   - "rac" instruction rounds the accumulator in word size.
71          */
72         __asm__ __volatile__ (
73                 "srli   %0, #1                          \n\t"
74                 "mulwhi %0, %1  ; a0                    \n\t"
75                 "mulwu1 %0, %1  ; a1                    \n\t"
76                 "sadd           ; a0 += (a1 >> 16)      \n\t"
77                 "rac    a0, a0, #1                      \n\t"
78                 "mvfacmi %0, a0                         \n\t"
79                 : "+r" (xloops)
80                 : "r" (current_cpu_data.loops_per_jiffy)
81                 : "a0", "a1"
82         );
83 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
84         /*
85          * u64 ull;
86          * ull = (u64)xloops * (u64)current_cpu_data.loops_per_jiffy;
87          * xloops = (ull >> 32);
88          */
89         __asm__ __volatile__ (
90                 "and3   r4, %0, #0xffff         \n\t"
91                 "and3   r5, %1, #0xffff         \n\t"
92                 "mul    r4, r5                  \n\t"
93                 "srl3   r6, %0, #16             \n\t"
94                 "srli   r4, #16                 \n\t"
95                 "mul    r5, r6                  \n\t"
96                 "add    r4, r5                  \n\t"
97                 "and3   r5, %0, #0xffff         \n\t"
98                 "srl3   r6, %1, #16             \n\t"
99                 "mul    r5, r6                  \n\t"
100                 "add    r4, r5                  \n\t"
101                 "srl3   r5, %0, #16             \n\t"
102                 "srli   r4, #16                 \n\t"
103                 "mul    r5, r6                  \n\t"
104                 "add    r4, r5                  \n\t"
105                 "mv     %0, r4                  \n\t"
106                 : "+r" (xloops)
107                 : "r" (current_cpu_data.loops_per_jiffy)
108                 : "r4", "r5", "r6"
109         );
110 #else
111 #error unknown isa configuration
112 #endif
113         __delay(xloops * HZ);
114 }
115
116 void __udelay(unsigned long usecs)
117 {
118         __const_udelay(usecs * 0x000010c7);  /* 2**32 / 1000000 (rounded up) */
119 }
120
121 void __ndelay(unsigned long nsecs)
122 {
123         __const_udelay(nsecs * 0x00005);  /* 2**32 / 1000000000 (rounded up) */
124 }
125
126 EXPORT_SYMBOL(__delay);
127 EXPORT_SYMBOL(__const_udelay);
128 EXPORT_SYMBOL(__udelay);
129 EXPORT_SYMBOL(__ndelay);