[IA64] Add API for allocating Dynamic TR resource.
[linux-2.6.git] / arch / ia64 / mm / tlb.c
1 /*
2  * TLB support routines.
3  *
4  * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5  *      David Mosberger-Tang <davidm@hpl.hp.com>
6  *
7  * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
8  *              Modified RID allocation for SMP
9  *          Goutham Rao <goutham.rao@intel.com>
10  *              IPI based ptc implementation and A-step IPI implementation.
11  * Rohit Seth <rohit.seth@intel.com>
12  * Ken Chen <kenneth.w.chen@intel.com>
13  * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
14  */
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/mm.h>
21 #include <linux/bootmem.h>
22
23 #include <asm/delay.h>
24 #include <asm/mmu_context.h>
25 #include <asm/pgalloc.h>
26 #include <asm/pal.h>
27 #include <asm/tlbflush.h>
28 #include <asm/dma.h>
29 #include <asm/processor.h>
30 #include <asm/tlb.h>
31
32 static struct {
33         unsigned long mask;     /* mask of supported purge page-sizes */
34         unsigned long max_bits; /* log2 of largest supported purge page-size */
35 } purge;
36
37 struct ia64_ctx ia64_ctx = {
38         .lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
39         .next = 1,
40         .max_ctx = ~0U
41 };
42
43 DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
44 DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
45 DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
46
47 struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
48
49 /*
50  * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
51  * Called after cpu_init() has setup ia64_ctx.max_ctx based on
52  * maximum RID that is supported by boot CPU.
53  */
54 void __init
55 mmu_context_init (void)
56 {
57         ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
58         ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
59 }
60
61 /*
62  * Acquire the ia64_ctx.lock before calling this function!
63  */
64 void
65 wrap_mmu_context (struct mm_struct *mm)
66 {
67         int i, cpu;
68         unsigned long flush_bit;
69
70         for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
71                 flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
72                 ia64_ctx.bitmap[i] ^= flush_bit;
73         }
74  
75         /* use offset at 300 to skip daemons */
76         ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
77                                 ia64_ctx.max_ctx, 300);
78         ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
79                                 ia64_ctx.max_ctx, ia64_ctx.next);
80
81         /*
82          * can't call flush_tlb_all() here because of race condition
83          * with O(1) scheduler [EF]
84          */
85         cpu = get_cpu(); /* prevent preemption/migration */
86         for_each_online_cpu(i)
87                 if (i != cpu)
88                         per_cpu(ia64_need_tlb_flush, i) = 1;
89         put_cpu();
90         local_flush_tlb_all();
91 }
92
93 void
94 ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
95                        unsigned long end, unsigned long nbits)
96 {
97         static DEFINE_SPINLOCK(ptcg_lock);
98
99         struct mm_struct *active_mm = current->active_mm;
100
101         if (mm != active_mm) {
102                 /* Restore region IDs for mm */
103                 if (mm && active_mm) {
104                         activate_context(mm);
105                 } else {
106                         flush_tlb_all();
107                         return;
108                 }
109         }
110
111         /* HW requires global serialization of ptc.ga.  */
112         spin_lock(&ptcg_lock);
113         {
114                 do {
115                         /*
116                          * Flush ALAT entries also.
117                          */
118                         ia64_ptcga(start, (nbits<<2));
119                         ia64_srlz_i();
120                         start += (1UL << nbits);
121                 } while (start < end);
122         }
123         spin_unlock(&ptcg_lock);
124
125         if (mm != active_mm) {
126                 activate_context(active_mm);
127         }
128 }
129
130 void
131 local_flush_tlb_all (void)
132 {
133         unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
134
135         addr    = local_cpu_data->ptce_base;
136         count0  = local_cpu_data->ptce_count[0];
137         count1  = local_cpu_data->ptce_count[1];
138         stride0 = local_cpu_data->ptce_stride[0];
139         stride1 = local_cpu_data->ptce_stride[1];
140
141         local_irq_save(flags);
142         for (i = 0; i < count0; ++i) {
143                 for (j = 0; j < count1; ++j) {
144                         ia64_ptce(addr);
145                         addr += stride1;
146                 }
147                 addr += stride0;
148         }
149         local_irq_restore(flags);
150         ia64_srlz_i();                  /* srlz.i implies srlz.d */
151 }
152
153 void
154 flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
155                  unsigned long end)
156 {
157         struct mm_struct *mm = vma->vm_mm;
158         unsigned long size = end - start;
159         unsigned long nbits;
160
161 #ifndef CONFIG_SMP
162         if (mm != current->active_mm) {
163                 mm->context = 0;
164                 return;
165         }
166 #endif
167
168         nbits = ia64_fls(size + 0xfff);
169         while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
170                         (nbits < purge.max_bits))
171                 ++nbits;
172         if (nbits > purge.max_bits)
173                 nbits = purge.max_bits;
174         start &= ~((1UL << nbits) - 1);
175
176         preempt_disable();
177 #ifdef CONFIG_SMP
178         if (mm != current->active_mm || cpus_weight(mm->cpu_vm_mask) != 1) {
179                 platform_global_tlb_purge(mm, start, end, nbits);
180                 preempt_enable();
181                 return;
182         }
183 #endif
184         do {
185                 ia64_ptcl(start, (nbits<<2));
186                 start += (1UL << nbits);
187         } while (start < end);
188         preempt_enable();
189         ia64_srlz_i();                  /* srlz.i implies srlz.d */
190 }
191 EXPORT_SYMBOL(flush_tlb_range);
192
193 void __devinit
194 ia64_tlb_init (void)
195 {
196         ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
197         unsigned long tr_pgbits;
198         long status;
199         pal_vm_info_1_u_t vm_info_1;
200         pal_vm_info_2_u_t vm_info_2;
201         int cpu = smp_processor_id();
202
203         if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
204                 printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
205                        "defaulting to architected purge page-sizes.\n", status);
206                 purge.mask = 0x115557000UL;
207         }
208         purge.max_bits = ia64_fls(purge.mask);
209
210         ia64_get_ptce(&ptce_info);
211         local_cpu_data->ptce_base = ptce_info.base;
212         local_cpu_data->ptce_count[0] = ptce_info.count[0];
213         local_cpu_data->ptce_count[1] = ptce_info.count[1];
214         local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
215         local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
216
217         local_flush_tlb_all();  /* nuke left overs from bootstrapping... */
218         status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
219
220         if (status) {
221                 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
222                 per_cpu(ia64_tr_num, cpu) = 8;
223                 return;
224         }
225         per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
226         if (per_cpu(ia64_tr_num, cpu) >
227                                 (vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
228                 per_cpu(ia64_tr_num, cpu) =
229                                 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
230         if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
231                 per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
232                 printk(KERN_DEBUG "TR register number exceeds IA64_TR_ALLOC_MAX!"
233                         "IA64_TR_ALLOC_MAX should be extended\n");
234         }
235 }
236
237 /*
238  * is_tr_overlap
239  *
240  * Check overlap with inserted TRs.
241  */
242 static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
243 {
244         u64 tr_log_size;
245         u64 tr_end;
246         u64 va_rr = ia64_get_rr(va);
247         u64 va_rid = RR_TO_RID(va_rr);
248         u64 va_end = va + (1<<log_size) - 1;
249
250         if (va_rid != RR_TO_RID(p->rr))
251                 return 0;
252         tr_log_size = (p->itir & 0xff) >> 2;
253         tr_end = p->ifa + (1<<tr_log_size) - 1;
254
255         if (va > tr_end || p->ifa > va_end)
256                 return 0;
257         return 1;
258
259 }
260
261 /*
262  * ia64_insert_tr in virtual mode. Allocate a TR slot
263  *
264  * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
265  *
266  * va   : virtual address.
267  * pte  : pte entries inserted.
268  * log_size: range to be covered.
269  *
270  * Return value:  <0 :  error No.
271  *
272  *                >=0 : slot number allocated for TR.
273  * Must be called with preemption disabled.
274  */
275 int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
276 {
277         int i, r;
278         unsigned long psr;
279         struct ia64_tr_entry *p;
280         int cpu = smp_processor_id();
281
282         r = -EINVAL;
283         /*Check overlap with existing TR entries*/
284         if (target_mask & 0x1) {
285                 p = &__per_cpu_idtrs[cpu][0][0];
286                 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
287                                                                 i++, p++) {
288                         if (p->pte & 0x1)
289                                 if (is_tr_overlap(p, va, log_size)) {
290                                         printk(KERN_DEBUG "Overlapped Entry"
291                                                 "Inserted for TR Reigster!!\n");
292                                         goto out;
293                         }
294                 }
295         }
296         if (target_mask & 0x2) {
297                 p = &__per_cpu_idtrs[cpu][1][0];
298                 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
299                                                                 i++, p++) {
300                         if (p->pte & 0x1)
301                                 if (is_tr_overlap(p, va, log_size)) {
302                                         printk(KERN_DEBUG "Overlapped Entry"
303                                                 "Inserted for TR Reigster!!\n");
304                                         goto out;
305                                 }
306                 }
307         }
308
309         for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
310                 switch (target_mask & 0x3) {
311                 case 1:
312                         if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1))
313                                 goto found;
314                         continue;
315                 case 2:
316                         if (!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
317                                 goto found;
318                         continue;
319                 case 3:
320                         if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1) &&
321                                 !(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
322                                 goto found;
323                         continue;
324                 default:
325                         r = -EINVAL;
326                         goto out;
327                 }
328         }
329 found:
330         if (i >= per_cpu(ia64_tr_num, cpu))
331                 return -EBUSY;
332
333         /*Record tr info for mca hander use!*/
334         if (i > per_cpu(ia64_tr_used, cpu))
335                 per_cpu(ia64_tr_used, cpu) = i;
336
337         psr = ia64_clear_ic();
338         if (target_mask & 0x1) {
339                 ia64_itr(0x1, i, va, pte, log_size);
340                 ia64_srlz_i();
341                 p = &__per_cpu_idtrs[cpu][0][i];
342                 p->ifa = va;
343                 p->pte = pte;
344                 p->itir = log_size << 2;
345                 p->rr = ia64_get_rr(va);
346         }
347         if (target_mask & 0x2) {
348                 ia64_itr(0x2, i, va, pte, log_size);
349                 ia64_srlz_i();
350                 p = &__per_cpu_idtrs[cpu][1][i];
351                 p->ifa = va;
352                 p->pte = pte;
353                 p->itir = log_size << 2;
354                 p->rr = ia64_get_rr(va);
355         }
356         ia64_set_psr(psr);
357         r = i;
358 out:
359         return r;
360 }
361 EXPORT_SYMBOL_GPL(ia64_itr_entry);
362
363 /*
364  * ia64_purge_tr
365  *
366  * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
367  * slot: slot number to be freed.
368  *
369  * Must be called with preemption disabled.
370  */
371 void ia64_ptr_entry(u64 target_mask, int slot)
372 {
373         int cpu = smp_processor_id();
374         int i;
375         struct ia64_tr_entry *p;
376
377         if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
378                 return;
379
380         if (target_mask & 0x1) {
381                 p = &__per_cpu_idtrs[cpu][0][slot];
382                 if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
383                         p->pte = 0;
384                         ia64_ptr(0x1, p->ifa, p->itir>>2);
385                         ia64_srlz_i();
386                 }
387         }
388
389         if (target_mask & 0x2) {
390                 p = &__per_cpu_idtrs[cpu][1][slot];
391                 if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
392                         p->pte = 0;
393                         ia64_ptr(0x2, p->ifa, p->itir>>2);
394                         ia64_srlz_i();
395                 }
396         }
397
398         for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
399                 if ((__per_cpu_idtrs[cpu][0][i].pte & 0x1) ||
400                                 (__per_cpu_idtrs[cpu][1][i].pte & 0x1))
401                         break;
402         }
403         per_cpu(ia64_tr_used, cpu) = i;
404 }
405 EXPORT_SYMBOL_GPL(ia64_ptr_entry);