page allocator: do not check NUMA node ID when the caller knows the node is valid
[linux-2.6.git] / arch / ia64 / kernel / mca.c
1 /*
2  * File:        mca.c
3  * Purpose:     Generic MCA handling layer
4  *
5  * Copyright (C) 2003 Hewlett-Packard Co
6  *      David Mosberger-Tang <davidm@hpl.hp.com>
7  *
8  * Copyright (C) 2002 Dell Inc.
9  * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
10  *
11  * Copyright (C) 2002 Intel
12  * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
13  *
14  * Copyright (C) 2001 Intel
15  * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
16  *
17  * Copyright (C) 2000 Intel
18  * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
19  *
20  * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
21  * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
22  *
23  * Copyright (C) 2006 FUJITSU LIMITED
24  * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
25  *
26  * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
27  *            Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
28  *            added min save state dump, added INIT handler.
29  *
30  * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
31  *            Added setup of CMCI and CPEI IRQs, logging of corrected platform
32  *            errors, completed code for logging of corrected & uncorrected
33  *            machine check errors, and updated for conformance with Nov. 2000
34  *            revision of the SAL 3.0 spec.
35  *
36  * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
37  *            Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
38  *            set SAL default return values, changed error record structure to
39  *            linked list, added init call to sal_get_state_info_size().
40  *
41  * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
42  *            GUID cleanups.
43  *
44  * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
45  *            Added INIT backtrace support.
46  *
47  * 2003-12-08 Keith Owens <kaos@sgi.com>
48  *            smp_call_function() must not be called from interrupt context
49  *            (can deadlock on tasklist_lock).
50  *            Use keventd to call smp_call_function().
51  *
52  * 2004-02-01 Keith Owens <kaos@sgi.com>
53  *            Avoid deadlock when using printk() for MCA and INIT records.
54  *            Delete all record printing code, moved to salinfo_decode in user
55  *            space.  Mark variables and functions static where possible.
56  *            Delete dead variables and functions.  Reorder to remove the need
57  *            for forward declarations and to consolidate related code.
58  *
59  * 2005-08-12 Keith Owens <kaos@sgi.com>
60  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS
61  *            state.
62  *
63  * 2005-10-07 Keith Owens <kaos@sgi.com>
64  *            Add notify_die() hooks.
65  *
66  * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
67  *            Add printing support for MCA/INIT.
68  *
69  * 2007-04-27 Russ Anderson <rja@sgi.com>
70  *            Support multiple cpus going through OS_MCA in the same event.
71  */
72 #include <linux/jiffies.h>
73 #include <linux/types.h>
74 #include <linux/init.h>
75 #include <linux/sched.h>
76 #include <linux/interrupt.h>
77 #include <linux/irq.h>
78 #include <linux/bootmem.h>
79 #include <linux/acpi.h>
80 #include <linux/timer.h>
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/smp.h>
84 #include <linux/workqueue.h>
85 #include <linux/cpumask.h>
86 #include <linux/kdebug.h>
87 #include <linux/cpu.h>
88
89 #include <asm/delay.h>
90 #include <asm/machvec.h>
91 #include <asm/meminit.h>
92 #include <asm/page.h>
93 #include <asm/ptrace.h>
94 #include <asm/system.h>
95 #include <asm/sal.h>
96 #include <asm/mca.h>
97 #include <asm/kexec.h>
98
99 #include <asm/irq.h>
100 #include <asm/hw_irq.h>
101 #include <asm/tlb.h>
102
103 #include "mca_drv.h"
104 #include "entry.h"
105
106 #if defined(IA64_MCA_DEBUG_INFO)
107 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
108 #else
109 # define IA64_MCA_DEBUG(fmt...)
110 #endif
111
112 #define NOTIFY_INIT(event, regs, arg, spin)                             \
113 do {                                                                    \
114         if ((notify_die((event), "INIT", (regs), (arg), 0, 0)           \
115                         == NOTIFY_STOP) && ((spin) == 1))               \
116                 ia64_mca_spin(__func__);                                \
117 } while (0)
118
119 #define NOTIFY_MCA(event, regs, arg, spin)                              \
120 do {                                                                    \
121         if ((notify_die((event), "MCA", (regs), (arg), 0, 0)            \
122                         == NOTIFY_STOP) && ((spin) == 1))               \
123                 ia64_mca_spin(__func__);                                \
124 } while (0)
125
126 /* Used by mca_asm.S */
127 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
128 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
129 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
130 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
131 DEFINE_PER_CPU(u64, ia64_mca_tr_reload);   /* Flag for TR reload */
132
133 unsigned long __per_cpu_mca[NR_CPUS];
134
135 /* In mca_asm.S */
136 extern void                     ia64_os_init_dispatch_monarch (void);
137 extern void                     ia64_os_init_dispatch_slave (void);
138
139 static int monarch_cpu = -1;
140
141 static ia64_mc_info_t           ia64_mc_info;
142
143 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
144 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
145 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
146 #define CPE_HISTORY_LENGTH    5
147 #define CMC_HISTORY_LENGTH    5
148
149 #ifdef CONFIG_ACPI
150 static struct timer_list cpe_poll_timer;
151 #endif
152 static struct timer_list cmc_poll_timer;
153 /*
154  * This variable tells whether we are currently in polling mode.
155  * Start with this in the wrong state so we won't play w/ timers
156  * before the system is ready.
157  */
158 static int cmc_polling_enabled = 1;
159
160 /*
161  * Clearing this variable prevents CPE polling from getting activated
162  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
163  * but encounters problems retrieving CPE logs.  This should only be
164  * necessary for debugging.
165  */
166 static int cpe_poll_enabled = 1;
167
168 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
169
170 static int mca_init __initdata;
171
172 /*
173  * limited & delayed printing support for MCA/INIT handler
174  */
175
176 #define mprintk(fmt...) ia64_mca_printk(fmt)
177
178 #define MLOGBUF_SIZE (512+256*NR_CPUS)
179 #define MLOGBUF_MSGMAX 256
180 static char mlogbuf[MLOGBUF_SIZE];
181 static DEFINE_SPINLOCK(mlogbuf_wlock);  /* mca context only */
182 static DEFINE_SPINLOCK(mlogbuf_rlock);  /* normal context only */
183 static unsigned long mlogbuf_start;
184 static unsigned long mlogbuf_end;
185 static unsigned int mlogbuf_finished = 0;
186 static unsigned long mlogbuf_timestamp = 0;
187
188 static int loglevel_save = -1;
189 #define BREAK_LOGLEVEL(__console_loglevel)              \
190         oops_in_progress = 1;                           \
191         if (loglevel_save < 0)                          \
192                 loglevel_save = __console_loglevel;     \
193         __console_loglevel = 15;
194
195 #define RESTORE_LOGLEVEL(__console_loglevel)            \
196         if (loglevel_save >= 0) {                       \
197                 __console_loglevel = loglevel_save;     \
198                 loglevel_save = -1;                     \
199         }                                               \
200         mlogbuf_finished = 0;                           \
201         oops_in_progress = 0;
202
203 /*
204  * Push messages into buffer, print them later if not urgent.
205  */
206 void ia64_mca_printk(const char *fmt, ...)
207 {
208         va_list args;
209         int printed_len;
210         char temp_buf[MLOGBUF_MSGMAX];
211         char *p;
212
213         va_start(args, fmt);
214         printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
215         va_end(args);
216
217         /* Copy the output into mlogbuf */
218         if (oops_in_progress) {
219                 /* mlogbuf was abandoned, use printk directly instead. */
220                 printk(temp_buf);
221         } else {
222                 spin_lock(&mlogbuf_wlock);
223                 for (p = temp_buf; *p; p++) {
224                         unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
225                         if (next != mlogbuf_start) {
226                                 mlogbuf[mlogbuf_end] = *p;
227                                 mlogbuf_end = next;
228                         } else {
229                                 /* buffer full */
230                                 break;
231                         }
232                 }
233                 mlogbuf[mlogbuf_end] = '\0';
234                 spin_unlock(&mlogbuf_wlock);
235         }
236 }
237 EXPORT_SYMBOL(ia64_mca_printk);
238
239 /*
240  * Print buffered messages.
241  *  NOTE: call this after returning normal context. (ex. from salinfod)
242  */
243 void ia64_mlogbuf_dump(void)
244 {
245         char temp_buf[MLOGBUF_MSGMAX];
246         char *p;
247         unsigned long index;
248         unsigned long flags;
249         unsigned int printed_len;
250
251         /* Get output from mlogbuf */
252         while (mlogbuf_start != mlogbuf_end) {
253                 temp_buf[0] = '\0';
254                 p = temp_buf;
255                 printed_len = 0;
256
257                 spin_lock_irqsave(&mlogbuf_rlock, flags);
258
259                 index = mlogbuf_start;
260                 while (index != mlogbuf_end) {
261                         *p = mlogbuf[index];
262                         index = (index + 1) % MLOGBUF_SIZE;
263                         if (!*p)
264                                 break;
265                         p++;
266                         if (++printed_len >= MLOGBUF_MSGMAX - 1)
267                                 break;
268                 }
269                 *p = '\0';
270                 if (temp_buf[0])
271                         printk(temp_buf);
272                 mlogbuf_start = index;
273
274                 mlogbuf_timestamp = 0;
275                 spin_unlock_irqrestore(&mlogbuf_rlock, flags);
276         }
277 }
278 EXPORT_SYMBOL(ia64_mlogbuf_dump);
279
280 /*
281  * Call this if system is going to down or if immediate flushing messages to
282  * console is required. (ex. recovery was failed, crash dump is going to be
283  * invoked, long-wait rendezvous etc.)
284  *  NOTE: this should be called from monarch.
285  */
286 static void ia64_mlogbuf_finish(int wait)
287 {
288         BREAK_LOGLEVEL(console_loglevel);
289
290         spin_lock_init(&mlogbuf_rlock);
291         ia64_mlogbuf_dump();
292         printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
293                 "MCA/INIT might be dodgy or fail.\n");
294
295         if (!wait)
296                 return;
297
298         /* wait for console */
299         printk("Delaying for 5 seconds...\n");
300         udelay(5*1000000);
301
302         mlogbuf_finished = 1;
303 }
304
305 /*
306  * Print buffered messages from INIT context.
307  */
308 static void ia64_mlogbuf_dump_from_init(void)
309 {
310         if (mlogbuf_finished)
311                 return;
312
313         if (mlogbuf_timestamp &&
314                         time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
315                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
316                         " and the system seems to be messed up.\n");
317                 ia64_mlogbuf_finish(0);
318                 return;
319         }
320
321         if (!spin_trylock(&mlogbuf_rlock)) {
322                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
323                         "Generated messages other than stack dump will be "
324                         "buffered to mlogbuf and will be printed later.\n");
325                 printk(KERN_ERR "INIT: If messages would not printed after "
326                         "this INIT, wait 30sec and assert INIT again.\n");
327                 if (!mlogbuf_timestamp)
328                         mlogbuf_timestamp = jiffies;
329                 return;
330         }
331         spin_unlock(&mlogbuf_rlock);
332         ia64_mlogbuf_dump();
333 }
334
335 static void inline
336 ia64_mca_spin(const char *func)
337 {
338         if (monarch_cpu == smp_processor_id())
339                 ia64_mlogbuf_finish(0);
340         mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
341         while (1)
342                 cpu_relax();
343 }
344 /*
345  * IA64_MCA log support
346  */
347 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
348 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
349
350 typedef struct ia64_state_log_s
351 {
352         spinlock_t      isl_lock;
353         int             isl_index;
354         unsigned long   isl_count;
355         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
356 } ia64_state_log_t;
357
358 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
359
360 #define IA64_LOG_ALLOCATE(it, size) \
361         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
362                 (ia64_err_rec_t *)alloc_bootmem(size); \
363         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
364                 (ia64_err_rec_t *)alloc_bootmem(size);}
365 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
366 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
367 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
368 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
369 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
370 #define IA64_LOG_INDEX_INC(it) \
371     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
372     ia64_state_log[it].isl_count++;}
373 #define IA64_LOG_INDEX_DEC(it) \
374     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
375 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
376 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
377 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
378
379 /*
380  * ia64_log_init
381  *      Reset the OS ia64 log buffer
382  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
383  * Outputs      :       None
384  */
385 static void __init
386 ia64_log_init(int sal_info_type)
387 {
388         u64     max_size = 0;
389
390         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
391         IA64_LOG_LOCK_INIT(sal_info_type);
392
393         // SAL will tell us the maximum size of any error record of this type
394         max_size = ia64_sal_get_state_info_size(sal_info_type);
395         if (!max_size)
396                 /* alloc_bootmem() doesn't like zero-sized allocations! */
397                 return;
398
399         // set up OS data structures to hold error info
400         IA64_LOG_ALLOCATE(sal_info_type, max_size);
401         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
402         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
403 }
404
405 /*
406  * ia64_log_get
407  *
408  *      Get the current MCA log from SAL and copy it into the OS log buffer.
409  *
410  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
411  *              irq_safe    whether you can use printk at this point
412  *  Outputs :   size        (total record length)
413  *              *buffer     (ptr to error record)
414  *
415  */
416 static u64
417 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
418 {
419         sal_log_record_header_t     *log_buffer;
420         u64                         total_len = 0;
421         unsigned long               s;
422
423         IA64_LOG_LOCK(sal_info_type);
424
425         /* Get the process state information */
426         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
427
428         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
429
430         if (total_len) {
431                 IA64_LOG_INDEX_INC(sal_info_type);
432                 IA64_LOG_UNLOCK(sal_info_type);
433                 if (irq_safe) {
434                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
435                                        __func__, sal_info_type, total_len);
436                 }
437                 *buffer = (u8 *) log_buffer;
438                 return total_len;
439         } else {
440                 IA64_LOG_UNLOCK(sal_info_type);
441                 return 0;
442         }
443 }
444
445 /*
446  *  ia64_mca_log_sal_error_record
447  *
448  *  This function retrieves a specified error record type from SAL
449  *  and wakes up any processes waiting for error records.
450  *
451  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
452  *              FIXME: remove MCA and irq_safe.
453  */
454 static void
455 ia64_mca_log_sal_error_record(int sal_info_type)
456 {
457         u8 *buffer;
458         sal_log_record_header_t *rh;
459         u64 size;
460         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
461 #ifdef IA64_MCA_DEBUG_INFO
462         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
463 #endif
464
465         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
466         if (!size)
467                 return;
468
469         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
470
471         if (irq_safe)
472                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
473                         smp_processor_id(),
474                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
475
476         /* Clear logs from corrected errors in case there's no user-level logger */
477         rh = (sal_log_record_header_t *)buffer;
478         if (rh->severity == sal_log_severity_corrected)
479                 ia64_sal_clear_state_info(sal_info_type);
480 }
481
482 /*
483  * search_mca_table
484  *  See if the MCA surfaced in an instruction range
485  *  that has been tagged as recoverable.
486  *
487  *  Inputs
488  *      first   First address range to check
489  *      last    Last address range to check
490  *      ip      Instruction pointer, address we are looking for
491  *
492  * Return value:
493  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
494  */
495 int
496 search_mca_table (const struct mca_table_entry *first,
497                 const struct mca_table_entry *last,
498                 unsigned long ip)
499 {
500         const struct mca_table_entry *curr;
501         u64 curr_start, curr_end;
502
503         curr = first;
504         while (curr <= last) {
505                 curr_start = (u64) &curr->start_addr + curr->start_addr;
506                 curr_end = (u64) &curr->end_addr + curr->end_addr;
507
508                 if ((ip >= curr_start) && (ip <= curr_end)) {
509                         return 1;
510                 }
511                 curr++;
512         }
513         return 0;
514 }
515
516 /* Given an address, look for it in the mca tables. */
517 int mca_recover_range(unsigned long addr)
518 {
519         extern struct mca_table_entry __start___mca_table[];
520         extern struct mca_table_entry __stop___mca_table[];
521
522         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
523 }
524 EXPORT_SYMBOL_GPL(mca_recover_range);
525
526 #ifdef CONFIG_ACPI
527
528 int cpe_vector = -1;
529 int ia64_cpe_irq = -1;
530
531 static irqreturn_t
532 ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
533 {
534         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
535         static int              index;
536         static DEFINE_SPINLOCK(cpe_history_lock);
537
538         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
539                        __func__, cpe_irq, smp_processor_id());
540
541         /* SAL spec states this should run w/ interrupts enabled */
542         local_irq_enable();
543
544         spin_lock(&cpe_history_lock);
545         if (!cpe_poll_enabled && cpe_vector >= 0) {
546
547                 int i, count = 1; /* we know 1 happened now */
548                 unsigned long now = jiffies;
549
550                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
551                         if (now - cpe_history[i] <= HZ)
552                                 count++;
553                 }
554
555                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
556                 if (count >= CPE_HISTORY_LENGTH) {
557
558                         cpe_poll_enabled = 1;
559                         spin_unlock(&cpe_history_lock);
560                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
561
562                         /*
563                          * Corrected errors will still be corrected, but
564                          * make sure there's a log somewhere that indicates
565                          * something is generating more than we can handle.
566                          */
567                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
568
569                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
570
571                         /* lock already released, get out now */
572                         goto out;
573                 } else {
574                         cpe_history[index++] = now;
575                         if (index == CPE_HISTORY_LENGTH)
576                                 index = 0;
577                 }
578         }
579         spin_unlock(&cpe_history_lock);
580 out:
581         /* Get the CPE error record and log it */
582         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
583
584         return IRQ_HANDLED;
585 }
586
587 #endif /* CONFIG_ACPI */
588
589 #ifdef CONFIG_ACPI
590 /*
591  * ia64_mca_register_cpev
592  *
593  *  Register the corrected platform error vector with SAL.
594  *
595  *  Inputs
596  *      cpev        Corrected Platform Error Vector number
597  *
598  *  Outputs
599  *      None
600  */
601 void
602 ia64_mca_register_cpev (int cpev)
603 {
604         /* Register the CPE interrupt vector with SAL */
605         struct ia64_sal_retval isrv;
606
607         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
608         if (isrv.status) {
609                 printk(KERN_ERR "Failed to register Corrected Platform "
610                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
611                 return;
612         }
613
614         IA64_MCA_DEBUG("%s: corrected platform error "
615                        "vector %#x registered\n", __func__, cpev);
616 }
617 #endif /* CONFIG_ACPI */
618
619 /*
620  * ia64_mca_cmc_vector_setup
621  *
622  *  Setup the corrected machine check vector register in the processor.
623  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
624  *  This function is invoked on a per-processor basis.
625  *
626  * Inputs
627  *      None
628  *
629  * Outputs
630  *      None
631  */
632 void __cpuinit
633 ia64_mca_cmc_vector_setup (void)
634 {
635         cmcv_reg_t      cmcv;
636
637         cmcv.cmcv_regval        = 0;
638         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
639         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
640         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
641
642         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
643                        __func__, smp_processor_id(), IA64_CMC_VECTOR);
644
645         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
646                        __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
647 }
648
649 /*
650  * ia64_mca_cmc_vector_disable
651  *
652  *  Mask the corrected machine check vector register in the processor.
653  *  This function is invoked on a per-processor basis.
654  *
655  * Inputs
656  *      dummy(unused)
657  *
658  * Outputs
659  *      None
660  */
661 static void
662 ia64_mca_cmc_vector_disable (void *dummy)
663 {
664         cmcv_reg_t      cmcv;
665
666         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
667
668         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
669         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
670
671         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
672                        __func__, smp_processor_id(), cmcv.cmcv_vector);
673 }
674
675 /*
676  * ia64_mca_cmc_vector_enable
677  *
678  *  Unmask the corrected machine check vector register in the processor.
679  *  This function is invoked on a per-processor basis.
680  *
681  * Inputs
682  *      dummy(unused)
683  *
684  * Outputs
685  *      None
686  */
687 static void
688 ia64_mca_cmc_vector_enable (void *dummy)
689 {
690         cmcv_reg_t      cmcv;
691
692         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
693
694         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
695         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
696
697         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
698                        __func__, smp_processor_id(), cmcv.cmcv_vector);
699 }
700
701 /*
702  * ia64_mca_cmc_vector_disable_keventd
703  *
704  * Called via keventd (smp_call_function() is not safe in interrupt context) to
705  * disable the cmc interrupt vector.
706  */
707 static void
708 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
709 {
710         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
711 }
712
713 /*
714  * ia64_mca_cmc_vector_enable_keventd
715  *
716  * Called via keventd (smp_call_function() is not safe in interrupt context) to
717  * enable the cmc interrupt vector.
718  */
719 static void
720 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
721 {
722         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
723 }
724
725 /*
726  * ia64_mca_wakeup
727  *
728  *      Send an inter-cpu interrupt to wake-up a particular cpu.
729  *
730  *  Inputs  :   cpuid
731  *  Outputs :   None
732  */
733 static void
734 ia64_mca_wakeup(int cpu)
735 {
736         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
737 }
738
739 /*
740  * ia64_mca_wakeup_all
741  *
742  *      Wakeup all the slave cpus which have rendez'ed previously.
743  *
744  *  Inputs  :   None
745  *  Outputs :   None
746  */
747 static void
748 ia64_mca_wakeup_all(void)
749 {
750         int cpu;
751
752         /* Clear the Rendez checkin flag for all cpus */
753         for_each_online_cpu(cpu) {
754                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
755                         ia64_mca_wakeup(cpu);
756         }
757
758 }
759
760 /*
761  * ia64_mca_rendez_interrupt_handler
762  *
763  *      This is handler used to put slave processors into spinloop
764  *      while the monarch processor does the mca handling and later
765  *      wake each slave up once the monarch is done.  The state
766  *      IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
767  *      in SAL.  The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
768  *      the cpu has come out of OS rendezvous.
769  *
770  *  Inputs  :   None
771  *  Outputs :   None
772  */
773 static irqreturn_t
774 ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
775 {
776         unsigned long flags;
777         int cpu = smp_processor_id();
778         struct ia64_mca_notify_die nd =
779                 { .sos = NULL, .monarch_cpu = &monarch_cpu };
780
781         /* Mask all interrupts */
782         local_irq_save(flags);
783
784         NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
785
786         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
787         /* Register with the SAL monarch that the slave has
788          * reached SAL
789          */
790         ia64_sal_mc_rendez();
791
792         NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
793
794         /* Wait for the monarch cpu to exit. */
795         while (monarch_cpu != -1)
796                cpu_relax();     /* spin until monarch leaves */
797
798         NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
799
800         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
801         /* Enable all interrupts */
802         local_irq_restore(flags);
803         return IRQ_HANDLED;
804 }
805
806 /*
807  * ia64_mca_wakeup_int_handler
808  *
809  *      The interrupt handler for processing the inter-cpu interrupt to the
810  *      slave cpu which was spinning in the rendez loop.
811  *      Since this spinning is done by turning off the interrupts and
812  *      polling on the wakeup-interrupt bit in the IRR, there is
813  *      nothing useful to be done in the handler.
814  *
815  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
816  *      arg             (Interrupt handler specific argument)
817  *  Outputs :   None
818  *
819  */
820 static irqreturn_t
821 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
822 {
823         return IRQ_HANDLED;
824 }
825
826 /* Function pointer for extra MCA recovery */
827 int (*ia64_mca_ucmc_extension)
828         (void*,struct ia64_sal_os_state*)
829         = NULL;
830
831 int
832 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
833 {
834         if (ia64_mca_ucmc_extension)
835                 return 1;
836
837         ia64_mca_ucmc_extension = fn;
838         return 0;
839 }
840
841 void
842 ia64_unreg_MCA_extension(void)
843 {
844         if (ia64_mca_ucmc_extension)
845                 ia64_mca_ucmc_extension = NULL;
846 }
847
848 EXPORT_SYMBOL(ia64_reg_MCA_extension);
849 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
850
851
852 static inline void
853 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
854 {
855         u64 fslot, tslot, nat;
856         *tr = *fr;
857         fslot = ((unsigned long)fr >> 3) & 63;
858         tslot = ((unsigned long)tr >> 3) & 63;
859         *tnat &= ~(1UL << tslot);
860         nat = (fnat >> fslot) & 1;
861         *tnat |= (nat << tslot);
862 }
863
864 /* Change the comm field on the MCA/INT task to include the pid that
865  * was interrupted, it makes for easier debugging.  If that pid was 0
866  * (swapper or nested MCA/INIT) then use the start of the previous comm
867  * field suffixed with its cpu.
868  */
869
870 static void
871 ia64_mca_modify_comm(const struct task_struct *previous_current)
872 {
873         char *p, comm[sizeof(current->comm)];
874         if (previous_current->pid)
875                 snprintf(comm, sizeof(comm), "%s %d",
876                         current->comm, previous_current->pid);
877         else {
878                 int l;
879                 if ((p = strchr(previous_current->comm, ' ')))
880                         l = p - previous_current->comm;
881                 else
882                         l = strlen(previous_current->comm);
883                 snprintf(comm, sizeof(comm), "%s %*s %d",
884                         current->comm, l, previous_current->comm,
885                         task_thread_info(previous_current)->cpu);
886         }
887         memcpy(current->comm, comm, sizeof(current->comm));
888 }
889
890 /* On entry to this routine, we are running on the per cpu stack, see
891  * mca_asm.h.  The original stack has not been touched by this event.  Some of
892  * the original stack's registers will be in the RBS on this stack.  This stack
893  * also contains a partial pt_regs and switch_stack, the rest of the data is in
894  * PAL minstate.
895  *
896  * The first thing to do is modify the original stack to look like a blocked
897  * task so we can run backtrace on the original task.  Also mark the per cpu
898  * stack as current to ensure that we use the correct task state, it also means
899  * that we can do backtrace on the MCA/INIT handler code itself.
900  */
901
902 static struct task_struct *
903 ia64_mca_modify_original_stack(struct pt_regs *regs,
904                 const struct switch_stack *sw,
905                 struct ia64_sal_os_state *sos,
906                 const char *type)
907 {
908         char *p;
909         ia64_va va;
910         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
911         const pal_min_state_area_t *ms = sos->pal_min_state;
912         struct task_struct *previous_current;
913         struct pt_regs *old_regs;
914         struct switch_stack *old_sw;
915         unsigned size = sizeof(struct pt_regs) +
916                         sizeof(struct switch_stack) + 16;
917         u64 *old_bspstore, *old_bsp;
918         u64 *new_bspstore, *new_bsp;
919         u64 old_unat, old_rnat, new_rnat, nat;
920         u64 slots, loadrs = regs->loadrs;
921         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
922         u64 ar_bspstore = regs->ar_bspstore;
923         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
924         const u64 *bank;
925         const char *msg;
926         int cpu = smp_processor_id();
927
928         previous_current = curr_task(cpu);
929         set_curr_task(cpu, current);
930         if ((p = strchr(current->comm, ' ')))
931                 *p = '\0';
932
933         /* Best effort attempt to cope with MCA/INIT delivered while in
934          * physical mode.
935          */
936         regs->cr_ipsr = ms->pmsa_ipsr;
937         if (ia64_psr(regs)->dt == 0) {
938                 va.l = r12;
939                 if (va.f.reg == 0) {
940                         va.f.reg = 7;
941                         r12 = va.l;
942                 }
943                 va.l = r13;
944                 if (va.f.reg == 0) {
945                         va.f.reg = 7;
946                         r13 = va.l;
947                 }
948         }
949         if (ia64_psr(regs)->rt == 0) {
950                 va.l = ar_bspstore;
951                 if (va.f.reg == 0) {
952                         va.f.reg = 7;
953                         ar_bspstore = va.l;
954                 }
955                 va.l = ar_bsp;
956                 if (va.f.reg == 0) {
957                         va.f.reg = 7;
958                         ar_bsp = va.l;
959                 }
960         }
961
962         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
963          * have been copied to the old stack, the old stack may fail the
964          * validation tests below.  So ia64_old_stack() must restore the dirty
965          * registers from the new stack.  The old and new bspstore probably
966          * have different alignments, so loadrs calculated on the old bsp
967          * cannot be used to restore from the new bsp.  Calculate a suitable
968          * loadrs for the new stack and save it in the new pt_regs, where
969          * ia64_old_stack() can get it.
970          */
971         old_bspstore = (u64 *)ar_bspstore;
972         old_bsp = (u64 *)ar_bsp;
973         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
974         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
975         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
976         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
977
978         /* Verify the previous stack state before we change it */
979         if (user_mode(regs)) {
980                 msg = "occurred in user space";
981                 /* previous_current is guaranteed to be valid when the task was
982                  * in user space, so ...
983                  */
984                 ia64_mca_modify_comm(previous_current);
985                 goto no_mod;
986         }
987
988         if (r13 != sos->prev_IA64_KR_CURRENT) {
989                 msg = "inconsistent previous current and r13";
990                 goto no_mod;
991         }
992
993         if (!mca_recover_range(ms->pmsa_iip)) {
994                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
995                         msg = "inconsistent r12 and r13";
996                         goto no_mod;
997                 }
998                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
999                         msg = "inconsistent ar.bspstore and r13";
1000                         goto no_mod;
1001                 }
1002                 va.p = old_bspstore;
1003                 if (va.f.reg < 5) {
1004                         msg = "old_bspstore is in the wrong region";
1005                         goto no_mod;
1006                 }
1007                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
1008                         msg = "inconsistent ar.bsp and r13";
1009                         goto no_mod;
1010                 }
1011                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1012                 if (ar_bspstore + size > r12) {
1013                         msg = "no room for blocked state";
1014                         goto no_mod;
1015                 }
1016         }
1017
1018         ia64_mca_modify_comm(previous_current);
1019
1020         /* Make the original task look blocked.  First stack a struct pt_regs,
1021          * describing the state at the time of interrupt.  mca_asm.S built a
1022          * partial pt_regs, copy it and fill in the blanks using minstate.
1023          */
1024         p = (char *)r12 - sizeof(*regs);
1025         old_regs = (struct pt_regs *)p;
1026         memcpy(old_regs, regs, sizeof(*regs));
1027         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
1028          * pmsa_{xip,xpsr,xfs}
1029          */
1030         if (ia64_psr(regs)->ic) {
1031                 old_regs->cr_iip = ms->pmsa_iip;
1032                 old_regs->cr_ipsr = ms->pmsa_ipsr;
1033                 old_regs->cr_ifs = ms->pmsa_ifs;
1034         } else {
1035                 old_regs->cr_iip = ms->pmsa_xip;
1036                 old_regs->cr_ipsr = ms->pmsa_xpsr;
1037                 old_regs->cr_ifs = ms->pmsa_xfs;
1038         }
1039         old_regs->pr = ms->pmsa_pr;
1040         old_regs->b0 = ms->pmsa_br0;
1041         old_regs->loadrs = loadrs;
1042         old_regs->ar_rsc = ms->pmsa_rsc;
1043         old_unat = old_regs->ar_unat;
1044         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
1045         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
1046         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
1047         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
1048         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
1049         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
1050         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
1051         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
1052         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
1053         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
1054         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
1055         if (ia64_psr(old_regs)->bn)
1056                 bank = ms->pmsa_bank1_gr;
1057         else
1058                 bank = ms->pmsa_bank0_gr;
1059         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
1060         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
1061         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
1062         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
1063         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
1064         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
1065         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
1066         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
1067         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
1068         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
1069         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
1070         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
1071         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
1072         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
1073         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
1074         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
1075
1076         /* Next stack a struct switch_stack.  mca_asm.S built a partial
1077          * switch_stack, copy it and fill in the blanks using pt_regs and
1078          * minstate.
1079          *
1080          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1081          * ar.pfs is set to 0.
1082          *
1083          * unwind.c::unw_unwind() does special processing for interrupt frames.
1084          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1085          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
1086          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
1087          * switch_stack on the original stack so it will unwind correctly when
1088          * unwind.c reads pt_regs.
1089          *
1090          * thread.ksp is updated to point to the synthesized switch_stack.
1091          */
1092         p -= sizeof(struct switch_stack);
1093         old_sw = (struct switch_stack *)p;
1094         memcpy(old_sw, sw, sizeof(*sw));
1095         old_sw->caller_unat = old_unat;
1096         old_sw->ar_fpsr = old_regs->ar_fpsr;
1097         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1098         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1099         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1100         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1101         old_sw->b0 = (u64)ia64_leave_kernel;
1102         old_sw->b1 = ms->pmsa_br1;
1103         old_sw->ar_pfs = 0;
1104         old_sw->ar_unat = old_unat;
1105         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1106         previous_current->thread.ksp = (u64)p - 16;
1107
1108         /* Finally copy the original stack's registers back to its RBS.
1109          * Registers from ar.bspstore through ar.bsp at the time of the event
1110          * are in the current RBS, copy them back to the original stack.  The
1111          * copy must be done register by register because the original bspstore
1112          * and the current one have different alignments, so the saved RNAT
1113          * data occurs at different places.
1114          *
1115          * mca_asm does cover, so the old_bsp already includes all registers at
1116          * the time of MCA/INIT.  It also does flushrs, so all registers before
1117          * this function have been written to backing store on the MCA/INIT
1118          * stack.
1119          */
1120         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1121         old_rnat = regs->ar_rnat;
1122         while (slots--) {
1123                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
1124                         new_rnat = ia64_get_rnat(new_bspstore++);
1125                 }
1126                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
1127                         *old_bspstore++ = old_rnat;
1128                         old_rnat = 0;
1129                 }
1130                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1131                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1132                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1133                 *old_bspstore++ = *new_bspstore++;
1134         }
1135         old_sw->ar_bspstore = (unsigned long)old_bspstore;
1136         old_sw->ar_rnat = old_rnat;
1137
1138         sos->prev_task = previous_current;
1139         return previous_current;
1140
1141 no_mod:
1142         mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1143                         smp_processor_id(), type, msg);
1144         return previous_current;
1145 }
1146
1147 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1148  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
1149  * not entered rendezvous yet then wait a bit.  The assumption is that any
1150  * slave that has not rendezvoused after a reasonable time is never going to do
1151  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
1152  * interrupt, as well as cpus that receive the INIT slave event.
1153  */
1154
1155 static void
1156 ia64_wait_for_slaves(int monarch, const char *type)
1157 {
1158         int c, i , wait;
1159
1160         /*
1161          * wait 5 seconds total for slaves (arbitrary)
1162          */
1163         for (i = 0; i < 5000; i++) {
1164                 wait = 0;
1165                 for_each_online_cpu(c) {
1166                         if (c == monarch)
1167                                 continue;
1168                         if (ia64_mc_info.imi_rendez_checkin[c]
1169                                         == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1170                                 udelay(1000);           /* short wait */
1171                                 wait = 1;
1172                                 break;
1173                         }
1174                 }
1175                 if (!wait)
1176                         goto all_in;
1177         }
1178
1179         /*
1180          * Maybe slave(s) dead. Print buffered messages immediately.
1181          */
1182         ia64_mlogbuf_finish(0);
1183         mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1184         for_each_online_cpu(c) {
1185                 if (c == monarch)
1186                         continue;
1187                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1188                         mprintk(" %d", c);
1189         }
1190         mprintk("\n");
1191         return;
1192
1193 all_in:
1194         mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1195         return;
1196 }
1197
1198 /*  mca_insert_tr
1199  *
1200  *  Switch rid when TR reload and needed!
1201  *  iord: 1: itr, 2: itr;
1202  *
1203 */
1204 static void mca_insert_tr(u64 iord)
1205 {
1206
1207         int i;
1208         u64 old_rr;
1209         struct ia64_tr_entry *p;
1210         unsigned long psr;
1211         int cpu = smp_processor_id();
1212
1213         psr = ia64_clear_ic();
1214         for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1215                 p = &__per_cpu_idtrs[cpu][iord-1][i];
1216                 if (p->pte & 0x1) {
1217                         old_rr = ia64_get_rr(p->ifa);
1218                         if (old_rr != p->rr) {
1219                                 ia64_set_rr(p->ifa, p->rr);
1220                                 ia64_srlz_d();
1221                         }
1222                         ia64_ptr(iord, p->ifa, p->itir >> 2);
1223                         ia64_srlz_i();
1224                         if (iord & 0x1) {
1225                                 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1226                                 ia64_srlz_i();
1227                         }
1228                         if (iord & 0x2) {
1229                                 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1230                                 ia64_srlz_i();
1231                         }
1232                         if (old_rr != p->rr) {
1233                                 ia64_set_rr(p->ifa, old_rr);
1234                                 ia64_srlz_d();
1235                         }
1236                 }
1237         }
1238         ia64_set_psr(psr);
1239 }
1240
1241 /*
1242  * ia64_mca_handler
1243  *
1244  *      This is uncorrectable machine check handler called from OS_MCA
1245  *      dispatch code which is in turn called from SAL_CHECK().
1246  *      This is the place where the core of OS MCA handling is done.
1247  *      Right now the logs are extracted and displayed in a well-defined
1248  *      format. This handler code is supposed to be run only on the
1249  *      monarch processor. Once the monarch is done with MCA handling
1250  *      further MCA logging is enabled by clearing logs.
1251  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1252  *      slave processors out of rendezvous spinloop.
1253  *
1254  *      If multiple processors call into OS_MCA, the first will become
1255  *      the monarch.  Subsequent cpus will be recorded in the mca_cpu
1256  *      bitmask.  After the first monarch has processed its MCA, it
1257  *      will wake up the next cpu in the mca_cpu bitmask and then go
1258  *      into the rendezvous loop.  When all processors have serviced
1259  *      their MCA, the last monarch frees up the rest of the processors.
1260  */
1261 void
1262 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1263                  struct ia64_sal_os_state *sos)
1264 {
1265         int recover, cpu = smp_processor_id();
1266         struct task_struct *previous_current;
1267         struct ia64_mca_notify_die nd =
1268                 { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
1269         static atomic_t mca_count;
1270         static cpumask_t mca_cpu;
1271
1272         if (atomic_add_return(1, &mca_count) == 1) {
1273                 monarch_cpu = cpu;
1274                 sos->monarch = 1;
1275         } else {
1276                 cpu_set(cpu, mca_cpu);
1277                 sos->monarch = 0;
1278         }
1279         mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1280                 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1281
1282         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1283
1284         NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
1285
1286         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1287         if (sos->monarch) {
1288                 ia64_wait_for_slaves(cpu, "MCA");
1289
1290                 /* Wakeup all the processors which are spinning in the
1291                  * rendezvous loop.  They will leave SAL, then spin in the OS
1292                  * with interrupts disabled until this monarch cpu leaves the
1293                  * MCA handler.  That gets control back to the OS so we can
1294                  * backtrace the other cpus, backtrace when spinning in SAL
1295                  * does not work.
1296                  */
1297                 ia64_mca_wakeup_all();
1298         } else {
1299                 while (cpu_isset(cpu, mca_cpu))
1300                         cpu_relax();    /* spin until monarch wakes us */
1301         }
1302
1303         NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
1304
1305         /* Get the MCA error record and log it */
1306         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1307
1308         /* MCA error recovery */
1309         recover = (ia64_mca_ucmc_extension
1310                 && ia64_mca_ucmc_extension(
1311                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1312                         sos));
1313
1314         if (recover) {
1315                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1316                 rh->severity = sal_log_severity_corrected;
1317                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1318                 sos->os_status = IA64_MCA_CORRECTED;
1319         } else {
1320                 /* Dump buffered message to console */
1321                 ia64_mlogbuf_finish(1);
1322         }
1323
1324         if (__get_cpu_var(ia64_mca_tr_reload)) {
1325                 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1326                 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1327         }
1328
1329         NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
1330
1331         if (atomic_dec_return(&mca_count) > 0) {
1332                 int i;
1333
1334                 /* wake up the next monarch cpu,
1335                  * and put this cpu in the rendez loop.
1336                  */
1337                 for_each_online_cpu(i) {
1338                         if (cpu_isset(i, mca_cpu)) {
1339                                 monarch_cpu = i;
1340                                 cpu_clear(i, mca_cpu);  /* wake next cpu */
1341                                 while (monarch_cpu != -1)
1342                                         cpu_relax();    /* spin until last cpu leaves */
1343                                 set_curr_task(cpu, previous_current);
1344                                 ia64_mc_info.imi_rendez_checkin[cpu]
1345                                                 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1346                                 return;
1347                         }
1348                 }
1349         }
1350         set_curr_task(cpu, previous_current);
1351         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1352         monarch_cpu = -1;       /* This frees the slaves and previous monarchs */
1353 }
1354
1355 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1356 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1357
1358 /*
1359  * ia64_mca_cmc_int_handler
1360  *
1361  *  This is corrected machine check interrupt handler.
1362  *      Right now the logs are extracted and displayed in a well-defined
1363  *      format.
1364  *
1365  * Inputs
1366  *      interrupt number
1367  *      client data arg ptr
1368  *
1369  * Outputs
1370  *      None
1371  */
1372 static irqreturn_t
1373 ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1374 {
1375         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1376         static int              index;
1377         static DEFINE_SPINLOCK(cmc_history_lock);
1378
1379         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1380                        __func__, cmc_irq, smp_processor_id());
1381
1382         /* SAL spec states this should run w/ interrupts enabled */
1383         local_irq_enable();
1384
1385         spin_lock(&cmc_history_lock);
1386         if (!cmc_polling_enabled) {
1387                 int i, count = 1; /* we know 1 happened now */
1388                 unsigned long now = jiffies;
1389
1390                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1391                         if (now - cmc_history[i] <= HZ)
1392                                 count++;
1393                 }
1394
1395                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1396                 if (count >= CMC_HISTORY_LENGTH) {
1397
1398                         cmc_polling_enabled = 1;
1399                         spin_unlock(&cmc_history_lock);
1400                         /* If we're being hit with CMC interrupts, we won't
1401                          * ever execute the schedule_work() below.  Need to
1402                          * disable CMC interrupts on this processor now.
1403                          */
1404                         ia64_mca_cmc_vector_disable(NULL);
1405                         schedule_work(&cmc_disable_work);
1406
1407                         /*
1408                          * Corrected errors will still be corrected, but
1409                          * make sure there's a log somewhere that indicates
1410                          * something is generating more than we can handle.
1411                          */
1412                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1413
1414                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1415
1416                         /* lock already released, get out now */
1417                         goto out;
1418                 } else {
1419                         cmc_history[index++] = now;
1420                         if (index == CMC_HISTORY_LENGTH)
1421                                 index = 0;
1422                 }
1423         }
1424         spin_unlock(&cmc_history_lock);
1425 out:
1426         /* Get the CMC error record and log it */
1427         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1428
1429         return IRQ_HANDLED;
1430 }
1431
1432 /*
1433  *  ia64_mca_cmc_int_caller
1434  *
1435  *      Triggered by sw interrupt from CMC polling routine.  Calls
1436  *      real interrupt handler and either triggers a sw interrupt
1437  *      on the next cpu or does cleanup at the end.
1438  *
1439  * Inputs
1440  *      interrupt number
1441  *      client data arg ptr
1442  * Outputs
1443  *      handled
1444  */
1445 static irqreturn_t
1446 ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1447 {
1448         static int start_count = -1;
1449         unsigned int cpuid;
1450
1451         cpuid = smp_processor_id();
1452
1453         /* If first cpu, update count */
1454         if (start_count == -1)
1455                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1456
1457         ia64_mca_cmc_int_handler(cmc_irq, arg);
1458
1459         cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1460
1461         if (cpuid < nr_cpu_ids) {
1462                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1463         } else {
1464                 /* If no log record, switch out of polling mode */
1465                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1466
1467                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1468                         schedule_work(&cmc_enable_work);
1469                         cmc_polling_enabled = 0;
1470
1471                 } else {
1472
1473                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1474                 }
1475
1476                 start_count = -1;
1477         }
1478
1479         return IRQ_HANDLED;
1480 }
1481
1482 /*
1483  *  ia64_mca_cmc_poll
1484  *
1485  *      Poll for Corrected Machine Checks (CMCs)
1486  *
1487  * Inputs   :   dummy(unused)
1488  * Outputs  :   None
1489  *
1490  */
1491 static void
1492 ia64_mca_cmc_poll (unsigned long dummy)
1493 {
1494         /* Trigger a CMC interrupt cascade  */
1495         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1496 }
1497
1498 /*
1499  *  ia64_mca_cpe_int_caller
1500  *
1501  *      Triggered by sw interrupt from CPE polling routine.  Calls
1502  *      real interrupt handler and either triggers a sw interrupt
1503  *      on the next cpu or does cleanup at the end.
1504  *
1505  * Inputs
1506  *      interrupt number
1507  *      client data arg ptr
1508  * Outputs
1509  *      handled
1510  */
1511 #ifdef CONFIG_ACPI
1512
1513 static irqreturn_t
1514 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1515 {
1516         static int start_count = -1;
1517         static int poll_time = MIN_CPE_POLL_INTERVAL;
1518         unsigned int cpuid;
1519
1520         cpuid = smp_processor_id();
1521
1522         /* If first cpu, update count */
1523         if (start_count == -1)
1524                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1525
1526         ia64_mca_cpe_int_handler(cpe_irq, arg);
1527
1528         cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1529
1530         if (cpuid < NR_CPUS) {
1531                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1532         } else {
1533                 /*
1534                  * If a log was recorded, increase our polling frequency,
1535                  * otherwise, backoff or return to interrupt mode.
1536                  */
1537                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1538                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1539                 } else if (cpe_vector < 0) {
1540                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1541                 } else {
1542                         poll_time = MIN_CPE_POLL_INTERVAL;
1543
1544                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1545                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1546                         cpe_poll_enabled = 0;
1547                 }
1548
1549                 if (cpe_poll_enabled)
1550                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1551                 start_count = -1;
1552         }
1553
1554         return IRQ_HANDLED;
1555 }
1556
1557 /*
1558  *  ia64_mca_cpe_poll
1559  *
1560  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1561  *      on first cpu, from there it will trickle through all the cpus.
1562  *
1563  * Inputs   :   dummy(unused)
1564  * Outputs  :   None
1565  *
1566  */
1567 static void
1568 ia64_mca_cpe_poll (unsigned long dummy)
1569 {
1570         /* Trigger a CPE interrupt cascade  */
1571         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1572 }
1573
1574 #endif /* CONFIG_ACPI */
1575
1576 static int
1577 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1578 {
1579         int c;
1580         struct task_struct *g, *t;
1581         if (val != DIE_INIT_MONARCH_PROCESS)
1582                 return NOTIFY_DONE;
1583 #ifdef CONFIG_KEXEC
1584         if (atomic_read(&kdump_in_progress))
1585                 return NOTIFY_DONE;
1586 #endif
1587
1588         /*
1589          * FIXME: mlogbuf will brim over with INIT stack dumps.
1590          * To enable show_stack from INIT, we use oops_in_progress which should
1591          * be used in real oops. This would cause something wrong after INIT.
1592          */
1593         BREAK_LOGLEVEL(console_loglevel);
1594         ia64_mlogbuf_dump_from_init();
1595
1596         printk(KERN_ERR "Processes interrupted by INIT -");
1597         for_each_online_cpu(c) {
1598                 struct ia64_sal_os_state *s;
1599                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1600                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1601                 g = s->prev_task;
1602                 if (g) {
1603                         if (g->pid)
1604                                 printk(" %d", g->pid);
1605                         else
1606                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1607                 }
1608         }
1609         printk("\n\n");
1610         if (read_trylock(&tasklist_lock)) {
1611                 do_each_thread (g, t) {
1612                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1613                         show_stack(t, NULL);
1614                 } while_each_thread (g, t);
1615                 read_unlock(&tasklist_lock);
1616         }
1617         /* FIXME: This will not restore zapped printk locks. */
1618         RESTORE_LOGLEVEL(console_loglevel);
1619         return NOTIFY_DONE;
1620 }
1621
1622 /*
1623  * C portion of the OS INIT handler
1624  *
1625  * Called from ia64_os_init_dispatch
1626  *
1627  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1628  * this event.  This code is used for both monarch and slave INIT events, see
1629  * sos->monarch.
1630  *
1631  * All INIT events switch to the INIT stack and change the previous process to
1632  * blocked status.  If one of the INIT events is the monarch then we are
1633  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1634  * the processes.  The slave INIT events all spin until the monarch cpu
1635  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1636  * process is the monarch.
1637  */
1638
1639 void
1640 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1641                   struct ia64_sal_os_state *sos)
1642 {
1643         static atomic_t slaves;
1644         static atomic_t monarchs;
1645         struct task_struct *previous_current;
1646         int cpu = smp_processor_id();
1647         struct ia64_mca_notify_die nd =
1648                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1649
1650         NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
1651
1652         mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1653                 sos->proc_state_param, cpu, sos->monarch);
1654         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1655
1656         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1657         sos->os_status = IA64_INIT_RESUME;
1658
1659         /* FIXME: Workaround for broken proms that drive all INIT events as
1660          * slaves.  The last slave that enters is promoted to be a monarch.
1661          * Remove this code in September 2006, that gives platforms a year to
1662          * fix their proms and get their customers updated.
1663          */
1664         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1665                 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1666                         __func__, cpu);
1667                 atomic_dec(&slaves);
1668                 sos->monarch = 1;
1669         }
1670
1671         /* FIXME: Workaround for broken proms that drive all INIT events as
1672          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1673          * Remove this code in September 2006, that gives platforms a year to
1674          * fix their proms and get their customers updated.
1675          */
1676         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1677                 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1678                                __func__, cpu);
1679                 atomic_dec(&monarchs);
1680                 sos->monarch = 0;
1681         }
1682
1683         if (!sos->monarch) {
1684                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1685                 while (monarch_cpu == -1)
1686                        cpu_relax();     /* spin until monarch enters */
1687
1688                 NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
1689                 NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
1690
1691                 while (monarch_cpu != -1)
1692                        cpu_relax();     /* spin until monarch leaves */
1693
1694                 NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
1695
1696                 mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1697                 set_curr_task(cpu, previous_current);
1698                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1699                 atomic_dec(&slaves);
1700                 return;
1701         }
1702
1703         monarch_cpu = cpu;
1704         NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
1705
1706         /*
1707          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1708          * generated via the BMC's command-line interface, but since the console is on the
1709          * same serial line, the user will need some time to switch out of the BMC before
1710          * the dump begins.
1711          */
1712         mprintk("Delaying for 5 seconds...\n");
1713         udelay(5*1000000);
1714         ia64_wait_for_slaves(cpu, "INIT");
1715         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1716          * to default_monarch_init_process() above and just print all the
1717          * tasks.
1718          */
1719         NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
1720         NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
1721
1722         mprintk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1723         atomic_dec(&monarchs);
1724         set_curr_task(cpu, previous_current);
1725         monarch_cpu = -1;
1726         return;
1727 }
1728
1729 static int __init
1730 ia64_mca_disable_cpe_polling(char *str)
1731 {
1732         cpe_poll_enabled = 0;
1733         return 1;
1734 }
1735
1736 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1737
1738 static struct irqaction cmci_irqaction = {
1739         .handler =      ia64_mca_cmc_int_handler,
1740         .flags =        IRQF_DISABLED,
1741         .name =         "cmc_hndlr"
1742 };
1743
1744 static struct irqaction cmcp_irqaction = {
1745         .handler =      ia64_mca_cmc_int_caller,
1746         .flags =        IRQF_DISABLED,
1747         .name =         "cmc_poll"
1748 };
1749
1750 static struct irqaction mca_rdzv_irqaction = {
1751         .handler =      ia64_mca_rendez_int_handler,
1752         .flags =        IRQF_DISABLED,
1753         .name =         "mca_rdzv"
1754 };
1755
1756 static struct irqaction mca_wkup_irqaction = {
1757         .handler =      ia64_mca_wakeup_int_handler,
1758         .flags =        IRQF_DISABLED,
1759         .name =         "mca_wkup"
1760 };
1761
1762 #ifdef CONFIG_ACPI
1763 static struct irqaction mca_cpe_irqaction = {
1764         .handler =      ia64_mca_cpe_int_handler,
1765         .flags =        IRQF_DISABLED,
1766         .name =         "cpe_hndlr"
1767 };
1768
1769 static struct irqaction mca_cpep_irqaction = {
1770         .handler =      ia64_mca_cpe_int_caller,
1771         .flags =        IRQF_DISABLED,
1772         .name =         "cpe_poll"
1773 };
1774 #endif /* CONFIG_ACPI */
1775
1776 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1777  * these stacks can never sleep, they cannot return from the kernel to user
1778  * space, they do not appear in a normal ps listing.  So there is no need to
1779  * format most of the fields.
1780  */
1781
1782 static void __cpuinit
1783 format_mca_init_stack(void *mca_data, unsigned long offset,
1784                 const char *type, int cpu)
1785 {
1786         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1787         struct thread_info *ti;
1788         memset(p, 0, KERNEL_STACK_SIZE);
1789         ti = task_thread_info(p);
1790         ti->flags = _TIF_MCA_INIT;
1791         ti->preempt_count = 1;
1792         ti->task = p;
1793         ti->cpu = cpu;
1794         p->stack = ti;
1795         p->state = TASK_UNINTERRUPTIBLE;
1796         cpu_set(cpu, p->cpus_allowed);
1797         INIT_LIST_HEAD(&p->tasks);
1798         p->parent = p->real_parent = p->group_leader = p;
1799         INIT_LIST_HEAD(&p->children);
1800         INIT_LIST_HEAD(&p->sibling);
1801         strncpy(p->comm, type, sizeof(p->comm)-1);
1802 }
1803
1804 /* Caller prevents this from being called after init */
1805 static void * __init_refok mca_bootmem(void)
1806 {
1807         return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
1808                             KERNEL_STACK_SIZE, 0);
1809 }
1810
1811 /* Do per-CPU MCA-related initialization.  */
1812 void __cpuinit
1813 ia64_mca_cpu_init(void *cpu_data)
1814 {
1815         void *pal_vaddr;
1816         void *data;
1817         long sz = sizeof(struct ia64_mca_cpu);
1818         int cpu = smp_processor_id();
1819         static int first_time = 1;
1820
1821         /*
1822          * Structure will already be allocated if cpu has been online,
1823          * then offlined.
1824          */
1825         if (__per_cpu_mca[cpu]) {
1826                 data = __va(__per_cpu_mca[cpu]);
1827         } else {
1828                 if (first_time) {
1829                         data = mca_bootmem();
1830                         first_time = 0;
1831                 } else
1832                         data = __get_free_pages(GFP_KERNEL, get_order(sz));
1833                 if (!data)
1834                         panic("Could not allocate MCA memory for cpu %d\n",
1835                                         cpu);
1836         }
1837         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1838                 "MCA", cpu);
1839         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1840                 "INIT", cpu);
1841         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[cpu] = __pa(data);
1842
1843         /*
1844          * Stash away a copy of the PTE needed to map the per-CPU page.
1845          * We may need it during MCA recovery.
1846          */
1847         __get_cpu_var(ia64_mca_per_cpu_pte) =
1848                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1849
1850         /*
1851          * Also, stash away a copy of the PAL address and the PTE
1852          * needed to map it.
1853          */
1854         pal_vaddr = efi_get_pal_addr();
1855         if (!pal_vaddr)
1856                 return;
1857         __get_cpu_var(ia64_mca_pal_base) =
1858                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1859         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1860                                                               PAGE_KERNEL));
1861 }
1862
1863 static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
1864 {
1865         unsigned long flags;
1866
1867         local_irq_save(flags);
1868         if (!cmc_polling_enabled)
1869                 ia64_mca_cmc_vector_enable(NULL);
1870         local_irq_restore(flags);
1871 }
1872
1873 static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
1874                                       unsigned long action,
1875                                       void *hcpu)
1876 {
1877         int hotcpu = (unsigned long) hcpu;
1878
1879         switch (action) {
1880         case CPU_ONLINE:
1881         case CPU_ONLINE_FROZEN:
1882                 smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust,
1883                                          NULL, 0);
1884                 break;
1885         }
1886         return NOTIFY_OK;
1887 }
1888
1889 static struct notifier_block mca_cpu_notifier __cpuinitdata = {
1890         .notifier_call = mca_cpu_callback
1891 };
1892
1893 /*
1894  * ia64_mca_init
1895  *
1896  *  Do all the system level mca specific initialization.
1897  *
1898  *      1. Register spinloop and wakeup request interrupt vectors
1899  *
1900  *      2. Register OS_MCA handler entry point
1901  *
1902  *      3. Register OS_INIT handler entry point
1903  *
1904  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1905  *
1906  *  Note that this initialization is done very early before some kernel
1907  *  services are available.
1908  *
1909  *  Inputs  :   None
1910  *
1911  *  Outputs :   None
1912  */
1913 void __init
1914 ia64_mca_init(void)
1915 {
1916         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1917         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1918         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1919         int i;
1920         s64 rc;
1921         struct ia64_sal_retval isrv;
1922         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1923         static struct notifier_block default_init_monarch_nb = {
1924                 .notifier_call = default_monarch_init_process,
1925                 .priority = 0/* we need to notified last */
1926         };
1927
1928         IA64_MCA_DEBUG("%s: begin\n", __func__);
1929
1930         /* Clear the Rendez checkin flag for all cpus */
1931         for(i = 0 ; i < NR_CPUS; i++)
1932                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1933
1934         /*
1935          * Register the rendezvous spinloop and wakeup mechanism with SAL
1936          */
1937
1938         /* Register the rendezvous interrupt vector with SAL */
1939         while (1) {
1940                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1941                                               SAL_MC_PARAM_MECHANISM_INT,
1942                                               IA64_MCA_RENDEZ_VECTOR,
1943                                               timeout,
1944                                               SAL_MC_PARAM_RZ_ALWAYS);
1945                 rc = isrv.status;
1946                 if (rc == 0)
1947                         break;
1948                 if (rc == -2) {
1949                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1950                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1951                         timeout = isrv.v0;
1952                         NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
1953                         continue;
1954                 }
1955                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1956                        "with SAL (status %ld)\n", rc);
1957                 return;
1958         }
1959
1960         /* Register the wakeup interrupt vector with SAL */
1961         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1962                                       SAL_MC_PARAM_MECHANISM_INT,
1963                                       IA64_MCA_WAKEUP_VECTOR,
1964                                       0, 0);
1965         rc = isrv.status;
1966         if (rc) {
1967                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1968                        "(status %ld)\n", rc);
1969                 return;
1970         }
1971
1972         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
1973
1974         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1975         /*
1976          * XXX - disable SAL checksum by setting size to 0; should be
1977          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1978          */
1979         ia64_mc_info.imi_mca_handler_size       = 0;
1980
1981         /* Register the os mca handler with SAL */
1982         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1983                                        ia64_mc_info.imi_mca_handler,
1984                                        ia64_tpa(mca_hldlr_ptr->gp),
1985                                        ia64_mc_info.imi_mca_handler_size,
1986                                        0, 0, 0)))
1987         {
1988                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1989                        "(status %ld)\n", rc);
1990                 return;
1991         }
1992
1993         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
1994                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1995
1996         /*
1997          * XXX - disable SAL checksum by setting size to 0, should be
1998          * size of the actual init handler in mca_asm.S.
1999          */
2000         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
2001         ia64_mc_info.imi_monarch_init_handler_size      = 0;
2002         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
2003         ia64_mc_info.imi_slave_init_handler_size        = 0;
2004
2005         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
2006                        ia64_mc_info.imi_monarch_init_handler);
2007
2008         /* Register the os init handler with SAL */
2009         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
2010                                        ia64_mc_info.imi_monarch_init_handler,
2011                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2012                                        ia64_mc_info.imi_monarch_init_handler_size,
2013                                        ia64_mc_info.imi_slave_init_handler,
2014                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2015                                        ia64_mc_info.imi_slave_init_handler_size)))
2016         {
2017                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
2018                        "(status %ld)\n", rc);
2019                 return;
2020         }
2021         if (register_die_notifier(&default_init_monarch_nb)) {
2022                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
2023                 return;
2024         }
2025
2026         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2027
2028         /*
2029          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
2030          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2031          */
2032         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
2033         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
2034         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
2035
2036         /* Setup the MCA rendezvous interrupt vector */
2037         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
2038
2039         /* Setup the MCA wakeup interrupt vector */
2040         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
2041
2042 #ifdef CONFIG_ACPI
2043         /* Setup the CPEI/P handler */
2044         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
2045 #endif
2046
2047         /* Initialize the areas set aside by the OS to buffer the
2048          * platform/processor error states for MCA/INIT/CMC
2049          * handling.
2050          */
2051         ia64_log_init(SAL_INFO_TYPE_MCA);
2052         ia64_log_init(SAL_INFO_TYPE_INIT);
2053         ia64_log_init(SAL_INFO_TYPE_CMC);
2054         ia64_log_init(SAL_INFO_TYPE_CPE);
2055
2056         mca_init = 1;
2057         printk(KERN_INFO "MCA related initialization done\n");
2058 }
2059
2060 /*
2061  * ia64_mca_late_init
2062  *
2063  *      Opportunity to setup things that require initialization later
2064  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
2065  *      platform doesn't support an interrupt driven mechanism.
2066  *
2067  *  Inputs  :   None
2068  *  Outputs :   Status
2069  */
2070 static int __init
2071 ia64_mca_late_init(void)
2072 {
2073         if (!mca_init)
2074                 return 0;
2075
2076         register_hotcpu_notifier(&mca_cpu_notifier);
2077
2078         /* Setup the CMCI/P vector and handler */
2079         init_timer(&cmc_poll_timer);
2080         cmc_poll_timer.function = ia64_mca_cmc_poll;
2081
2082         /* Unmask/enable the vector */
2083         cmc_polling_enabled = 0;
2084         schedule_work(&cmc_enable_work);
2085
2086         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2087
2088 #ifdef CONFIG_ACPI
2089         /* Setup the CPEI/P vector and handler */
2090         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2091         init_timer(&cpe_poll_timer);
2092         cpe_poll_timer.function = ia64_mca_cpe_poll;
2093
2094         {
2095                 irq_desc_t *desc;
2096                 unsigned int irq;
2097
2098                 if (cpe_vector >= 0) {
2099                         /* If platform supports CPEI, enable the irq. */
2100                         irq = local_vector_to_irq(cpe_vector);
2101                         if (irq > 0) {
2102                                 cpe_poll_enabled = 0;
2103                                 desc = irq_desc + irq;
2104                                 desc->status |= IRQ_PER_CPU;
2105                                 setup_irq(irq, &mca_cpe_irqaction);
2106                                 ia64_cpe_irq = irq;
2107                                 ia64_mca_register_cpev(cpe_vector);
2108                                 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2109                                         __func__);
2110                                 return 0;
2111                         }
2112                         printk(KERN_ERR "%s: Failed to find irq for CPE "
2113                                         "interrupt handler, vector %d\n",
2114                                         __func__, cpe_vector);
2115                 }
2116                 /* If platform doesn't support CPEI, get the timer going. */
2117                 if (cpe_poll_enabled) {
2118                         ia64_mca_cpe_poll(0UL);
2119                         IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2120                 }
2121         }
2122 #endif
2123
2124         return 0;
2125 }
2126
2127 device_initcall(ia64_mca_late_init);