Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6.git] / arch / ia64 / kernel / iosapic.c
1 /*
2  * I/O SAPIC support.
3  *
4  * Copyright (C) 1999 Intel Corp.
5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8  *      David Mosberger-Tang <davidm@hpl.hp.com>
9  * Copyright (C) 1999 VA Linux Systems
10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
11  *
12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
13  *                              APIC code.  In particular, we now have separate
14  *                              handlers for edge and level triggered
15  *                              interrupts.
16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17  *                              allocation PCI to vector mapping, shared PCI
18  *                              interrupts.
19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
20  *                              understandable.  Clean up much of the old
21  *                              IOSAPIC cruft.
22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
23  *                              and fixes for ACPI S5(SoftOff) support.
24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
26  *                              vectors in iosapic_set_affinity(),
27  *                              initializations for /proc/irq/#/smp_affinity
28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
31  *                              IOSAPIC mapping error
32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
34  *                              interrupt, vector, etc.)
35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
36  *                              pci_irq code.
37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
38  *                              Remove iosapic_address & gsi_base from
39  *                              external interfaces.  Rationalize
40  *                              __init/__devinit attributes.
41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
42  *                              Updated to work with irq migration necessary
43  *                              for CPU Hotplug
44  */
45 /*
46  * Here is what the interrupt logic between a PCI device and the kernel looks
47  * like:
48  *
49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
51  *     (the function number does not matter here because all functions share
52  *     the same interrupt lines).
53  *
54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55  *     controller.  Multiple interrupt lines may have to share the same
56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
58  *     which can be calculated as the sum of the controller's base GSI number
59  *     and the IOSAPIC pin number to which the line connects.
60  *
61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
63  * sent to the CPU.
64  *
65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
66  *     used as architecture-independent interrupt handling mechanism in Linux.
67  *     As an IRQ is a number, we have to have
68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
70  *     platform can implement platform_irq_to_vector(irq) and
71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72  *     Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
73  *
74  * To sum up, there are three levels of mappings involved:
75  *
76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
77  *
78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
80  * (isa_irq) is the only exception in this source code.
81  */
82
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/slab.h>
90 #include <linux/smp.h>
91 #include <linux/string.h>
92 #include <linux/bootmem.h>
93
94 #include <asm/delay.h>
95 #include <asm/hw_irq.h>
96 #include <asm/io.h>
97 #include <asm/iosapic.h>
98 #include <asm/machvec.h>
99 #include <asm/processor.h>
100 #include <asm/ptrace.h>
101 #include <asm/system.h>
102
103 #undef DEBUG_INTERRUPT_ROUTING
104
105 #ifdef DEBUG_INTERRUPT_ROUTING
106 #define DBG(fmt...)     printk(fmt)
107 #else
108 #define DBG(fmt...)
109 #endif
110
111 static DEFINE_SPINLOCK(iosapic_lock);
112
113 /*
114  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
115  * vector.
116  */
117
118 #define NO_REF_RTE      0
119
120 static struct iosapic {
121         char __iomem    *addr;          /* base address of IOSAPIC */
122         unsigned int    gsi_base;       /* GSI base */
123         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
124         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
125 #ifdef CONFIG_NUMA
126         unsigned short  node;           /* numa node association via pxm */
127 #endif
128         spinlock_t      lock;           /* lock for indirect reg access */
129 } iosapic_lists[NR_IOSAPICS];
130
131 struct iosapic_rte_info {
132         struct list_head rte_list;      /* RTEs sharing the same vector */
133         char            rte_index;      /* IOSAPIC RTE index */
134         int             refcnt;         /* reference counter */
135         struct iosapic  *iosapic;
136 } ____cacheline_aligned;
137
138 static struct iosapic_intr_info {
139         struct list_head rtes;          /* RTEs using this vector (empty =>
140                                          * not an IOSAPIC interrupt) */
141         int             count;          /* # of registered RTEs */
142         u32             low32;          /* current value of low word of
143                                          * Redirection table entry */
144         unsigned int    dest;           /* destination CPU physical ID */
145         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
146         unsigned char   polarity: 1;    /* interrupt polarity
147                                          * (see iosapic.h) */
148         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
149 } iosapic_intr_info[NR_IRQS];
150
151 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
152
153 static inline void
154 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
155 {
156         unsigned long flags;
157
158         spin_lock_irqsave(&iosapic->lock, flags);
159         __iosapic_write(iosapic->addr, reg, val);
160         spin_unlock_irqrestore(&iosapic->lock, flags);
161 }
162
163 /*
164  * Find an IOSAPIC associated with a GSI
165  */
166 static inline int
167 find_iosapic (unsigned int gsi)
168 {
169         int i;
170
171         for (i = 0; i < NR_IOSAPICS; i++) {
172                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
173                     iosapic_lists[i].num_rte)
174                         return i;
175         }
176
177         return -1;
178 }
179
180 static inline int __gsi_to_irq(unsigned int gsi)
181 {
182         int irq;
183         struct iosapic_intr_info *info;
184         struct iosapic_rte_info *rte;
185
186         for (irq = 0; irq < NR_IRQS; irq++) {
187                 info = &iosapic_intr_info[irq];
188                 list_for_each_entry(rte, &info->rtes, rte_list)
189                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
190                                 return irq;
191         }
192         return -1;
193 }
194
195 int
196 gsi_to_irq (unsigned int gsi)
197 {
198         unsigned long flags;
199         int irq;
200
201         spin_lock_irqsave(&iosapic_lock, flags);
202         irq = __gsi_to_irq(gsi);
203         spin_unlock_irqrestore(&iosapic_lock, flags);
204         return irq;
205 }
206
207 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
208 {
209         struct iosapic_rte_info *rte;
210
211         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
212                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
213                         return rte;
214         return NULL;
215 }
216
217 static void
218 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
219 {
220         unsigned long pol, trigger, dmode;
221         u32 low32, high32;
222         int rte_index;
223         char redir;
224         struct iosapic_rte_info *rte;
225         ia64_vector vector = irq_to_vector(irq);
226
227         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
228
229         rte = find_rte(irq, gsi);
230         if (!rte)
231                 return;         /* not an IOSAPIC interrupt */
232
233         rte_index = rte->rte_index;
234         pol     = iosapic_intr_info[irq].polarity;
235         trigger = iosapic_intr_info[irq].trigger;
236         dmode   = iosapic_intr_info[irq].dmode;
237
238         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
239
240 #ifdef CONFIG_SMP
241         set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
242 #endif
243
244         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
245                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
246                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
247                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
248                  vector);
249
250         /* dest contains both id and eid */
251         high32 = (dest << IOSAPIC_DEST_SHIFT);
252
253         iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
254         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
255         iosapic_intr_info[irq].low32 = low32;
256         iosapic_intr_info[irq].dest = dest;
257 }
258
259 static void
260 nop (unsigned int irq)
261 {
262         /* do nothing... */
263 }
264
265
266 #ifdef CONFIG_KEXEC
267 void
268 kexec_disable_iosapic(void)
269 {
270         struct iosapic_intr_info *info;
271         struct iosapic_rte_info *rte;
272         ia64_vector vec;
273         int irq;
274
275         for (irq = 0; irq < NR_IRQS; irq++) {
276                 info = &iosapic_intr_info[irq];
277                 vec = irq_to_vector(irq);
278                 list_for_each_entry(rte, &info->rtes,
279                                 rte_list) {
280                         iosapic_write(rte->iosapic,
281                                         IOSAPIC_RTE_LOW(rte->rte_index),
282                                         IOSAPIC_MASK|vec);
283                         iosapic_eoi(rte->iosapic->addr, vec);
284                 }
285         }
286 }
287 #endif
288
289 static void
290 mask_irq (unsigned int irq)
291 {
292         u32 low32;
293         int rte_index;
294         struct iosapic_rte_info *rte;
295
296         if (!iosapic_intr_info[irq].count)
297                 return;                 /* not an IOSAPIC interrupt! */
298
299         /* set only the mask bit */
300         low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
301         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
302                 rte_index = rte->rte_index;
303                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
304         }
305 }
306
307 static void
308 unmask_irq (unsigned int irq)
309 {
310         u32 low32;
311         int rte_index;
312         struct iosapic_rte_info *rte;
313
314         if (!iosapic_intr_info[irq].count)
315                 return;                 /* not an IOSAPIC interrupt! */
316
317         low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
318         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
319                 rte_index = rte->rte_index;
320                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
321         }
322 }
323
324
325 static int
326 iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
327 {
328 #ifdef CONFIG_SMP
329         u32 high32, low32;
330         int cpu, dest, rte_index;
331         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
332         struct iosapic_rte_info *rte;
333         struct iosapic *iosapic;
334
335         irq &= (~IA64_IRQ_REDIRECTED);
336
337         cpu = cpumask_first_and(cpu_online_mask, mask);
338         if (cpu >= nr_cpu_ids)
339                 return -1;
340
341         if (irq_prepare_move(irq, cpu))
342                 return -1;
343
344         dest = cpu_physical_id(cpu);
345
346         if (!iosapic_intr_info[irq].count)
347                 return -1;                      /* not an IOSAPIC interrupt */
348
349         set_irq_affinity_info(irq, dest, redir);
350
351         /* dest contains both id and eid */
352         high32 = dest << IOSAPIC_DEST_SHIFT;
353
354         low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
355         if (redir)
356                 /* change delivery mode to lowest priority */
357                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
358         else
359                 /* change delivery mode to fixed */
360                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
361         low32 &= IOSAPIC_VECTOR_MASK;
362         low32 |= irq_to_vector(irq);
363
364         iosapic_intr_info[irq].low32 = low32;
365         iosapic_intr_info[irq].dest = dest;
366         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
367                 iosapic = rte->iosapic;
368                 rte_index = rte->rte_index;
369                 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
370                 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
371         }
372
373 #endif
374         return 0;
375 }
376
377 /*
378  * Handlers for level-triggered interrupts.
379  */
380
381 static unsigned int
382 iosapic_startup_level_irq (unsigned int irq)
383 {
384         unmask_irq(irq);
385         return 0;
386 }
387
388 static void
389 iosapic_unmask_level_irq (unsigned int irq)
390 {
391         ia64_vector vec = irq_to_vector(irq);
392         struct iosapic_rte_info *rte;
393         int do_unmask_irq = 0;
394
395         irq_complete_move(irq);
396         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
397                 do_unmask_irq = 1;
398                 mask_irq(irq);
399         } else
400                 unmask_irq(irq);
401
402         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
403                 iosapic_eoi(rte->iosapic->addr, vec);
404
405         if (unlikely(do_unmask_irq)) {
406                 move_masked_irq(irq);
407                 unmask_irq(irq);
408         }
409 }
410
411 #define iosapic_shutdown_level_irq      mask_irq
412 #define iosapic_enable_level_irq        unmask_irq
413 #define iosapic_disable_level_irq       mask_irq
414 #define iosapic_ack_level_irq           nop
415
416 static struct irq_chip irq_type_iosapic_level = {
417         .name =         "IO-SAPIC-level",
418         .startup =      iosapic_startup_level_irq,
419         .shutdown =     iosapic_shutdown_level_irq,
420         .enable =       iosapic_enable_level_irq,
421         .disable =      iosapic_disable_level_irq,
422         .ack =          iosapic_ack_level_irq,
423         .mask =         mask_irq,
424         .unmask =       iosapic_unmask_level_irq,
425         .set_affinity = iosapic_set_affinity
426 };
427
428 /*
429  * Handlers for edge-triggered interrupts.
430  */
431
432 static unsigned int
433 iosapic_startup_edge_irq (unsigned int irq)
434 {
435         unmask_irq(irq);
436         /*
437          * IOSAPIC simply drops interrupts pended while the
438          * corresponding pin was masked, so we can't know if an
439          * interrupt is pending already.  Let's hope not...
440          */
441         return 0;
442 }
443
444 static void
445 iosapic_ack_edge_irq (unsigned int irq)
446 {
447         struct irq_desc *idesc = irq_desc + irq;
448
449         irq_complete_move(irq);
450         move_native_irq(irq);
451         /*
452          * Once we have recorded IRQ_PENDING already, we can mask the
453          * interrupt for real. This prevents IRQ storms from unhandled
454          * devices.
455          */
456         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
457             (IRQ_PENDING|IRQ_DISABLED))
458                 mask_irq(irq);
459 }
460
461 #define iosapic_enable_edge_irq         unmask_irq
462 #define iosapic_disable_edge_irq        nop
463 #define iosapic_end_edge_irq            nop
464
465 static struct irq_chip irq_type_iosapic_edge = {
466         .name =         "IO-SAPIC-edge",
467         .startup =      iosapic_startup_edge_irq,
468         .shutdown =     iosapic_disable_edge_irq,
469         .enable =       iosapic_enable_edge_irq,
470         .disable =      iosapic_disable_edge_irq,
471         .ack =          iosapic_ack_edge_irq,
472         .end =          iosapic_end_edge_irq,
473         .mask =         mask_irq,
474         .unmask =       unmask_irq,
475         .set_affinity = iosapic_set_affinity
476 };
477
478 static unsigned int
479 iosapic_version (char __iomem *addr)
480 {
481         /*
482          * IOSAPIC Version Register return 32 bit structure like:
483          * {
484          *      unsigned int version   : 8;
485          *      unsigned int reserved1 : 8;
486          *      unsigned int max_redir : 8;
487          *      unsigned int reserved2 : 8;
488          * }
489          */
490         return __iosapic_read(addr, IOSAPIC_VERSION);
491 }
492
493 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
494 {
495         int i, irq = -ENOSPC, min_count = -1;
496         struct iosapic_intr_info *info;
497
498         /*
499          * shared vectors for edge-triggered interrupts are not
500          * supported yet
501          */
502         if (trigger == IOSAPIC_EDGE)
503                 return -EINVAL;
504
505         for (i = 0; i < NR_IRQS; i++) {
506                 info = &iosapic_intr_info[i];
507                 if (info->trigger == trigger && info->polarity == pol &&
508                     (info->dmode == IOSAPIC_FIXED ||
509                      info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
510                     can_request_irq(i, IRQF_SHARED)) {
511                         if (min_count == -1 || info->count < min_count) {
512                                 irq = i;
513                                 min_count = info->count;
514                         }
515                 }
516         }
517         return irq;
518 }
519
520 /*
521  * if the given vector is already owned by other,
522  *  assign a new vector for the other and make the vector available
523  */
524 static void __init
525 iosapic_reassign_vector (int irq)
526 {
527         int new_irq;
528
529         if (iosapic_intr_info[irq].count) {
530                 new_irq = create_irq();
531                 if (new_irq < 0)
532                         panic("%s: out of interrupt vectors!\n", __func__);
533                 printk(KERN_INFO "Reassigning vector %d to %d\n",
534                        irq_to_vector(irq), irq_to_vector(new_irq));
535                 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
536                        sizeof(struct iosapic_intr_info));
537                 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
538                 list_move(iosapic_intr_info[irq].rtes.next,
539                           &iosapic_intr_info[new_irq].rtes);
540                 memset(&iosapic_intr_info[irq], 0,
541                        sizeof(struct iosapic_intr_info));
542                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
543                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
544         }
545 }
546
547 static inline int irq_is_shared (int irq)
548 {
549         return (iosapic_intr_info[irq].count > 1);
550 }
551
552 struct irq_chip*
553 ia64_native_iosapic_get_irq_chip(unsigned long trigger)
554 {
555         if (trigger == IOSAPIC_EDGE)
556                 return &irq_type_iosapic_edge;
557         else
558                 return &irq_type_iosapic_level;
559 }
560
561 static int
562 register_intr (unsigned int gsi, int irq, unsigned char delivery,
563                unsigned long polarity, unsigned long trigger)
564 {
565         struct irq_desc *idesc;
566         struct irq_chip *irq_type;
567         int index;
568         struct iosapic_rte_info *rte;
569
570         index = find_iosapic(gsi);
571         if (index < 0) {
572                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
573                        __func__, gsi);
574                 return -ENODEV;
575         }
576
577         rte = find_rte(irq, gsi);
578         if (!rte) {
579                 rte = kzalloc(sizeof (*rte), GFP_ATOMIC);
580                 if (!rte) {
581                         printk(KERN_WARNING "%s: cannot allocate memory\n",
582                                __func__);
583                         return -ENOMEM;
584                 }
585
586                 rte->iosapic    = &iosapic_lists[index];
587                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
588                 rte->refcnt++;
589                 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
590                 iosapic_intr_info[irq].count++;
591                 iosapic_lists[index].rtes_inuse++;
592         }
593         else if (rte->refcnt == NO_REF_RTE) {
594                 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
595                 if (info->count > 0 &&
596                     (info->trigger != trigger || info->polarity != polarity)){
597                         printk (KERN_WARNING
598                                 "%s: cannot override the interrupt\n",
599                                 __func__);
600                         return -EINVAL;
601                 }
602                 rte->refcnt++;
603                 iosapic_intr_info[irq].count++;
604                 iosapic_lists[index].rtes_inuse++;
605         }
606
607         iosapic_intr_info[irq].polarity = polarity;
608         iosapic_intr_info[irq].dmode    = delivery;
609         iosapic_intr_info[irq].trigger  = trigger;
610
611         irq_type = iosapic_get_irq_chip(trigger);
612
613         idesc = irq_desc + irq;
614         if (irq_type != NULL && idesc->chip != irq_type) {
615                 if (idesc->chip != &no_irq_chip)
616                         printk(KERN_WARNING
617                                "%s: changing vector %d from %s to %s\n",
618                                __func__, irq_to_vector(irq),
619                                idesc->chip->name, irq_type->name);
620                 idesc->chip = irq_type;
621         }
622         if (trigger == IOSAPIC_EDGE)
623                 __set_irq_handler_unlocked(irq, handle_edge_irq);
624         else
625                 __set_irq_handler_unlocked(irq, handle_level_irq);
626         return 0;
627 }
628
629 static unsigned int
630 get_target_cpu (unsigned int gsi, int irq)
631 {
632 #ifdef CONFIG_SMP
633         static int cpu = -1;
634         extern int cpe_vector;
635         cpumask_t domain = irq_to_domain(irq);
636
637         /*
638          * In case of vector shared by multiple RTEs, all RTEs that
639          * share the vector need to use the same destination CPU.
640          */
641         if (iosapic_intr_info[irq].count)
642                 return iosapic_intr_info[irq].dest;
643
644         /*
645          * If the platform supports redirection via XTP, let it
646          * distribute interrupts.
647          */
648         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
649                 return cpu_physical_id(smp_processor_id());
650
651         /*
652          * Some interrupts (ACPI SCI, for instance) are registered
653          * before the BSP is marked as online.
654          */
655         if (!cpu_online(smp_processor_id()))
656                 return cpu_physical_id(smp_processor_id());
657
658 #ifdef CONFIG_ACPI
659         if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
660                 return get_cpei_target_cpu();
661 #endif
662
663 #ifdef CONFIG_NUMA
664         {
665                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
666                 const struct cpumask *cpu_mask;
667
668                 iosapic_index = find_iosapic(gsi);
669                 if (iosapic_index < 0 ||
670                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
671                         goto skip_numa_setup;
672
673                 cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node);
674                 num_cpus = 0;
675                 for_each_cpu_and(numa_cpu, cpu_mask, &domain) {
676                         if (cpu_online(numa_cpu))
677                                 num_cpus++;
678                 }
679
680                 if (!num_cpus)
681                         goto skip_numa_setup;
682
683                 /* Use irq assignment to distribute across cpus in node */
684                 cpu_index = irq % num_cpus;
685
686                 for_each_cpu_and(numa_cpu, cpu_mask, &domain)
687                         if (cpu_online(numa_cpu) && i++ >= cpu_index)
688                                 break;
689
690                 if (numa_cpu < nr_cpu_ids)
691                         return cpu_physical_id(numa_cpu);
692         }
693 skip_numa_setup:
694 #endif
695         /*
696          * Otherwise, round-robin interrupt vectors across all the
697          * processors.  (It'd be nice if we could be smarter in the
698          * case of NUMA.)
699          */
700         do {
701                 if (++cpu >= nr_cpu_ids)
702                         cpu = 0;
703         } while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
704
705         return cpu_physical_id(cpu);
706 #else  /* CONFIG_SMP */
707         return cpu_physical_id(smp_processor_id());
708 #endif
709 }
710
711 static inline unsigned char choose_dmode(void)
712 {
713 #ifdef CONFIG_SMP
714         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
715                 return IOSAPIC_LOWEST_PRIORITY;
716 #endif
717         return IOSAPIC_FIXED;
718 }
719
720 /*
721  * ACPI can describe IOSAPIC interrupts via static tables and namespace
722  * methods.  This provides an interface to register those interrupts and
723  * program the IOSAPIC RTE.
724  */
725 int
726 iosapic_register_intr (unsigned int gsi,
727                        unsigned long polarity, unsigned long trigger)
728 {
729         int irq, mask = 1, err;
730         unsigned int dest;
731         unsigned long flags;
732         struct iosapic_rte_info *rte;
733         u32 low32;
734         unsigned char dmode;
735
736         /*
737          * If this GSI has already been registered (i.e., it's a
738          * shared interrupt, or we lost a race to register it),
739          * don't touch the RTE.
740          */
741         spin_lock_irqsave(&iosapic_lock, flags);
742         irq = __gsi_to_irq(gsi);
743         if (irq > 0) {
744                 rte = find_rte(irq, gsi);
745                 if(iosapic_intr_info[irq].count == 0) {
746                         assign_irq_vector(irq);
747                         dynamic_irq_init(irq);
748                 } else if (rte->refcnt != NO_REF_RTE) {
749                         rte->refcnt++;
750                         goto unlock_iosapic_lock;
751                 }
752         } else
753                 irq = create_irq();
754
755         /* If vector is running out, we try to find a sharable vector */
756         if (irq < 0) {
757                 irq = iosapic_find_sharable_irq(trigger, polarity);
758                 if (irq < 0)
759                         goto unlock_iosapic_lock;
760         }
761
762         raw_spin_lock(&irq_desc[irq].lock);
763         dest = get_target_cpu(gsi, irq);
764         dmode = choose_dmode();
765         err = register_intr(gsi, irq, dmode, polarity, trigger);
766         if (err < 0) {
767                 raw_spin_unlock(&irq_desc[irq].lock);
768                 irq = err;
769                 goto unlock_iosapic_lock;
770         }
771
772         /*
773          * If the vector is shared and already unmasked for other
774          * interrupt sources, don't mask it.
775          */
776         low32 = iosapic_intr_info[irq].low32;
777         if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
778                 mask = 0;
779         set_rte(gsi, irq, dest, mask);
780
781         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
782                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
783                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
784                cpu_logical_id(dest), dest, irq_to_vector(irq));
785
786         raw_spin_unlock(&irq_desc[irq].lock);
787  unlock_iosapic_lock:
788         spin_unlock_irqrestore(&iosapic_lock, flags);
789         return irq;
790 }
791
792 void
793 iosapic_unregister_intr (unsigned int gsi)
794 {
795         unsigned long flags;
796         int irq, index;
797         struct irq_desc *idesc;
798         u32 low32;
799         unsigned long trigger, polarity;
800         unsigned int dest;
801         struct iosapic_rte_info *rte;
802
803         /*
804          * If the irq associated with the gsi is not found,
805          * iosapic_unregister_intr() is unbalanced. We need to check
806          * this again after getting locks.
807          */
808         irq = gsi_to_irq(gsi);
809         if (irq < 0) {
810                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
811                        gsi);
812                 WARN_ON(1);
813                 return;
814         }
815
816         spin_lock_irqsave(&iosapic_lock, flags);
817         if ((rte = find_rte(irq, gsi)) == NULL) {
818                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
819                        gsi);
820                 WARN_ON(1);
821                 goto out;
822         }
823
824         if (--rte->refcnt > 0)
825                 goto out;
826
827         idesc = irq_desc + irq;
828         rte->refcnt = NO_REF_RTE;
829
830         /* Mask the interrupt */
831         low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
832         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
833
834         iosapic_intr_info[irq].count--;
835         index = find_iosapic(gsi);
836         iosapic_lists[index].rtes_inuse--;
837         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
838
839         trigger  = iosapic_intr_info[irq].trigger;
840         polarity = iosapic_intr_info[irq].polarity;
841         dest     = iosapic_intr_info[irq].dest;
842         printk(KERN_INFO
843                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
844                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
845                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
846                cpu_logical_id(dest), dest, irq_to_vector(irq));
847
848         if (iosapic_intr_info[irq].count == 0) {
849 #ifdef CONFIG_SMP
850                 /* Clear affinity */
851                 cpumask_setall(idesc->affinity);
852 #endif
853                 /* Clear the interrupt information */
854                 iosapic_intr_info[irq].dest = 0;
855                 iosapic_intr_info[irq].dmode = 0;
856                 iosapic_intr_info[irq].polarity = 0;
857                 iosapic_intr_info[irq].trigger = 0;
858                 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
859
860                 /* Destroy and reserve IRQ */
861                 destroy_and_reserve_irq(irq);
862         }
863  out:
864         spin_unlock_irqrestore(&iosapic_lock, flags);
865 }
866
867 /*
868  * ACPI calls this when it finds an entry for a platform interrupt.
869  */
870 int __init
871 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
872                                 int iosapic_vector, u16 eid, u16 id,
873                                 unsigned long polarity, unsigned long trigger)
874 {
875         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
876         unsigned char delivery;
877         int irq, vector, mask = 0;
878         unsigned int dest = ((id << 8) | eid) & 0xffff;
879
880         switch (int_type) {
881               case ACPI_INTERRUPT_PMI:
882                 irq = vector = iosapic_vector;
883                 bind_irq_vector(irq, vector, CPU_MASK_ALL);
884                 /*
885                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
886                  * we need to make sure the vector is available
887                  */
888                 iosapic_reassign_vector(irq);
889                 delivery = IOSAPIC_PMI;
890                 break;
891               case ACPI_INTERRUPT_INIT:
892                 irq = create_irq();
893                 if (irq < 0)
894                         panic("%s: out of interrupt vectors!\n", __func__);
895                 vector = irq_to_vector(irq);
896                 delivery = IOSAPIC_INIT;
897                 break;
898               case ACPI_INTERRUPT_CPEI:
899                 irq = vector = IA64_CPE_VECTOR;
900                 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
901                 delivery = IOSAPIC_FIXED;
902                 mask = 1;
903                 break;
904               default:
905                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__,
906                        int_type);
907                 return -1;
908         }
909
910         register_intr(gsi, irq, delivery, polarity, trigger);
911
912         printk(KERN_INFO
913                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
914                " vector %d\n",
915                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
916                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
917                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
918                cpu_logical_id(dest), dest, vector);
919
920         set_rte(gsi, irq, dest, mask);
921         return vector;
922 }
923
924 /*
925  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
926  */
927 void __devinit
928 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
929                           unsigned long polarity,
930                           unsigned long trigger)
931 {
932         int vector, irq;
933         unsigned int dest = cpu_physical_id(smp_processor_id());
934         unsigned char dmode;
935
936         irq = vector = isa_irq_to_vector(isa_irq);
937         BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
938         dmode = choose_dmode();
939         register_intr(gsi, irq, dmode, polarity, trigger);
940
941         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
942             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
943             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
944             cpu_logical_id(dest), dest, vector);
945
946         set_rte(gsi, irq, dest, 1);
947 }
948
949 void __init
950 ia64_native_iosapic_pcat_compat_init(void)
951 {
952         if (pcat_compat) {
953                 /*
954                  * Disable the compatibility mode interrupts (8259 style),
955                  * needs IN/OUT support enabled.
956                  */
957                 printk(KERN_INFO
958                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
959                        __func__);
960                 outb(0xff, 0xA1);
961                 outb(0xff, 0x21);
962         }
963 }
964
965 void __init
966 iosapic_system_init (int system_pcat_compat)
967 {
968         int irq;
969
970         for (irq = 0; irq < NR_IRQS; ++irq) {
971                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
972                 /* mark as unused */
973                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
974
975                 iosapic_intr_info[irq].count = 0;
976         }
977
978         pcat_compat = system_pcat_compat;
979         if (pcat_compat)
980                 iosapic_pcat_compat_init();
981 }
982
983 static inline int
984 iosapic_alloc (void)
985 {
986         int index;
987
988         for (index = 0; index < NR_IOSAPICS; index++)
989                 if (!iosapic_lists[index].addr)
990                         return index;
991
992         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__);
993         return -1;
994 }
995
996 static inline void
997 iosapic_free (int index)
998 {
999         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1000 }
1001
1002 static inline int
1003 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1004 {
1005         int index;
1006         unsigned int gsi_end, base, end;
1007
1008         /* check gsi range */
1009         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1010         for (index = 0; index < NR_IOSAPICS; index++) {
1011                 if (!iosapic_lists[index].addr)
1012                         continue;
1013
1014                 base = iosapic_lists[index].gsi_base;
1015                 end  = base + iosapic_lists[index].num_rte - 1;
1016
1017                 if (gsi_end < base || end < gsi_base)
1018                         continue; /* OK */
1019
1020                 return -EBUSY;
1021         }
1022         return 0;
1023 }
1024
1025 int __devinit
1026 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1027 {
1028         int num_rte, err, index;
1029         unsigned int isa_irq, ver;
1030         char __iomem *addr;
1031         unsigned long flags;
1032
1033         spin_lock_irqsave(&iosapic_lock, flags);
1034         index = find_iosapic(gsi_base);
1035         if (index >= 0) {
1036                 spin_unlock_irqrestore(&iosapic_lock, flags);
1037                 return -EBUSY;
1038         }
1039
1040         addr = ioremap(phys_addr, 0);
1041         if (addr == NULL) {
1042                 spin_unlock_irqrestore(&iosapic_lock, flags);
1043                 return -ENOMEM;
1044         }
1045         ver = iosapic_version(addr);
1046         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1047                 iounmap(addr);
1048                 spin_unlock_irqrestore(&iosapic_lock, flags);
1049                 return err;
1050         }
1051
1052         /*
1053          * The MAX_REDIR register holds the highest input pin number
1054          * (starting from 0).  We add 1 so that we can use it for
1055          * number of pins (= RTEs)
1056          */
1057         num_rte = ((ver >> 16) & 0xff) + 1;
1058
1059         index = iosapic_alloc();
1060         iosapic_lists[index].addr = addr;
1061         iosapic_lists[index].gsi_base = gsi_base;
1062         iosapic_lists[index].num_rte = num_rte;
1063 #ifdef CONFIG_NUMA
1064         iosapic_lists[index].node = MAX_NUMNODES;
1065 #endif
1066         spin_lock_init(&iosapic_lists[index].lock);
1067         spin_unlock_irqrestore(&iosapic_lock, flags);
1068
1069         if ((gsi_base == 0) && pcat_compat) {
1070                 /*
1071                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1072                  * these may get reprogrammed later on with data from the ACPI
1073                  * Interrupt Source Override table.
1074                  */
1075                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1076                         iosapic_override_isa_irq(isa_irq, isa_irq,
1077                                                  IOSAPIC_POL_HIGH,
1078                                                  IOSAPIC_EDGE);
1079         }
1080         return 0;
1081 }
1082
1083 #ifdef CONFIG_HOTPLUG
1084 int
1085 iosapic_remove (unsigned int gsi_base)
1086 {
1087         int index, err = 0;
1088         unsigned long flags;
1089
1090         spin_lock_irqsave(&iosapic_lock, flags);
1091         index = find_iosapic(gsi_base);
1092         if (index < 0) {
1093                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1094                        __func__, gsi_base);
1095                 goto out;
1096         }
1097
1098         if (iosapic_lists[index].rtes_inuse) {
1099                 err = -EBUSY;
1100                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1101                        __func__, gsi_base);
1102                 goto out;
1103         }
1104
1105         iounmap(iosapic_lists[index].addr);
1106         iosapic_free(index);
1107  out:
1108         spin_unlock_irqrestore(&iosapic_lock, flags);
1109         return err;
1110 }
1111 #endif /* CONFIG_HOTPLUG */
1112
1113 #ifdef CONFIG_NUMA
1114 void __devinit
1115 map_iosapic_to_node(unsigned int gsi_base, int node)
1116 {
1117         int index;
1118
1119         index = find_iosapic(gsi_base);
1120         if (index < 0) {
1121                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1122                        __func__, gsi_base);
1123                 return;
1124         }
1125         iosapic_lists[index].node = node;
1126         return;
1127 }
1128 #endif