Blackfin: decouple unrelated cache settings to get exact behavior
[linux-2.6.git] / arch / blackfin / mach-common / pm.c
1 /*
2  * File:         arch/blackfin/mach-common/pm.c
3  * Based on:     arm/mach-omap/pm.c
4  * Author:       Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
5  *
6  * Created:      2001
7  * Description:  Blackfin power management
8  *
9  * Modified:     Nicolas Pitre - PXA250 support
10  *                Copyright (c) 2002 Monta Vista Software, Inc.
11  *               David Singleton - OMAP1510
12  *                Copyright (c) 2002 Monta Vista Software, Inc.
13  *               Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
14  *                Copyright 2004
15  *               Copyright 2004-2008 Analog Devices Inc.
16  *
17  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program; if not, see the file COPYING, or write
31  * to the Free Software Foundation, Inc.,
32  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
33  */
34
35 #include <linux/suspend.h>
36 #include <linux/sched.h>
37 #include <linux/proc_fs.h>
38 #include <linux/io.h>
39 #include <linux/irq.h>
40
41 #include <asm/gpio.h>
42 #include <asm/dma.h>
43 #include <asm/dpmc.h>
44
45 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
46 #define WAKEUP_TYPE     PM_WAKE_HIGH
47 #endif
48
49 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
50 #define WAKEUP_TYPE     PM_WAKE_LOW
51 #endif
52
53 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
54 #define WAKEUP_TYPE     PM_WAKE_FALLING
55 #endif
56
57 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
58 #define WAKEUP_TYPE     PM_WAKE_RISING
59 #endif
60
61 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
62 #define WAKEUP_TYPE     PM_WAKE_BOTH_EDGES
63 #endif
64
65
66 void bfin_pm_suspend_standby_enter(void)
67 {
68         unsigned long flags;
69
70 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
71         gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
72 #endif
73
74         local_irq_save_hw(flags);
75         bfin_pm_standby_setup();
76
77 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
78         sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
79 #else
80         sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
81 #endif
82
83         bfin_pm_standby_restore();
84
85 #ifdef SIC_IWR0
86         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
87 # ifdef SIC_IWR1
88         /* BF52x system reset does not properly reset SIC_IWR1 which
89          * will screw up the bootrom as it relies on MDMA0/1 waking it
90          * up from IDLE instructions.  See this report for more info:
91          * http://blackfin.uclinux.org/gf/tracker/4323
92          */
93         if (ANOMALY_05000435)
94                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
95         else
96                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
97 # endif
98 # ifdef SIC_IWR2
99         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
100 # endif
101 #else
102         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
103 #endif
104
105         local_irq_restore_hw(flags);
106 }
107
108 int bf53x_suspend_l1_mem(unsigned char *memptr)
109 {
110         dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
111         dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
112                         L1_DATA_A_LENGTH);
113         dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
114                         (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
115         memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
116                         L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
117                         L1_SCRATCH_LENGTH);
118
119         return 0;
120 }
121
122 int bf53x_resume_l1_mem(unsigned char *memptr)
123 {
124         dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
125         dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
126                         L1_DATA_A_LENGTH);
127         dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
128                         L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
129         memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
130                         L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
131
132         return 0;
133 }
134
135 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
136 static void flushinv_all_dcache(void)
137 {
138         u32 way, bank, subbank, set;
139         u32 status, addr;
140         u32 dmem_ctl = bfin_read_DMEM_CONTROL();
141
142         for (bank = 0; bank < 2; ++bank) {
143                 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
144                         continue;
145
146                 for (way = 0; way < 2; ++way)
147                         for (subbank = 0; subbank < 4; ++subbank)
148                                 for (set = 0; set < 64; ++set) {
149
150                                         bfin_write_DTEST_COMMAND(
151                                                 way << 26 |
152                                                 bank << 23 |
153                                                 subbank << 16 |
154                                                 set << 5
155                                         );
156                                         CSYNC();
157                                         status = bfin_read_DTEST_DATA0();
158
159                                         /* only worry about valid/dirty entries */
160                                         if ((status & 0x3) != 0x3)
161                                                 continue;
162
163                                         /* construct the address using the tag */
164                                         addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
165
166                                         /* flush it */
167                                         __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
168                                 }
169         }
170 }
171 #endif
172
173 static inline void dcache_disable(void)
174 {
175 #ifdef CONFIG_BFIN_DCACHE
176         unsigned long ctrl;
177
178 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
179         flushinv_all_dcache();
180 #endif
181         SSYNC();
182         ctrl = bfin_read_DMEM_CONTROL();
183         ctrl &= ~ENDCPLB;
184         bfin_write_DMEM_CONTROL(ctrl);
185         SSYNC();
186 #endif
187 }
188
189 static inline void dcache_enable(void)
190 {
191 #ifdef CONFIG_BFIN_DCACHE
192         unsigned long ctrl;
193         SSYNC();
194         ctrl = bfin_read_DMEM_CONTROL();
195         ctrl |= ENDCPLB;
196         bfin_write_DMEM_CONTROL(ctrl);
197         SSYNC();
198 #endif
199 }
200
201 static inline void icache_disable(void)
202 {
203 #ifdef CONFIG_BFIN_ICACHE
204         unsigned long ctrl;
205         SSYNC();
206         ctrl = bfin_read_IMEM_CONTROL();
207         ctrl &= ~ENICPLB;
208         bfin_write_IMEM_CONTROL(ctrl);
209         SSYNC();
210 #endif
211 }
212
213 static inline void icache_enable(void)
214 {
215 #ifdef CONFIG_BFIN_ICACHE
216         unsigned long ctrl;
217         SSYNC();
218         ctrl = bfin_read_IMEM_CONTROL();
219         ctrl |= ENICPLB;
220         bfin_write_IMEM_CONTROL(ctrl);
221         SSYNC();
222 #endif
223 }
224
225 int bfin_pm_suspend_mem_enter(void)
226 {
227         unsigned long flags;
228         int wakeup, ret;
229
230         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
231                                          + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
232                                           GFP_KERNEL);
233
234         if (memptr == NULL) {
235                 panic("bf53x_suspend_l1_mem malloc failed");
236                 return -ENOMEM;
237         }
238
239         wakeup = bfin_read_VR_CTL() & ~FREQ;
240         wakeup |= SCKELOW;
241
242 #ifdef CONFIG_PM_BFIN_WAKE_PH6
243         wakeup |= PHYWE;
244 #endif
245 #ifdef CONFIG_PM_BFIN_WAKE_GP
246         wakeup |= GPWE;
247 #endif
248
249         local_irq_save_hw(flags);
250
251         ret = blackfin_dma_suspend();
252
253         if (ret) {
254                 local_irq_restore_hw(flags);
255                 kfree(memptr);
256                 return ret;
257         }
258
259         bfin_gpio_pm_hibernate_suspend();
260
261         dcache_disable();
262         icache_disable();
263         bf53x_suspend_l1_mem(memptr);
264
265         do_hibernate(wakeup | vr_wakeup);       /* Goodbye */
266
267         bf53x_resume_l1_mem(memptr);
268
269         icache_enable();
270         dcache_enable();
271
272         bfin_gpio_pm_hibernate_restore();
273         blackfin_dma_resume();
274
275         local_irq_restore_hw(flags);
276         kfree(memptr);
277
278         return 0;
279 }
280
281 /*
282  *      bfin_pm_valid - Tell the PM core that we only support the standby sleep
283  *                      state
284  *      @state:         suspend state we're checking.
285  *
286  */
287 static int bfin_pm_valid(suspend_state_t state)
288 {
289         return (state == PM_SUSPEND_STANDBY
290 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
291         /*
292          * On BF533/2/1:
293          * If we enter Hibernate the SCKE Pin is driven Low,
294          * so that the SDRAM enters Self Refresh Mode.
295          * However when the reset sequence that follows hibernate
296          * state is executed, SCKE is driven High, taking the
297          * SDRAM out of Self Refresh.
298          *
299          * If you reconfigure and access the SDRAM "very quickly",
300          * you are likely to avoid errors, otherwise the SDRAM
301          * start losing its contents.
302          * An external HW workaround is possible using logic gates.
303          */
304         || state == PM_SUSPEND_MEM
305 #endif
306         );
307 }
308
309 /*
310  *      bfin_pm_enter - Actually enter a sleep state.
311  *      @state:         State we're entering.
312  *
313  */
314 static int bfin_pm_enter(suspend_state_t state)
315 {
316         switch (state) {
317         case PM_SUSPEND_STANDBY:
318                 bfin_pm_suspend_standby_enter();
319                 break;
320         case PM_SUSPEND_MEM:
321                 bfin_pm_suspend_mem_enter();
322                 break;
323         default:
324                 return -EINVAL;
325         }
326
327         return 0;
328 }
329
330 struct platform_suspend_ops bfin_pm_ops = {
331         .enter = bfin_pm_enter,
332         .valid  = bfin_pm_valid,
333 };
334
335 static int __init bfin_pm_init(void)
336 {
337         suspend_set_ops(&bfin_pm_ops);
338         return 0;
339 }
340
341 __initcall(bfin_pm_init);