Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6.git] / arch / blackfin / mach-bf561 / include / mach / blackfin.h
1 /*
2  * Copyright 2005-2009 Analog Devices Inc.
3  *
4  * Licensed under the GPL-2 or later.
5  */
6
7 #ifndef _MACH_BLACKFIN_H_
8 #define _MACH_BLACKFIN_H_
9
10 #define BF561_FAMILY
11
12 #include "bf561.h"
13 #include "defBF561.h"
14 #include "anomaly.h"
15
16 #if !defined(__ASSEMBLY__)
17 #include "cdefBF561.h"
18 #endif
19
20 #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
21 #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
22 #define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
23 #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
24 #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
25 #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
26
27 /* Weird muxer funcs which pick SIC regs from IMASK base */
28 #define __SIC_MUX(base, x)              ((base) + ((x) << 2))
29 #define bfin_read_SIC_IMASK(x)          bfin_read32(__SIC_MUX(SIC_IMASK0, x))
30 #define bfin_write_SIC_IMASK(x, val)    bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
31 #define bfin_read_SICB_IMASK(x)         bfin_read32(__SIC_MUX(SICB_IMASK0, x))
32 #define bfin_write_SICB_IMASK(x, val)   bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
33 #define bfin_read_SIC_ISR(x)            bfin_read32(__SIC_MUX(SIC_ISR0, x))
34 #define bfin_write_SIC_ISR(x, val)      bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
35 #define bfin_read_SICB_ISR(x)           bfin_read32(__SIC_MUX(SICB_ISR0, x))
36 #define bfin_write_SICB_ISR(x, val)     bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37
38 #define BFIN_UART_NR_PORTS      1
39
40 #define OFFSET_THR              0x00    /* Transmit Holding register            */
41 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
42 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
43 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
44 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
45 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
46 #define OFFSET_LCR              0x0C    /* Line Control Register                */
47 #define OFFSET_MCR              0x10    /* Modem Control Register               */
48 #define OFFSET_LSR              0x14    /* Line Status Register                 */
49 #define OFFSET_MSR              0x18    /* Modem Status Register                */
50 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
51 #define OFFSET_GCTL             0x24    /* Global Control Register              */
52
53 #endif                          /* _MACH_BLACKFIN_H_ */