Blackfin arch: to do some consolidation of common code and common name spaces
[linux-2.6.git] / arch / blackfin / kernel / cplbinit.c
1 /*
2  * Blackfin CPLB initialization
3  *
4  *               Copyright 2004-2007 Analog Devices Inc.
5  *
6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, see the file COPYING, or write
20  * to the Free Software Foundation, Inc.,
21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
22  */
23 #include <linux/module.h>
24
25 #include <asm/blackfin.h>
26 #include <asm/cplb.h>
27 #include <asm/cplbinit.h>
28
29 u_long icplb_table[MAX_CPLBS+1];
30 u_long dcplb_table[MAX_CPLBS+1];
31
32 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
33 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
34 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
35
36 #ifdef CONFIG_CPLB_INFO
37 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
38 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
39 #endif /* CONFIG_CPLB_INFO */
40
41 #else
42
43 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
44 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
45
46 #ifdef CONFIG_CPLB_INFO
47 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
48 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
49 #endif /* CONFIG_CPLB_INFO */
50
51 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
52
53 struct s_cplb {
54         struct cplb_tab init_i;
55         struct cplb_tab init_d;
56         struct cplb_tab switch_i;
57         struct cplb_tab switch_d;
58 };
59
60 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
61 static struct cplb_desc cplb_data[] = {
62         {
63                 .start = 0,
64                 .end = SIZE_1K,
65                 .psize = SIZE_1K,
66                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
67                 .i_conf = SDRAM_OOPS,
68                 .d_conf = SDRAM_OOPS,
69 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
70                 .valid = 1,
71 #else
72                 .valid = 0,
73 #endif
74                 .name = "ZERO Pointer Saveguard",
75         },
76         {
77                 .start = L1_CODE_START,
78                 .end = L1_CODE_START + L1_CODE_LENGTH,
79                 .psize = SIZE_4M,
80                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
81                 .i_conf = L1_IMEMORY,
82                 .d_conf = 0,
83                 .valid = 1,
84                 .name = "L1 I-Memory",
85         },
86         {
87                 .start = L1_DATA_A_START,
88                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
89                 .psize = SIZE_4M,
90                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
91                 .i_conf = 0,
92                 .d_conf = L1_DMEMORY,
93 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
94                 .valid = 1,
95 #else
96                 .valid = 0,
97 #endif
98                 .name = "L1 D-Memory",
99         },
100         {
101                 .start = 0,
102                 .end = 0,  /* dynamic */
103                 .psize = 0,
104                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
105                 .i_conf =  SDRAM_IGENERIC,
106                 .d_conf =  SDRAM_DGENERIC,
107                 .valid = 1,
108                 .name = "SDRAM Kernel",
109         },
110         {
111                 .start = 0, /* dynamic */
112                 .end = 0, /* dynamic */
113                 .psize = 0,
114                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
115                 .i_conf =  SDRAM_IGENERIC,
116                 .d_conf =  SDRAM_DNON_CHBL,
117                 .valid = 1,
118                 .name = "SDRAM RAM MTD",
119         },
120         {
121                 .start = 0, /* dynamic */
122                 .end = 0,   /* dynamic */
123                 .psize = SIZE_1M,
124                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
125                 .d_conf = SDRAM_DNON_CHBL,
126                 .valid = 1,
127                 .name = "SDRAM Uncached DMA ZONE",
128         },
129         {
130                 .start = 0, /* dynamic */
131                 .end = 0, /* dynamic */
132                 .psize = 0,
133                 .attr = SWITCH_T | D_CPLB,
134                 .i_conf = 0, /* dynamic */
135                 .d_conf = 0, /* dynamic */
136                 .valid = 1,
137                 .name = "SDRAM Reserved Memory",
138         },
139         {
140                 .start = ASYNC_BANK0_BASE,
141                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
142                 .psize = 0,
143                 .attr = SWITCH_T | D_CPLB,
144                 .d_conf = SDRAM_EBIU,
145                 .valid = 1,
146                 .name = "ASYNC Memory",
147         },
148         {
149 #if defined(CONFIG_BF561)
150                 .start = L2_SRAM,
151                 .end = L2_SRAM_END,
152                 .psize = SIZE_1M,
153                 .attr = SWITCH_T | D_CPLB,
154                 .i_conf = L2_MEMORY,
155                 .d_conf = L2_MEMORY,
156                 .valid = 1,
157 #else
158                 .valid = 0,
159 #endif
160                 .name = "L2 Memory",
161         }
162 };
163
164 static u16 __init lock_kernel_check(u32 start, u32 end)
165 {
166         if ((start <= (u32) _stext && end >= (u32) _end)
167             || (start >= (u32) _stext && end <= (u32) _end))
168                 return IN_KERNEL;
169         return 0;
170 }
171
172 static unsigned short __init
173 fill_cplbtab(struct cplb_tab *table,
174              unsigned long start, unsigned long end,
175              unsigned long block_size, unsigned long cplb_data)
176 {
177         int i;
178
179         switch (block_size) {
180         case SIZE_4M:
181                 i = 3;
182                 break;
183         case SIZE_1M:
184                 i = 2;
185                 break;
186         case SIZE_4K:
187                 i = 1;
188                 break;
189         case SIZE_1K:
190         default:
191                 i = 0;
192                 break;
193         }
194
195         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
196
197         while ((start < end) && (table->pos < table->size)) {
198
199                 table->tab[table->pos++] = start;
200
201                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
202                         table->tab[table->pos++] =
203                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
204                 else
205                         table->tab[table->pos++] = cplb_data;
206
207                 start += block_size;
208         }
209         return 0;
210 }
211
212 static unsigned short __init
213 close_cplbtab(struct cplb_tab *table)
214 {
215
216         while (table->pos < table->size) {
217
218                 table->tab[table->pos++] = 0;
219                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
220         }
221         return 0;
222 }
223
224 /* helper function */
225 static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
226 {
227         if (cplb_data[i].psize) {
228                 fill_cplbtab(t,
229                                 cplb_data[i].start,
230                                 cplb_data[i].end,
231                                 cplb_data[i].psize,
232                                 cplb_data[i].i_conf);
233         } else {
234 #if defined(CONFIG_BFIN_ICACHE)
235                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
236                         fill_cplbtab(t,
237                                         cplb_data[i].start,
238                                         cplb_data[i].end,
239                                         SIZE_4M,
240                                         cplb_data[i].i_conf);
241                 } else
242 #endif
243                 {
244                         fill_cplbtab(t,
245                                         cplb_data[i].start,
246                                         a_start,
247                                         SIZE_1M,
248                                         cplb_data[i].i_conf);
249                         fill_cplbtab(t,
250                                         a_start,
251                                         a_end,
252                                         SIZE_4M,
253                                         cplb_data[i].i_conf);
254                         fill_cplbtab(t, a_end,
255                                         cplb_data[i].end,
256                                         SIZE_1M,
257                                         cplb_data[i].i_conf);
258                 }
259         }
260 }
261
262 static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
263 {
264         if (cplb_data[i].psize) {
265                 fill_cplbtab(t,
266                                 cplb_data[i].start,
267                                 cplb_data[i].end,
268                                 cplb_data[i].psize,
269                                 cplb_data[i].d_conf);
270         } else {
271                 fill_cplbtab(t,
272                                 cplb_data[i].start,
273                                 a_start, SIZE_1M,
274                                 cplb_data[i].d_conf);
275                 fill_cplbtab(t, a_start,
276                                 a_end, SIZE_4M,
277                                 cplb_data[i].d_conf);
278                 fill_cplbtab(t, a_end,
279                                 cplb_data[i].end,
280                                 SIZE_1M,
281                                 cplb_data[i].d_conf);
282         }
283 }
284
285 void __init generate_cpl_tables(void)
286 {
287
288         u16 i, j, process;
289         u32 a_start, a_end, as, ae, as_1m;
290
291         struct cplb_tab *t_i = NULL;
292         struct cplb_tab *t_d = NULL;
293         struct s_cplb cplb;
294
295         cplb.init_i.size = MAX_CPLBS;
296         cplb.init_d.size = MAX_CPLBS;
297         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
298         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
299
300         cplb.init_i.pos = 0;
301         cplb.init_d.pos = 0;
302         cplb.switch_i.pos = 0;
303         cplb.switch_d.pos = 0;
304
305         cplb.init_i.tab = icplb_table;
306         cplb.init_d.tab = dcplb_table;
307         cplb.switch_i.tab = ipdt_table;
308         cplb.switch_d.tab = dpdt_table;
309
310         cplb_data[SDRAM_KERN].end = memory_end;
311
312 #ifdef CONFIG_MTD_UCLINUX
313         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
314         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
315         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
316 # if defined(CONFIG_ROMFS_FS)
317         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
318
319         /*
320          * The ROMFS_FS size is often not multiple of 1MB.
321          * This can cause multiple CPLB sets covering the same memory area.
322          * This will then cause multiple CPLB hit exceptions.
323          * Workaround: We ensure a contiguous memory area by extending the kernel
324          * memory section over the mtd section.
325          * For ROMFS_FS memory must be covered with ICPLBs anyways.
326          * So there is no difference between kernel and mtd memory setup.
327          */
328
329         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
330         cplb_data[SDRAM_RAM_MTD].valid = 0;
331
332 # endif
333 #else
334         cplb_data[SDRAM_RAM_MTD].valid = 0;
335 #endif
336
337         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
338         cplb_data[SDRAM_DMAZ].end = _ramend;
339
340         cplb_data[RES_MEM].start = _ramend;
341         cplb_data[RES_MEM].end = physical_mem_end;
342
343         if (reserved_mem_dcache_on)
344                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
345         else
346                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
347
348         if (reserved_mem_icache_on)
349                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
350         else
351                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
352
353         for (i = ZERO_P; i <= L2_MEM; i++) {
354                 if (!cplb_data[i].valid)
355                         continue;
356
357                 as_1m = cplb_data[i].start % SIZE_1M;
358
359                 /* We need to make sure all sections are properly 1M aligned
360                  * However between Kernel Memory and the Kernel mtd section, depending on the
361                  * rootfs size, there can be overlapping memory areas.
362                  */
363
364                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
365 #ifdef CONFIG_MTD_UCLINUX
366                         if (i == SDRAM_RAM_MTD) {
367                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
368                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
369                                 else
370                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
371                         } else
372 #endif
373                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
374                                        cplb_data[i].name, cplb_data[i].start);
375                 }
376
377                 as = cplb_data[i].start % SIZE_4M;
378                 ae = cplb_data[i].end % SIZE_4M;
379
380                 if (as)
381                         a_start = cplb_data[i].start + (SIZE_4M - (as));
382                 else
383                         a_start = cplb_data[i].start;
384
385                 a_end = cplb_data[i].end - ae;
386
387                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
388
389                         switch (j) {
390                         case INITIAL_T:
391                                 if (cplb_data[i].attr & INITIAL_T) {
392                                         t_i = &cplb.init_i;
393                                         t_d = &cplb.init_d;
394                                         process = 1;
395                                 } else
396                                         process = 0;
397                                 break;
398                         case SWITCH_T:
399                                 if (cplb_data[i].attr & SWITCH_T) {
400                                         t_i = &cplb.switch_i;
401                                         t_d = &cplb.switch_d;
402                                         process = 1;
403                                 } else
404                                         process = 0;
405                                 break;
406                         default:
407                                         process = 0;
408                                 break;
409                         }
410
411                         if (!process)
412                                 continue;
413                         if (cplb_data[i].attr & I_CPLB)
414                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
415
416                         if (cplb_data[i].attr & D_CPLB)
417                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
418                 }
419         }
420
421 /* close tables */
422
423         close_cplbtab(&cplb.init_i);
424         close_cplbtab(&cplb.init_d);
425
426         cplb.init_i.tab[cplb.init_i.pos] = -1;
427         cplb.init_d.tab[cplb.init_d.pos] = -1;
428         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
429         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
430
431 }
432
433 #endif
434