gpio: sysfs interface
[linux-2.6.git] / arch / avr32 / mach-at32ap / at32ap700x.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/spi/spi.h>
16 #include <linux/usb/atmel_usba_udc.h>
17
18 #include <asm/atmel-mci.h>
19 #include <asm/io.h>
20 #include <asm/irq.h>
21
22 #include <asm/arch/at32ap700x.h>
23 #include <asm/arch/board.h>
24 #include <asm/arch/portmux.h>
25 #include <asm/arch/sram.h>
26
27 #include <video/atmel_lcdc.h>
28
29 #include "clock.h"
30 #include "hmatrix.h"
31 #include "pio.h"
32 #include "pm.h"
33
34
35 #define PBMEM(base)                                     \
36         {                                               \
37                 .start          = base,                 \
38                 .end            = base + 0x3ff,         \
39                 .flags          = IORESOURCE_MEM,       \
40         }
41 #define IRQ(num)                                        \
42         {                                               \
43                 .start          = num,                  \
44                 .end            = num,                  \
45                 .flags          = IORESOURCE_IRQ,       \
46         }
47 #define NAMED_IRQ(num, _name)                           \
48         {                                               \
49                 .start          = num,                  \
50                 .end            = num,                  \
51                 .name           = _name,                \
52                 .flags          = IORESOURCE_IRQ,       \
53         }
54
55 /* REVISIT these assume *every* device supports DMA, but several
56  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
57  */
58 #define DEFINE_DEV(_name, _id)                                  \
59 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
60 static struct platform_device _name##_id##_device = {           \
61         .name           = #_name,                               \
62         .id             = _id,                                  \
63         .dev            = {                                     \
64                 .dma_mask = &_name##_id##_dma_mask,             \
65                 .coherent_dma_mask = DMA_32BIT_MASK,            \
66         },                                                      \
67         .resource       = _name##_id##_resource,                \
68         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
69 }
70 #define DEFINE_DEV_DATA(_name, _id)                             \
71 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
72 static struct platform_device _name##_id##_device = {           \
73         .name           = #_name,                               \
74         .id             = _id,                                  \
75         .dev            = {                                     \
76                 .dma_mask = &_name##_id##_dma_mask,             \
77                 .platform_data  = &_name##_id##_data,           \
78                 .coherent_dma_mask = DMA_32BIT_MASK,            \
79         },                                                      \
80         .resource       = _name##_id##_resource,                \
81         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
82 }
83
84 #define select_peripheral(pin, periph, flags)                   \
85         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
86
87 #define DEV_CLK(_name, devname, bus, _index)                    \
88 static struct clk devname##_##_name = {                         \
89         .name           = #_name,                               \
90         .dev            = &devname##_device.dev,                \
91         .parent         = &bus##_clk,                           \
92         .mode           = bus##_clk_mode,                       \
93         .get_rate       = bus##_clk_get_rate,                   \
94         .index          = _index,                               \
95 }
96
97 static DEFINE_SPINLOCK(pm_lock);
98
99 static struct clk osc0;
100 static struct clk osc1;
101
102 static unsigned long osc_get_rate(struct clk *clk)
103 {
104         return at32_board_osc_rates[clk->index];
105 }
106
107 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
108 {
109         unsigned long div, mul, rate;
110
111         div = PM_BFEXT(PLLDIV, control) + 1;
112         mul = PM_BFEXT(PLLMUL, control) + 1;
113
114         rate = clk->parent->get_rate(clk->parent);
115         rate = (rate + div / 2) / div;
116         rate *= mul;
117
118         return rate;
119 }
120
121 static long pll_set_rate(struct clk *clk, unsigned long rate,
122                          u32 *pll_ctrl)
123 {
124         unsigned long mul;
125         unsigned long mul_best_fit = 0;
126         unsigned long div;
127         unsigned long div_min;
128         unsigned long div_max;
129         unsigned long div_best_fit = 0;
130         unsigned long base;
131         unsigned long pll_in;
132         unsigned long actual = 0;
133         unsigned long rate_error;
134         unsigned long rate_error_prev = ~0UL;
135         u32 ctrl;
136
137         /* Rate must be between 80 MHz and 200 Mhz. */
138         if (rate < 80000000UL || rate > 200000000UL)
139                 return -EINVAL;
140
141         ctrl = PM_BF(PLLOPT, 4);
142         base = clk->parent->get_rate(clk->parent);
143
144         /* PLL input frequency must be between 6 MHz and 32 MHz. */
145         div_min = DIV_ROUND_UP(base, 32000000UL);
146         div_max = base / 6000000UL;
147
148         if (div_max < div_min)
149                 return -EINVAL;
150
151         for (div = div_min; div <= div_max; div++) {
152                 pll_in = (base + div / 2) / div;
153                 mul = (rate + pll_in / 2) / pll_in;
154
155                 if (mul == 0)
156                         continue;
157
158                 actual = pll_in * mul;
159                 rate_error = abs(actual - rate);
160
161                 if (rate_error < rate_error_prev) {
162                         mul_best_fit = mul;
163                         div_best_fit = div;
164                         rate_error_prev = rate_error;
165                 }
166
167                 if (rate_error == 0)
168                         break;
169         }
170
171         if (div_best_fit == 0)
172                 return -EINVAL;
173
174         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
175         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
176         ctrl |= PM_BF(PLLCOUNT, 16);
177
178         if (clk->parent == &osc1)
179                 ctrl |= PM_BIT(PLLOSC);
180
181         *pll_ctrl = ctrl;
182
183         return actual;
184 }
185
186 static unsigned long pll0_get_rate(struct clk *clk)
187 {
188         u32 control;
189
190         control = pm_readl(PLL0);
191
192         return pll_get_rate(clk, control);
193 }
194
195 static void pll1_mode(struct clk *clk, int enabled)
196 {
197         unsigned long timeout;
198         u32 status;
199         u32 ctrl;
200
201         ctrl = pm_readl(PLL1);
202
203         if (enabled) {
204                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
205                         pr_debug("clk %s: failed to enable, rate not set\n",
206                                         clk->name);
207                         return;
208                 }
209
210                 ctrl |= PM_BIT(PLLEN);
211                 pm_writel(PLL1, ctrl);
212
213                 /* Wait for PLL lock. */
214                 for (timeout = 10000; timeout; timeout--) {
215                         status = pm_readl(ISR);
216                         if (status & PM_BIT(LOCK1))
217                                 break;
218                         udelay(10);
219                 }
220
221                 if (!(status & PM_BIT(LOCK1)))
222                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
223                                         clk->name);
224         } else {
225                 ctrl &= ~PM_BIT(PLLEN);
226                 pm_writel(PLL1, ctrl);
227         }
228 }
229
230 static unsigned long pll1_get_rate(struct clk *clk)
231 {
232         u32 control;
233
234         control = pm_readl(PLL1);
235
236         return pll_get_rate(clk, control);
237 }
238
239 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
240 {
241         u32 ctrl = 0;
242         unsigned long actual_rate;
243
244         actual_rate = pll_set_rate(clk, rate, &ctrl);
245
246         if (apply) {
247                 if (actual_rate != rate)
248                         return -EINVAL;
249                 if (clk->users > 0)
250                         return -EBUSY;
251                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
252                                 clk->name, rate, actual_rate);
253                 pm_writel(PLL1, ctrl);
254         }
255
256         return actual_rate;
257 }
258
259 static int pll1_set_parent(struct clk *clk, struct clk *parent)
260 {
261         u32 ctrl;
262
263         if (clk->users > 0)
264                 return -EBUSY;
265
266         ctrl = pm_readl(PLL1);
267         WARN_ON(ctrl & PM_BIT(PLLEN));
268
269         if (parent == &osc0)
270                 ctrl &= ~PM_BIT(PLLOSC);
271         else if (parent == &osc1)
272                 ctrl |= PM_BIT(PLLOSC);
273         else
274                 return -EINVAL;
275
276         pm_writel(PLL1, ctrl);
277         clk->parent = parent;
278
279         return 0;
280 }
281
282 /*
283  * The AT32AP7000 has five primary clock sources: One 32kHz
284  * oscillator, two crystal oscillators and two PLLs.
285  */
286 static struct clk osc32k = {
287         .name           = "osc32k",
288         .get_rate       = osc_get_rate,
289         .users          = 1,
290         .index          = 0,
291 };
292 static struct clk osc0 = {
293         .name           = "osc0",
294         .get_rate       = osc_get_rate,
295         .users          = 1,
296         .index          = 1,
297 };
298 static struct clk osc1 = {
299         .name           = "osc1",
300         .get_rate       = osc_get_rate,
301         .index          = 2,
302 };
303 static struct clk pll0 = {
304         .name           = "pll0",
305         .get_rate       = pll0_get_rate,
306         .parent         = &osc0,
307 };
308 static struct clk pll1 = {
309         .name           = "pll1",
310         .mode           = pll1_mode,
311         .get_rate       = pll1_get_rate,
312         .set_rate       = pll1_set_rate,
313         .set_parent     = pll1_set_parent,
314         .parent         = &osc0,
315 };
316
317 /*
318  * The main clock can be either osc0 or pll0.  The boot loader may
319  * have chosen one for us, so we don't really know which one until we
320  * have a look at the SM.
321  */
322 static struct clk *main_clock;
323
324 /*
325  * Synchronous clocks are generated from the main clock. The clocks
326  * must satisfy the constraint
327  *   fCPU >= fHSB >= fPB
328  * i.e. each clock must not be faster than its parent.
329  */
330 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
331 {
332         return main_clock->get_rate(main_clock) >> shift;
333 };
334
335 static void cpu_clk_mode(struct clk *clk, int enabled)
336 {
337         unsigned long flags;
338         u32 mask;
339
340         spin_lock_irqsave(&pm_lock, flags);
341         mask = pm_readl(CPU_MASK);
342         if (enabled)
343                 mask |= 1 << clk->index;
344         else
345                 mask &= ~(1 << clk->index);
346         pm_writel(CPU_MASK, mask);
347         spin_unlock_irqrestore(&pm_lock, flags);
348 }
349
350 static unsigned long cpu_clk_get_rate(struct clk *clk)
351 {
352         unsigned long cksel, shift = 0;
353
354         cksel = pm_readl(CKSEL);
355         if (cksel & PM_BIT(CPUDIV))
356                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
357
358         return bus_clk_get_rate(clk, shift);
359 }
360
361 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
362 {
363         u32 control;
364         unsigned long parent_rate, child_div, actual_rate, div;
365
366         parent_rate = clk->parent->get_rate(clk->parent);
367         control = pm_readl(CKSEL);
368
369         if (control & PM_BIT(HSBDIV))
370                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
371         else
372                 child_div = 1;
373
374         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
375                 actual_rate = parent_rate;
376                 control &= ~PM_BIT(CPUDIV);
377         } else {
378                 unsigned int cpusel;
379                 div = (parent_rate + rate / 2) / rate;
380                 if (div > child_div)
381                         div = child_div;
382                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
383                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
384                 actual_rate = parent_rate / (1 << (cpusel + 1));
385         }
386
387         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
388                         clk->name, rate, actual_rate);
389
390         if (apply)
391                 pm_writel(CKSEL, control);
392
393         return actual_rate;
394 }
395
396 static void hsb_clk_mode(struct clk *clk, int enabled)
397 {
398         unsigned long flags;
399         u32 mask;
400
401         spin_lock_irqsave(&pm_lock, flags);
402         mask = pm_readl(HSB_MASK);
403         if (enabled)
404                 mask |= 1 << clk->index;
405         else
406                 mask &= ~(1 << clk->index);
407         pm_writel(HSB_MASK, mask);
408         spin_unlock_irqrestore(&pm_lock, flags);
409 }
410
411 static unsigned long hsb_clk_get_rate(struct clk *clk)
412 {
413         unsigned long cksel, shift = 0;
414
415         cksel = pm_readl(CKSEL);
416         if (cksel & PM_BIT(HSBDIV))
417                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
418
419         return bus_clk_get_rate(clk, shift);
420 }
421
422 static void pba_clk_mode(struct clk *clk, int enabled)
423 {
424         unsigned long flags;
425         u32 mask;
426
427         spin_lock_irqsave(&pm_lock, flags);
428         mask = pm_readl(PBA_MASK);
429         if (enabled)
430                 mask |= 1 << clk->index;
431         else
432                 mask &= ~(1 << clk->index);
433         pm_writel(PBA_MASK, mask);
434         spin_unlock_irqrestore(&pm_lock, flags);
435 }
436
437 static unsigned long pba_clk_get_rate(struct clk *clk)
438 {
439         unsigned long cksel, shift = 0;
440
441         cksel = pm_readl(CKSEL);
442         if (cksel & PM_BIT(PBADIV))
443                 shift = PM_BFEXT(PBASEL, cksel) + 1;
444
445         return bus_clk_get_rate(clk, shift);
446 }
447
448 static void pbb_clk_mode(struct clk *clk, int enabled)
449 {
450         unsigned long flags;
451         u32 mask;
452
453         spin_lock_irqsave(&pm_lock, flags);
454         mask = pm_readl(PBB_MASK);
455         if (enabled)
456                 mask |= 1 << clk->index;
457         else
458                 mask &= ~(1 << clk->index);
459         pm_writel(PBB_MASK, mask);
460         spin_unlock_irqrestore(&pm_lock, flags);
461 }
462
463 static unsigned long pbb_clk_get_rate(struct clk *clk)
464 {
465         unsigned long cksel, shift = 0;
466
467         cksel = pm_readl(CKSEL);
468         if (cksel & PM_BIT(PBBDIV))
469                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
470
471         return bus_clk_get_rate(clk, shift);
472 }
473
474 static struct clk cpu_clk = {
475         .name           = "cpu",
476         .get_rate       = cpu_clk_get_rate,
477         .set_rate       = cpu_clk_set_rate,
478         .users          = 1,
479 };
480 static struct clk hsb_clk = {
481         .name           = "hsb",
482         .parent         = &cpu_clk,
483         .get_rate       = hsb_clk_get_rate,
484 };
485 static struct clk pba_clk = {
486         .name           = "pba",
487         .parent         = &hsb_clk,
488         .mode           = hsb_clk_mode,
489         .get_rate       = pba_clk_get_rate,
490         .index          = 1,
491 };
492 static struct clk pbb_clk = {
493         .name           = "pbb",
494         .parent         = &hsb_clk,
495         .mode           = hsb_clk_mode,
496         .get_rate       = pbb_clk_get_rate,
497         .users          = 1,
498         .index          = 2,
499 };
500
501 /* --------------------------------------------------------------------
502  *  Generic Clock operations
503  * -------------------------------------------------------------------- */
504
505 static void genclk_mode(struct clk *clk, int enabled)
506 {
507         u32 control;
508
509         control = pm_readl(GCCTRL(clk->index));
510         if (enabled)
511                 control |= PM_BIT(CEN);
512         else
513                 control &= ~PM_BIT(CEN);
514         pm_writel(GCCTRL(clk->index), control);
515 }
516
517 static unsigned long genclk_get_rate(struct clk *clk)
518 {
519         u32 control;
520         unsigned long div = 1;
521
522         control = pm_readl(GCCTRL(clk->index));
523         if (control & PM_BIT(DIVEN))
524                 div = 2 * (PM_BFEXT(DIV, control) + 1);
525
526         return clk->parent->get_rate(clk->parent) / div;
527 }
528
529 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
530 {
531         u32 control;
532         unsigned long parent_rate, actual_rate, div;
533
534         parent_rate = clk->parent->get_rate(clk->parent);
535         control = pm_readl(GCCTRL(clk->index));
536
537         if (rate > 3 * parent_rate / 4) {
538                 actual_rate = parent_rate;
539                 control &= ~PM_BIT(DIVEN);
540         } else {
541                 div = (parent_rate + rate) / (2 * rate) - 1;
542                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
543                 actual_rate = parent_rate / (2 * (div + 1));
544         }
545
546         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
547                 clk->name, rate, actual_rate);
548
549         if (apply)
550                 pm_writel(GCCTRL(clk->index), control);
551
552         return actual_rate;
553 }
554
555 int genclk_set_parent(struct clk *clk, struct clk *parent)
556 {
557         u32 control;
558
559         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
560                 clk->name, parent->name, clk->parent->name);
561
562         control = pm_readl(GCCTRL(clk->index));
563
564         if (parent == &osc1 || parent == &pll1)
565                 control |= PM_BIT(OSCSEL);
566         else if (parent == &osc0 || parent == &pll0)
567                 control &= ~PM_BIT(OSCSEL);
568         else
569                 return -EINVAL;
570
571         if (parent == &pll0 || parent == &pll1)
572                 control |= PM_BIT(PLLSEL);
573         else
574                 control &= ~PM_BIT(PLLSEL);
575
576         pm_writel(GCCTRL(clk->index), control);
577         clk->parent = parent;
578
579         return 0;
580 }
581
582 static void __init genclk_init_parent(struct clk *clk)
583 {
584         u32 control;
585         struct clk *parent;
586
587         BUG_ON(clk->index > 7);
588
589         control = pm_readl(GCCTRL(clk->index));
590         if (control & PM_BIT(OSCSEL))
591                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
592         else
593                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
594
595         clk->parent = parent;
596 }
597
598 static struct dw_dma_platform_data dw_dmac0_data = {
599         .nr_channels    = 3,
600 };
601
602 static struct resource dw_dmac0_resource[] = {
603         PBMEM(0xff200000),
604         IRQ(2),
605 };
606 DEFINE_DEV_DATA(dw_dmac, 0);
607 DEV_CLK(hclk, dw_dmac0, hsb, 10);
608
609 /* --------------------------------------------------------------------
610  *  System peripherals
611  * -------------------------------------------------------------------- */
612 static struct resource at32_pm0_resource[] = {
613         {
614                 .start  = 0xfff00000,
615                 .end    = 0xfff0007f,
616                 .flags  = IORESOURCE_MEM,
617         },
618         IRQ(20),
619 };
620
621 static struct resource at32ap700x_rtc0_resource[] = {
622         {
623                 .start  = 0xfff00080,
624                 .end    = 0xfff000af,
625                 .flags  = IORESOURCE_MEM,
626         },
627         IRQ(21),
628 };
629
630 static struct resource at32_wdt0_resource[] = {
631         {
632                 .start  = 0xfff000b0,
633                 .end    = 0xfff000cf,
634                 .flags  = IORESOURCE_MEM,
635         },
636 };
637
638 static struct resource at32_eic0_resource[] = {
639         {
640                 .start  = 0xfff00100,
641                 .end    = 0xfff0013f,
642                 .flags  = IORESOURCE_MEM,
643         },
644         IRQ(19),
645 };
646
647 DEFINE_DEV(at32_pm, 0);
648 DEFINE_DEV(at32ap700x_rtc, 0);
649 DEFINE_DEV(at32_wdt, 0);
650 DEFINE_DEV(at32_eic, 0);
651
652 /*
653  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
654  * is always running.
655  */
656 static struct clk at32_pm_pclk = {
657         .name           = "pclk",
658         .dev            = &at32_pm0_device.dev,
659         .parent         = &pbb_clk,
660         .mode           = pbb_clk_mode,
661         .get_rate       = pbb_clk_get_rate,
662         .users          = 1,
663         .index          = 0,
664 };
665
666 static struct resource intc0_resource[] = {
667         PBMEM(0xfff00400),
668 };
669 struct platform_device at32_intc0_device = {
670         .name           = "intc",
671         .id             = 0,
672         .resource       = intc0_resource,
673         .num_resources  = ARRAY_SIZE(intc0_resource),
674 };
675 DEV_CLK(pclk, at32_intc0, pbb, 1);
676
677 static struct clk ebi_clk = {
678         .name           = "ebi",
679         .parent         = &hsb_clk,
680         .mode           = hsb_clk_mode,
681         .get_rate       = hsb_clk_get_rate,
682         .users          = 1,
683 };
684 static struct clk hramc_clk = {
685         .name           = "hramc",
686         .parent         = &hsb_clk,
687         .mode           = hsb_clk_mode,
688         .get_rate       = hsb_clk_get_rate,
689         .users          = 1,
690         .index          = 3,
691 };
692 static struct clk sdramc_clk = {
693         .name           = "sdramc_clk",
694         .parent         = &pbb_clk,
695         .mode           = pbb_clk_mode,
696         .get_rate       = pbb_clk_get_rate,
697         .users          = 1,
698         .index          = 14,
699 };
700
701 static struct resource smc0_resource[] = {
702         PBMEM(0xfff03400),
703 };
704 DEFINE_DEV(smc, 0);
705 DEV_CLK(pclk, smc0, pbb, 13);
706 DEV_CLK(mck, smc0, hsb, 0);
707
708 static struct platform_device pdc_device = {
709         .name           = "pdc",
710         .id             = 0,
711 };
712 DEV_CLK(hclk, pdc, hsb, 4);
713 DEV_CLK(pclk, pdc, pba, 16);
714
715 static struct clk pico_clk = {
716         .name           = "pico",
717         .parent         = &cpu_clk,
718         .mode           = cpu_clk_mode,
719         .get_rate       = cpu_clk_get_rate,
720         .users          = 1,
721 };
722
723 /* --------------------------------------------------------------------
724  * HMATRIX
725  * -------------------------------------------------------------------- */
726
727 static struct clk hmatrix_clk = {
728         .name           = "hmatrix_clk",
729         .parent         = &pbb_clk,
730         .mode           = pbb_clk_mode,
731         .get_rate       = pbb_clk_get_rate,
732         .index          = 2,
733         .users          = 1,
734 };
735 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
736
737 #define hmatrix_readl(reg)                                      \
738         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
739 #define hmatrix_writel(reg,value)                               \
740         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
741
742 /*
743  * Set bits in the HMATRIX Special Function Register (SFR) used by the
744  * External Bus Interface (EBI). This can be used to enable special
745  * features like CompactFlash support, NAND Flash support, etc. on
746  * certain chipselects.
747  */
748 static inline void set_ebi_sfr_bits(u32 mask)
749 {
750         u32 sfr;
751
752         clk_enable(&hmatrix_clk);
753         sfr = hmatrix_readl(SFR4);
754         sfr |= mask;
755         hmatrix_writel(SFR4, sfr);
756         clk_disable(&hmatrix_clk);
757 }
758
759 /* --------------------------------------------------------------------
760  *  Timer/Counter (TC)
761  * -------------------------------------------------------------------- */
762
763 static struct resource at32_tcb0_resource[] = {
764         PBMEM(0xfff00c00),
765         IRQ(22),
766 };
767 static struct platform_device at32_tcb0_device = {
768         .name           = "atmel_tcb",
769         .id             = 0,
770         .resource       = at32_tcb0_resource,
771         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
772 };
773 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
774
775 static struct resource at32_tcb1_resource[] = {
776         PBMEM(0xfff01000),
777         IRQ(23),
778 };
779 static struct platform_device at32_tcb1_device = {
780         .name           = "atmel_tcb",
781         .id             = 1,
782         .resource       = at32_tcb1_resource,
783         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
784 };
785 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
786
787 /* --------------------------------------------------------------------
788  *  PIO
789  * -------------------------------------------------------------------- */
790
791 static struct resource pio0_resource[] = {
792         PBMEM(0xffe02800),
793         IRQ(13),
794 };
795 DEFINE_DEV(pio, 0);
796 DEV_CLK(mck, pio0, pba, 10);
797
798 static struct resource pio1_resource[] = {
799         PBMEM(0xffe02c00),
800         IRQ(14),
801 };
802 DEFINE_DEV(pio, 1);
803 DEV_CLK(mck, pio1, pba, 11);
804
805 static struct resource pio2_resource[] = {
806         PBMEM(0xffe03000),
807         IRQ(15),
808 };
809 DEFINE_DEV(pio, 2);
810 DEV_CLK(mck, pio2, pba, 12);
811
812 static struct resource pio3_resource[] = {
813         PBMEM(0xffe03400),
814         IRQ(16),
815 };
816 DEFINE_DEV(pio, 3);
817 DEV_CLK(mck, pio3, pba, 13);
818
819 static struct resource pio4_resource[] = {
820         PBMEM(0xffe03800),
821         IRQ(17),
822 };
823 DEFINE_DEV(pio, 4);
824 DEV_CLK(mck, pio4, pba, 14);
825
826 void __init at32_add_system_devices(void)
827 {
828         platform_device_register(&at32_pm0_device);
829         platform_device_register(&at32_intc0_device);
830         platform_device_register(&at32ap700x_rtc0_device);
831         platform_device_register(&at32_wdt0_device);
832         platform_device_register(&at32_eic0_device);
833         platform_device_register(&smc0_device);
834         platform_device_register(&pdc_device);
835         platform_device_register(&dw_dmac0_device);
836
837         platform_device_register(&at32_tcb0_device);
838         platform_device_register(&at32_tcb1_device);
839
840         platform_device_register(&pio0_device);
841         platform_device_register(&pio1_device);
842         platform_device_register(&pio2_device);
843         platform_device_register(&pio3_device);
844         platform_device_register(&pio4_device);
845 }
846
847 /* --------------------------------------------------------------------
848  *  PSIF
849  * -------------------------------------------------------------------- */
850 static struct resource atmel_psif0_resource[] __initdata = {
851         {
852                 .start  = 0xffe03c00,
853                 .end    = 0xffe03cff,
854                 .flags  = IORESOURCE_MEM,
855         },
856         IRQ(18),
857 };
858 static struct clk atmel_psif0_pclk = {
859         .name           = "pclk",
860         .parent         = &pba_clk,
861         .mode           = pba_clk_mode,
862         .get_rate       = pba_clk_get_rate,
863         .index          = 15,
864 };
865
866 static struct resource atmel_psif1_resource[] __initdata = {
867         {
868                 .start  = 0xffe03d00,
869                 .end    = 0xffe03dff,
870                 .flags  = IORESOURCE_MEM,
871         },
872         IRQ(18),
873 };
874 static struct clk atmel_psif1_pclk = {
875         .name           = "pclk",
876         .parent         = &pba_clk,
877         .mode           = pba_clk_mode,
878         .get_rate       = pba_clk_get_rate,
879         .index          = 15,
880 };
881
882 struct platform_device *__init at32_add_device_psif(unsigned int id)
883 {
884         struct platform_device *pdev;
885
886         if (!(id == 0 || id == 1))
887                 return NULL;
888
889         pdev = platform_device_alloc("atmel_psif", id);
890         if (!pdev)
891                 return NULL;
892
893         switch (id) {
894         case 0:
895                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
896                                         ARRAY_SIZE(atmel_psif0_resource)))
897                         goto err_add_resources;
898                 atmel_psif0_pclk.dev = &pdev->dev;
899                 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
900                 select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
901                 break;
902         case 1:
903                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
904                                         ARRAY_SIZE(atmel_psif1_resource)))
905                         goto err_add_resources;
906                 atmel_psif1_pclk.dev = &pdev->dev;
907                 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
908                 select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
909                 break;
910         default:
911                 return NULL;
912         }
913
914         platform_device_add(pdev);
915         return pdev;
916
917 err_add_resources:
918         platform_device_put(pdev);
919         return NULL;
920 }
921
922 /* --------------------------------------------------------------------
923  *  USART
924  * -------------------------------------------------------------------- */
925
926 static struct atmel_uart_data atmel_usart0_data = {
927         .use_dma_tx     = 1,
928         .use_dma_rx     = 1,
929 };
930 static struct resource atmel_usart0_resource[] = {
931         PBMEM(0xffe00c00),
932         IRQ(6),
933 };
934 DEFINE_DEV_DATA(atmel_usart, 0);
935 DEV_CLK(usart, atmel_usart0, pba, 3);
936
937 static struct atmel_uart_data atmel_usart1_data = {
938         .use_dma_tx     = 1,
939         .use_dma_rx     = 1,
940 };
941 static struct resource atmel_usart1_resource[] = {
942         PBMEM(0xffe01000),
943         IRQ(7),
944 };
945 DEFINE_DEV_DATA(atmel_usart, 1);
946 DEV_CLK(usart, atmel_usart1, pba, 4);
947
948 static struct atmel_uart_data atmel_usart2_data = {
949         .use_dma_tx     = 1,
950         .use_dma_rx     = 1,
951 };
952 static struct resource atmel_usart2_resource[] = {
953         PBMEM(0xffe01400),
954         IRQ(8),
955 };
956 DEFINE_DEV_DATA(atmel_usart, 2);
957 DEV_CLK(usart, atmel_usart2, pba, 5);
958
959 static struct atmel_uart_data atmel_usart3_data = {
960         .use_dma_tx     = 1,
961         .use_dma_rx     = 1,
962 };
963 static struct resource atmel_usart3_resource[] = {
964         PBMEM(0xffe01800),
965         IRQ(9),
966 };
967 DEFINE_DEV_DATA(atmel_usart, 3);
968 DEV_CLK(usart, atmel_usart3, pba, 6);
969
970 static inline void configure_usart0_pins(void)
971 {
972         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
973         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
974 }
975
976 static inline void configure_usart1_pins(void)
977 {
978         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
979         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
980 }
981
982 static inline void configure_usart2_pins(void)
983 {
984         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
985         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
986 }
987
988 static inline void configure_usart3_pins(void)
989 {
990         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
991         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
992 }
993
994 static struct platform_device *__initdata at32_usarts[4];
995
996 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
997 {
998         struct platform_device *pdev;
999
1000         switch (hw_id) {
1001         case 0:
1002                 pdev = &atmel_usart0_device;
1003                 configure_usart0_pins();
1004                 break;
1005         case 1:
1006                 pdev = &atmel_usart1_device;
1007                 configure_usart1_pins();
1008                 break;
1009         case 2:
1010                 pdev = &atmel_usart2_device;
1011                 configure_usart2_pins();
1012                 break;
1013         case 3:
1014                 pdev = &atmel_usart3_device;
1015                 configure_usart3_pins();
1016                 break;
1017         default:
1018                 return;
1019         }
1020
1021         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1022                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1023                 struct atmel_uart_data *data = pdev->dev.platform_data;
1024                 data->regs = (void __iomem *)pdev->resource[0].start;
1025         }
1026
1027         pdev->id = line;
1028         at32_usarts[line] = pdev;
1029 }
1030
1031 struct platform_device *__init at32_add_device_usart(unsigned int id)
1032 {
1033         platform_device_register(at32_usarts[id]);
1034         return at32_usarts[id];
1035 }
1036
1037 struct platform_device *atmel_default_console_device;
1038
1039 void __init at32_setup_serial_console(unsigned int usart_id)
1040 {
1041         atmel_default_console_device = at32_usarts[usart_id];
1042 }
1043
1044 /* --------------------------------------------------------------------
1045  *  Ethernet
1046  * -------------------------------------------------------------------- */
1047
1048 #ifdef CONFIG_CPU_AT32AP7000
1049 static struct eth_platform_data macb0_data;
1050 static struct resource macb0_resource[] = {
1051         PBMEM(0xfff01800),
1052         IRQ(25),
1053 };
1054 DEFINE_DEV_DATA(macb, 0);
1055 DEV_CLK(hclk, macb0, hsb, 8);
1056 DEV_CLK(pclk, macb0, pbb, 6);
1057
1058 static struct eth_platform_data macb1_data;
1059 static struct resource macb1_resource[] = {
1060         PBMEM(0xfff01c00),
1061         IRQ(26),
1062 };
1063 DEFINE_DEV_DATA(macb, 1);
1064 DEV_CLK(hclk, macb1, hsb, 9);
1065 DEV_CLK(pclk, macb1, pbb, 7);
1066
1067 struct platform_device *__init
1068 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1069 {
1070         struct platform_device *pdev;
1071
1072         switch (id) {
1073         case 0:
1074                 pdev = &macb0_device;
1075
1076                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
1077                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
1078                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1079                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1080                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1081                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1082                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1083                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1084                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1085                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1086
1087                 if (!data->is_rmii) {
1088                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1089                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1090                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1091                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1092                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1093                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1094                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1095                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1096                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1097                 }
1098                 break;
1099
1100         case 1:
1101                 pdev = &macb1_device;
1102
1103                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1104                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1105                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1106                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1107                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1108                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1109                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1110                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1111                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1112                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1113
1114                 if (!data->is_rmii) {
1115                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1116                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1117                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1118                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1119                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1120                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1121                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1122                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1123                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1124                 }
1125                 break;
1126
1127         default:
1128                 return NULL;
1129         }
1130
1131         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1132         platform_device_register(pdev);
1133
1134         return pdev;
1135 }
1136 #endif
1137
1138 /* --------------------------------------------------------------------
1139  *  SPI
1140  * -------------------------------------------------------------------- */
1141 static struct resource atmel_spi0_resource[] = {
1142         PBMEM(0xffe00000),
1143         IRQ(3),
1144 };
1145 DEFINE_DEV(atmel_spi, 0);
1146 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1147
1148 static struct resource atmel_spi1_resource[] = {
1149         PBMEM(0xffe00400),
1150         IRQ(4),
1151 };
1152 DEFINE_DEV(atmel_spi, 1);
1153 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1154
1155 static void __init
1156 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1157                       unsigned int n, const u8 *pins)
1158 {
1159         unsigned int pin, mode;
1160
1161         for (; n; n--, b++) {
1162                 b->bus_num = bus_num;
1163                 if (b->chip_select >= 4)
1164                         continue;
1165                 pin = (unsigned)b->controller_data;
1166                 if (!pin) {
1167                         pin = pins[b->chip_select];
1168                         b->controller_data = (void *)pin;
1169                 }
1170                 mode = AT32_GPIOF_OUTPUT;
1171                 if (!(b->mode & SPI_CS_HIGH))
1172                         mode |= AT32_GPIOF_HIGH;
1173                 at32_select_gpio(pin, mode);
1174         }
1175 }
1176
1177 struct platform_device *__init
1178 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1179 {
1180         /*
1181          * Manage the chipselects as GPIOs, normally using the same pins
1182          * the SPI controller expects; but boards can use other pins.
1183          */
1184         static u8 __initdata spi0_pins[] =
1185                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1186                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1187         static u8 __initdata spi1_pins[] =
1188                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1189                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1190         struct platform_device *pdev;
1191
1192         switch (id) {
1193         case 0:
1194                 pdev = &atmel_spi0_device;
1195                 /* pullup MISO so a level is always defined */
1196                 select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
1197                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1198                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1199                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1200                 break;
1201
1202         case 1:
1203                 pdev = &atmel_spi1_device;
1204                 /* pullup MISO so a level is always defined */
1205                 select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
1206                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1207                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1208                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1209                 break;
1210
1211         default:
1212                 return NULL;
1213         }
1214
1215         spi_register_board_info(b, n);
1216         platform_device_register(pdev);
1217         return pdev;
1218 }
1219
1220 /* --------------------------------------------------------------------
1221  *  TWI
1222  * -------------------------------------------------------------------- */
1223 static struct resource atmel_twi0_resource[] __initdata = {
1224         PBMEM(0xffe00800),
1225         IRQ(5),
1226 };
1227 static struct clk atmel_twi0_pclk = {
1228         .name           = "twi_pclk",
1229         .parent         = &pba_clk,
1230         .mode           = pba_clk_mode,
1231         .get_rate       = pba_clk_get_rate,
1232         .index          = 2,
1233 };
1234
1235 struct platform_device *__init at32_add_device_twi(unsigned int id,
1236                                                     struct i2c_board_info *b,
1237                                                     unsigned int n)
1238 {
1239         struct platform_device *pdev;
1240
1241         if (id != 0)
1242                 return NULL;
1243
1244         pdev = platform_device_alloc("atmel_twi", id);
1245         if (!pdev)
1246                 return NULL;
1247
1248         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1249                                 ARRAY_SIZE(atmel_twi0_resource)))
1250                 goto err_add_resources;
1251
1252         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1253         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1254
1255         atmel_twi0_pclk.dev = &pdev->dev;
1256
1257         if (b)
1258                 i2c_register_board_info(id, b, n);
1259
1260         platform_device_add(pdev);
1261         return pdev;
1262
1263 err_add_resources:
1264         platform_device_put(pdev);
1265         return NULL;
1266 }
1267
1268 /* --------------------------------------------------------------------
1269  * MMC
1270  * -------------------------------------------------------------------- */
1271 static struct resource atmel_mci0_resource[] __initdata = {
1272         PBMEM(0xfff02400),
1273         IRQ(28),
1274 };
1275 static struct clk atmel_mci0_pclk = {
1276         .name           = "mci_clk",
1277         .parent         = &pbb_clk,
1278         .mode           = pbb_clk_mode,
1279         .get_rate       = pbb_clk_get_rate,
1280         .index          = 9,
1281 };
1282
1283 struct platform_device *__init
1284 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1285 {
1286         struct mci_platform_data        _data;
1287         struct platform_device          *pdev;
1288         struct dw_dma_slave             *dws;
1289
1290         if (id != 0)
1291                 return NULL;
1292
1293         pdev = platform_device_alloc("atmel_mci", id);
1294         if (!pdev)
1295                 goto fail;
1296
1297         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1298                                 ARRAY_SIZE(atmel_mci0_resource)))
1299                 goto fail;
1300
1301         if (!data) {
1302                 data = &_data;
1303                 memset(data, 0, sizeof(struct mci_platform_data));
1304         }
1305
1306         if (platform_device_add_data(pdev, data,
1307                                 sizeof(struct mci_platform_data)))
1308                 goto fail;
1309
1310         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1311         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1312         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1313         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1314         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1315         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1316
1317         if (data) {
1318                 if (data->detect_pin != GPIO_PIN_NONE)
1319                         at32_select_gpio(data->detect_pin, 0);
1320                 if (data->wp_pin != GPIO_PIN_NONE)
1321                         at32_select_gpio(data->wp_pin, 0);
1322         }
1323
1324         atmel_mci0_pclk.dev = &pdev->dev;
1325
1326         platform_device_add(pdev);
1327         return pdev;
1328
1329 fail:
1330         platform_device_put(pdev);
1331         return NULL;
1332 }
1333
1334 /* --------------------------------------------------------------------
1335  *  LCDC
1336  * -------------------------------------------------------------------- */
1337 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1338 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1339 static struct resource atmel_lcdfb0_resource[] = {
1340         {
1341                 .start          = 0xff000000,
1342                 .end            = 0xff000fff,
1343                 .flags          = IORESOURCE_MEM,
1344         },
1345         IRQ(1),
1346         {
1347                 /* Placeholder for pre-allocated fb memory */
1348                 .start          = 0x00000000,
1349                 .end            = 0x00000000,
1350                 .flags          = 0,
1351         },
1352 };
1353 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1354 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1355 static struct clk atmel_lcdfb0_pixclk = {
1356         .name           = "lcdc_clk",
1357         .dev            = &atmel_lcdfb0_device.dev,
1358         .mode           = genclk_mode,
1359         .get_rate       = genclk_get_rate,
1360         .set_rate       = genclk_set_rate,
1361         .set_parent     = genclk_set_parent,
1362         .index          = 7,
1363 };
1364
1365 struct platform_device *__init
1366 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1367                      unsigned long fbmem_start, unsigned long fbmem_len,
1368                      unsigned int pin_config)
1369 {
1370         struct platform_device *pdev;
1371         struct atmel_lcdfb_info *info;
1372         struct fb_monspecs *monspecs;
1373         struct fb_videomode *modedb;
1374         unsigned int modedb_size;
1375
1376         /*
1377          * Do a deep copy of the fb data, monspecs and modedb. Make
1378          * sure all allocations are done before setting up the
1379          * portmux.
1380          */
1381         monspecs = kmemdup(data->default_monspecs,
1382                            sizeof(struct fb_monspecs), GFP_KERNEL);
1383         if (!monspecs)
1384                 return NULL;
1385
1386         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1387         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1388         if (!modedb)
1389                 goto err_dup_modedb;
1390         monspecs->modedb = modedb;
1391
1392         switch (id) {
1393         case 0:
1394                 pdev = &atmel_lcdfb0_device;
1395
1396                 switch (pin_config) {
1397                 case 0:
1398                         select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1399                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1400                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1401                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1402                         select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1403                         select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1404                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1405                         select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1406                         select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1407                         select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1408                         select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1409                         select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1410                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1411                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1412                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1413                         select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1414                         select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1415                         select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1416                         select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1417                         select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1418                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1419                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1420                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1421                         select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1422                         select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1423                         select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1424                         select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1425                         select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1426                         select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1427                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1428                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1429                         break;
1430                 case 1:
1431                         select_peripheral(PE(0),  PERIPH_B, 0); /* CC     */
1432                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1433                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1434                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1435                         select_peripheral(PE(1),  PERIPH_B, 0); /* DVAL   */
1436                         select_peripheral(PE(2),  PERIPH_B, 0); /* MODE   */
1437                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1438                         select_peripheral(PE(3),  PERIPH_B, 0); /* DATA0  */
1439                         select_peripheral(PE(4),  PERIPH_B, 0); /* DATA1  */
1440                         select_peripheral(PE(5),  PERIPH_B, 0); /* DATA2  */
1441                         select_peripheral(PE(6),  PERIPH_B, 0); /* DATA3  */
1442                         select_peripheral(PE(7),  PERIPH_B, 0); /* DATA4  */
1443                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1444                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1445                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1446                         select_peripheral(PE(8),  PERIPH_B, 0); /* DATA8  */
1447                         select_peripheral(PE(9),  PERIPH_B, 0); /* DATA9  */
1448                         select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1449                         select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1450                         select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1451                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1452                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1453                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1454                         select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1455                         select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1456                         select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1457                         select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1458                         select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1459                         select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1460                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1461                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1462                         break;
1463                 default:
1464                         goto err_invalid_id;
1465                 }
1466
1467                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1468                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1469                 break;
1470
1471         default:
1472                 goto err_invalid_id;
1473         }
1474
1475         if (fbmem_len) {
1476                 pdev->resource[2].start = fbmem_start;
1477                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1478                 pdev->resource[2].flags = IORESOURCE_MEM;
1479         }
1480
1481         info = pdev->dev.platform_data;
1482         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1483         info->default_monspecs = monspecs;
1484
1485         platform_device_register(pdev);
1486         return pdev;
1487
1488 err_invalid_id:
1489         kfree(modedb);
1490 err_dup_modedb:
1491         kfree(monspecs);
1492         return NULL;
1493 }
1494 #endif
1495
1496 /* --------------------------------------------------------------------
1497  *  PWM
1498  * -------------------------------------------------------------------- */
1499 static struct resource atmel_pwm0_resource[] __initdata = {
1500         PBMEM(0xfff01400),
1501         IRQ(24),
1502 };
1503 static struct clk atmel_pwm0_mck = {
1504         .name           = "pwm_clk",
1505         .parent         = &pbb_clk,
1506         .mode           = pbb_clk_mode,
1507         .get_rate       = pbb_clk_get_rate,
1508         .index          = 5,
1509 };
1510
1511 struct platform_device *__init at32_add_device_pwm(u32 mask)
1512 {
1513         struct platform_device *pdev;
1514
1515         if (!mask)
1516                 return NULL;
1517
1518         pdev = platform_device_alloc("atmel_pwm", 0);
1519         if (!pdev)
1520                 return NULL;
1521
1522         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1523                                 ARRAY_SIZE(atmel_pwm0_resource)))
1524                 goto out_free_pdev;
1525
1526         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1527                 goto out_free_pdev;
1528
1529         if (mask & (1 << 0))
1530                 select_peripheral(PA(28), PERIPH_A, 0);
1531         if (mask & (1 << 1))
1532                 select_peripheral(PA(29), PERIPH_A, 0);
1533         if (mask & (1 << 2))
1534                 select_peripheral(PA(21), PERIPH_B, 0);
1535         if (mask & (1 << 3))
1536                 select_peripheral(PA(22), PERIPH_B, 0);
1537
1538         atmel_pwm0_mck.dev = &pdev->dev;
1539
1540         platform_device_add(pdev);
1541
1542         return pdev;
1543
1544 out_free_pdev:
1545         platform_device_put(pdev);
1546         return NULL;
1547 }
1548
1549 /* --------------------------------------------------------------------
1550  *  SSC
1551  * -------------------------------------------------------------------- */
1552 static struct resource ssc0_resource[] = {
1553         PBMEM(0xffe01c00),
1554         IRQ(10),
1555 };
1556 DEFINE_DEV(ssc, 0);
1557 DEV_CLK(pclk, ssc0, pba, 7);
1558
1559 static struct resource ssc1_resource[] = {
1560         PBMEM(0xffe02000),
1561         IRQ(11),
1562 };
1563 DEFINE_DEV(ssc, 1);
1564 DEV_CLK(pclk, ssc1, pba, 8);
1565
1566 static struct resource ssc2_resource[] = {
1567         PBMEM(0xffe02400),
1568         IRQ(12),
1569 };
1570 DEFINE_DEV(ssc, 2);
1571 DEV_CLK(pclk, ssc2, pba, 9);
1572
1573 struct platform_device *__init
1574 at32_add_device_ssc(unsigned int id, unsigned int flags)
1575 {
1576         struct platform_device *pdev;
1577
1578         switch (id) {
1579         case 0:
1580                 pdev = &ssc0_device;
1581                 if (flags & ATMEL_SSC_RF)
1582                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1583                 if (flags & ATMEL_SSC_RK)
1584                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1585                 if (flags & ATMEL_SSC_TK)
1586                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1587                 if (flags & ATMEL_SSC_TF)
1588                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1589                 if (flags & ATMEL_SSC_TD)
1590                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1591                 if (flags & ATMEL_SSC_RD)
1592                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1593                 break;
1594         case 1:
1595                 pdev = &ssc1_device;
1596                 if (flags & ATMEL_SSC_RF)
1597                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1598                 if (flags & ATMEL_SSC_RK)
1599                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1600                 if (flags & ATMEL_SSC_TK)
1601                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1602                 if (flags & ATMEL_SSC_TF)
1603                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1604                 if (flags & ATMEL_SSC_TD)
1605                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1606                 if (flags & ATMEL_SSC_RD)
1607                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1608                 break;
1609         case 2:
1610                 pdev = &ssc2_device;
1611                 if (flags & ATMEL_SSC_TD)
1612                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1613                 if (flags & ATMEL_SSC_RD)
1614                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1615                 if (flags & ATMEL_SSC_TK)
1616                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1617                 if (flags & ATMEL_SSC_TF)
1618                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1619                 if (flags & ATMEL_SSC_RF)
1620                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1621                 if (flags & ATMEL_SSC_RK)
1622                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1623                 break;
1624         default:
1625                 return NULL;
1626         }
1627
1628         platform_device_register(pdev);
1629         return pdev;
1630 }
1631
1632 /* --------------------------------------------------------------------
1633  *  USB Device Controller
1634  * -------------------------------------------------------------------- */
1635 static struct resource usba0_resource[] __initdata = {
1636         {
1637                 .start          = 0xff300000,
1638                 .end            = 0xff3fffff,
1639                 .flags          = IORESOURCE_MEM,
1640         }, {
1641                 .start          = 0xfff03000,
1642                 .end            = 0xfff033ff,
1643                 .flags          = IORESOURCE_MEM,
1644         },
1645         IRQ(31),
1646 };
1647 static struct clk usba0_pclk = {
1648         .name           = "pclk",
1649         .parent         = &pbb_clk,
1650         .mode           = pbb_clk_mode,
1651         .get_rate       = pbb_clk_get_rate,
1652         .index          = 12,
1653 };
1654 static struct clk usba0_hclk = {
1655         .name           = "hclk",
1656         .parent         = &hsb_clk,
1657         .mode           = hsb_clk_mode,
1658         .get_rate       = hsb_clk_get_rate,
1659         .index          = 6,
1660 };
1661
1662 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1663         [idx] = {                                               \
1664                 .name           = nam,                          \
1665                 .index          = idx,                          \
1666                 .fifo_size      = maxpkt,                       \
1667                 .nr_banks       = maxbk,                        \
1668                 .can_dma        = dma,                          \
1669                 .can_isoc       = isoc,                         \
1670         }
1671
1672 static struct usba_ep_data at32_usba_ep[] __initdata = {
1673         EP("ep0",     0,   64, 1, 0, 0),
1674         EP("ep1",     1,  512, 2, 1, 1),
1675         EP("ep2",     2,  512, 2, 1, 1),
1676         EP("ep3-int", 3,   64, 3, 1, 0),
1677         EP("ep4-int", 4,   64, 3, 1, 0),
1678         EP("ep5",     5, 1024, 3, 1, 1),
1679         EP("ep6",     6, 1024, 3, 1, 1),
1680 };
1681
1682 #undef EP
1683
1684 struct platform_device *__init
1685 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1686 {
1687         /*
1688          * pdata doesn't have room for any endpoints, so we need to
1689          * append room for the ones we need right after it.
1690          */
1691         struct {
1692                 struct usba_platform_data pdata;
1693                 struct usba_ep_data ep[7];
1694         } usba_data;
1695         struct platform_device *pdev;
1696
1697         if (id != 0)
1698                 return NULL;
1699
1700         pdev = platform_device_alloc("atmel_usba_udc", 0);
1701         if (!pdev)
1702                 return NULL;
1703
1704         if (platform_device_add_resources(pdev, usba0_resource,
1705                                           ARRAY_SIZE(usba0_resource)))
1706                 goto out_free_pdev;
1707
1708         if (data)
1709                 usba_data.pdata.vbus_pin = data->vbus_pin;
1710         else
1711                 usba_data.pdata.vbus_pin = -EINVAL;
1712
1713         data = &usba_data.pdata;
1714         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1715         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1716
1717         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1718                 goto out_free_pdev;
1719
1720         if (data->vbus_pin >= 0)
1721                 at32_select_gpio(data->vbus_pin, 0);
1722
1723         usba0_pclk.dev = &pdev->dev;
1724         usba0_hclk.dev = &pdev->dev;
1725
1726         platform_device_add(pdev);
1727
1728         return pdev;
1729
1730 out_free_pdev:
1731         platform_device_put(pdev);
1732         return NULL;
1733 }
1734
1735 /* --------------------------------------------------------------------
1736  * IDE / CompactFlash
1737  * -------------------------------------------------------------------- */
1738 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1739 static struct resource at32_smc_cs4_resource[] __initdata = {
1740         {
1741                 .start  = 0x04000000,
1742                 .end    = 0x07ffffff,
1743                 .flags  = IORESOURCE_MEM,
1744         },
1745         IRQ(~0UL), /* Magic IRQ will be overridden */
1746 };
1747 static struct resource at32_smc_cs5_resource[] __initdata = {
1748         {
1749                 .start  = 0x20000000,
1750                 .end    = 0x23ffffff,
1751                 .flags  = IORESOURCE_MEM,
1752         },
1753         IRQ(~0UL), /* Magic IRQ will be overridden */
1754 };
1755
1756 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1757                 unsigned int cs, unsigned int extint)
1758 {
1759         static unsigned int extint_pin_map[4] __initdata = {
1760                 GPIO_PIN_PB(25),
1761                 GPIO_PIN_PB(26),
1762                 GPIO_PIN_PB(27),
1763                 GPIO_PIN_PB(28),
1764         };
1765         static bool common_pins_initialized __initdata = false;
1766         unsigned int extint_pin;
1767         int ret;
1768
1769         if (extint >= ARRAY_SIZE(extint_pin_map))
1770                 return -EINVAL;
1771         extint_pin = extint_pin_map[extint];
1772
1773         switch (cs) {
1774         case 4:
1775                 ret = platform_device_add_resources(pdev,
1776                                 at32_smc_cs4_resource,
1777                                 ARRAY_SIZE(at32_smc_cs4_resource));
1778                 if (ret)
1779                         return ret;
1780
1781                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1782                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1783                 break;
1784         case 5:
1785                 ret = platform_device_add_resources(pdev,
1786                                 at32_smc_cs5_resource,
1787                                 ARRAY_SIZE(at32_smc_cs5_resource));
1788                 if (ret)
1789                         return ret;
1790
1791                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1792                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1793                 break;
1794         default:
1795                 return -EINVAL;
1796         }
1797
1798         if (!common_pins_initialized) {
1799                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1800                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1801                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1802                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1803                 common_pins_initialized = true;
1804         }
1805
1806         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1807
1808         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1809         pdev->resource[1].end = pdev->resource[1].start;
1810
1811         return 0;
1812 }
1813
1814 struct platform_device *__init
1815 at32_add_device_ide(unsigned int id, unsigned int extint,
1816                     struct ide_platform_data *data)
1817 {
1818         struct platform_device *pdev;
1819
1820         pdev = platform_device_alloc("at32_ide", id);
1821         if (!pdev)
1822                 goto fail;
1823
1824         if (platform_device_add_data(pdev, data,
1825                                 sizeof(struct ide_platform_data)))
1826                 goto fail;
1827
1828         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1829                 goto fail;
1830
1831         platform_device_add(pdev);
1832         return pdev;
1833
1834 fail:
1835         platform_device_put(pdev);
1836         return NULL;
1837 }
1838
1839 struct platform_device *__init
1840 at32_add_device_cf(unsigned int id, unsigned int extint,
1841                     struct cf_platform_data *data)
1842 {
1843         struct platform_device *pdev;
1844
1845         pdev = platform_device_alloc("at32_cf", id);
1846         if (!pdev)
1847                 goto fail;
1848
1849         if (platform_device_add_data(pdev, data,
1850                                 sizeof(struct cf_platform_data)))
1851                 goto fail;
1852
1853         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1854                 goto fail;
1855
1856         if (data->detect_pin != GPIO_PIN_NONE)
1857                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1858         if (data->reset_pin != GPIO_PIN_NONE)
1859                 at32_select_gpio(data->reset_pin, 0);
1860         if (data->vcc_pin != GPIO_PIN_NONE)
1861                 at32_select_gpio(data->vcc_pin, 0);
1862         /* READY is used as extint, so we can't select it as gpio */
1863
1864         platform_device_add(pdev);
1865         return pdev;
1866
1867 fail:
1868         platform_device_put(pdev);
1869         return NULL;
1870 }
1871 #endif
1872
1873 /* --------------------------------------------------------------------
1874  * AC97C
1875  * -------------------------------------------------------------------- */
1876 static struct resource atmel_ac97c0_resource[] __initdata = {
1877         PBMEM(0xfff02800),
1878         IRQ(29),
1879 };
1880 static struct clk atmel_ac97c0_pclk = {
1881         .name           = "pclk",
1882         .parent         = &pbb_clk,
1883         .mode           = pbb_clk_mode,
1884         .get_rate       = pbb_clk_get_rate,
1885         .index          = 10,
1886 };
1887
1888 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1889 {
1890         struct platform_device *pdev;
1891
1892         if (id != 0)
1893                 return NULL;
1894
1895         pdev = platform_device_alloc("atmel_ac97c", id);
1896         if (!pdev)
1897                 return NULL;
1898
1899         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1900                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1901                 goto err_add_resources;
1902
1903         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1904         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1905         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1906         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1907
1908         atmel_ac97c0_pclk.dev = &pdev->dev;
1909
1910         platform_device_add(pdev);
1911         return pdev;
1912
1913 err_add_resources:
1914         platform_device_put(pdev);
1915         return NULL;
1916 }
1917
1918 /* --------------------------------------------------------------------
1919  * ABDAC
1920  * -------------------------------------------------------------------- */
1921 static struct resource abdac0_resource[] __initdata = {
1922         PBMEM(0xfff02000),
1923         IRQ(27),
1924 };
1925 static struct clk abdac0_pclk = {
1926         .name           = "pclk",
1927         .parent         = &pbb_clk,
1928         .mode           = pbb_clk_mode,
1929         .get_rate       = pbb_clk_get_rate,
1930         .index          = 8,
1931 };
1932 static struct clk abdac0_sample_clk = {
1933         .name           = "sample_clk",
1934         .mode           = genclk_mode,
1935         .get_rate       = genclk_get_rate,
1936         .set_rate       = genclk_set_rate,
1937         .set_parent     = genclk_set_parent,
1938         .index          = 6,
1939 };
1940
1941 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1942 {
1943         struct platform_device *pdev;
1944
1945         if (id != 0)
1946                 return NULL;
1947
1948         pdev = platform_device_alloc("abdac", id);
1949         if (!pdev)
1950                 return NULL;
1951
1952         if (platform_device_add_resources(pdev, abdac0_resource,
1953                                 ARRAY_SIZE(abdac0_resource)))
1954                 goto err_add_resources;
1955
1956         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1957         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1958         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1959         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1960
1961         abdac0_pclk.dev = &pdev->dev;
1962         abdac0_sample_clk.dev = &pdev->dev;
1963
1964         platform_device_add(pdev);
1965         return pdev;
1966
1967 err_add_resources:
1968         platform_device_put(pdev);
1969         return NULL;
1970 }
1971
1972 /* --------------------------------------------------------------------
1973  *  GCLK
1974  * -------------------------------------------------------------------- */
1975 static struct clk gclk0 = {
1976         .name           = "gclk0",
1977         .mode           = genclk_mode,
1978         .get_rate       = genclk_get_rate,
1979         .set_rate       = genclk_set_rate,
1980         .set_parent     = genclk_set_parent,
1981         .index          = 0,
1982 };
1983 static struct clk gclk1 = {
1984         .name           = "gclk1",
1985         .mode           = genclk_mode,
1986         .get_rate       = genclk_get_rate,
1987         .set_rate       = genclk_set_rate,
1988         .set_parent     = genclk_set_parent,
1989         .index          = 1,
1990 };
1991 static struct clk gclk2 = {
1992         .name           = "gclk2",
1993         .mode           = genclk_mode,
1994         .get_rate       = genclk_get_rate,
1995         .set_rate       = genclk_set_rate,
1996         .set_parent     = genclk_set_parent,
1997         .index          = 2,
1998 };
1999 static struct clk gclk3 = {
2000         .name           = "gclk3",
2001         .mode           = genclk_mode,
2002         .get_rate       = genclk_get_rate,
2003         .set_rate       = genclk_set_rate,
2004         .set_parent     = genclk_set_parent,
2005         .index          = 3,
2006 };
2007 static struct clk gclk4 = {
2008         .name           = "gclk4",
2009         .mode           = genclk_mode,
2010         .get_rate       = genclk_get_rate,
2011         .set_rate       = genclk_set_rate,
2012         .set_parent     = genclk_set_parent,
2013         .index          = 4,
2014 };
2015
2016 struct clk *at32_clock_list[] = {
2017         &osc32k,
2018         &osc0,
2019         &osc1,
2020         &pll0,
2021         &pll1,
2022         &cpu_clk,
2023         &hsb_clk,
2024         &pba_clk,
2025         &pbb_clk,
2026         &at32_pm_pclk,
2027         &at32_intc0_pclk,
2028         &hmatrix_clk,
2029         &ebi_clk,
2030         &hramc_clk,
2031         &sdramc_clk,
2032         &smc0_pclk,
2033         &smc0_mck,
2034         &pdc_hclk,
2035         &pdc_pclk,
2036         &dw_dmac0_hclk,
2037         &pico_clk,
2038         &pio0_mck,
2039         &pio1_mck,
2040         &pio2_mck,
2041         &pio3_mck,
2042         &pio4_mck,
2043         &at32_tcb0_t0_clk,
2044         &at32_tcb1_t0_clk,
2045         &atmel_psif0_pclk,
2046         &atmel_psif1_pclk,
2047         &atmel_usart0_usart,
2048         &atmel_usart1_usart,
2049         &atmel_usart2_usart,
2050         &atmel_usart3_usart,
2051         &atmel_pwm0_mck,
2052 #if defined(CONFIG_CPU_AT32AP7000)
2053         &macb0_hclk,
2054         &macb0_pclk,
2055         &macb1_hclk,
2056         &macb1_pclk,
2057 #endif
2058         &atmel_spi0_spi_clk,
2059         &atmel_spi1_spi_clk,
2060         &atmel_twi0_pclk,
2061         &atmel_mci0_pclk,
2062 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2063         &atmel_lcdfb0_hck1,
2064         &atmel_lcdfb0_pixclk,
2065 #endif
2066         &ssc0_pclk,
2067         &ssc1_pclk,
2068         &ssc2_pclk,
2069         &usba0_hclk,
2070         &usba0_pclk,
2071         &atmel_ac97c0_pclk,
2072         &abdac0_pclk,
2073         &abdac0_sample_clk,
2074         &gclk0,
2075         &gclk1,
2076         &gclk2,
2077         &gclk3,
2078         &gclk4,
2079 };
2080 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2081
2082 void __init setup_platform(void)
2083 {
2084         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2085         int i;
2086
2087         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2088                 main_clock = &pll0;
2089                 cpu_clk.parent = &pll0;
2090         } else {
2091                 main_clock = &osc0;
2092                 cpu_clk.parent = &osc0;
2093         }
2094
2095         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2096                 pll0.parent = &osc1;
2097         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2098                 pll1.parent = &osc1;
2099
2100         genclk_init_parent(&gclk0);
2101         genclk_init_parent(&gclk1);
2102         genclk_init_parent(&gclk2);
2103         genclk_init_parent(&gclk3);
2104         genclk_init_parent(&gclk4);
2105 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2106         genclk_init_parent(&atmel_lcdfb0_pixclk);
2107 #endif
2108         genclk_init_parent(&abdac0_sample_clk);
2109
2110         /*
2111          * Turn on all clocks that have at least one user already, and
2112          * turn off everything else. We only do this for module
2113          * clocks, and even though it isn't particularly pretty to
2114          * check the address of the mode function, it should do the
2115          * trick...
2116          */
2117         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2118                 struct clk *clk = at32_clock_list[i];
2119
2120                 if (clk->users == 0)
2121                         continue;
2122
2123                 if (clk->mode == &cpu_clk_mode)
2124                         cpu_mask |= 1 << clk->index;
2125                 else if (clk->mode == &hsb_clk_mode)
2126                         hsb_mask |= 1 << clk->index;
2127                 else if (clk->mode == &pba_clk_mode)
2128                         pba_mask |= 1 << clk->index;
2129                 else if (clk->mode == &pbb_clk_mode)
2130                         pbb_mask |= 1 << clk->index;
2131         }
2132
2133         pm_writel(CPU_MASK, cpu_mask);
2134         pm_writel(HSB_MASK, hsb_mask);
2135         pm_writel(PBA_MASK, pba_mask);
2136         pm_writel(PBB_MASK, pbb_mask);
2137
2138         /* Initialize the port muxes */
2139         at32_init_pio(&pio0_device);
2140         at32_init_pio(&pio1_device);
2141         at32_init_pio(&pio2_device);
2142         at32_init_pio(&pio3_device);
2143         at32_init_pio(&pio4_device);
2144 }
2145
2146 struct gen_pool *sram_pool;
2147
2148 static int __init sram_init(void)
2149 {
2150         struct gen_pool *pool;
2151
2152         /* 1KiB granularity */
2153         pool = gen_pool_create(10, -1);
2154         if (!pool)
2155                 goto fail;
2156
2157         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2158                 goto err_pool_add;
2159
2160         sram_pool = pool;
2161         return 0;
2162
2163 err_pool_add:
2164         gen_pool_destroy(pool);
2165 fail:
2166         pr_err("Failed to create SRAM pool\n");
2167         return -ENOMEM;
2168 }
2169 core_initcall(sram_init);