Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen...
[linux-2.6.git] / arch / avr32 / mach-at32ap / at32ap700x.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
18
19 #include <asm/atmel-mci.h>
20 #include <asm/io.h>
21 #include <asm/irq.h>
22
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
28
29 #include <video/atmel_lcdc.h>
30
31 #include "clock.h"
32 #include "pio.h"
33 #include "pm.h"
34
35
36 #define PBMEM(base)                                     \
37         {                                               \
38                 .start          = base,                 \
39                 .end            = base + 0x3ff,         \
40                 .flags          = IORESOURCE_MEM,       \
41         }
42 #define IRQ(num)                                        \
43         {                                               \
44                 .start          = num,                  \
45                 .end            = num,                  \
46                 .flags          = IORESOURCE_IRQ,       \
47         }
48 #define NAMED_IRQ(num, _name)                           \
49         {                                               \
50                 .start          = num,                  \
51                 .end            = num,                  \
52                 .name           = _name,                \
53                 .flags          = IORESOURCE_IRQ,       \
54         }
55
56 /* REVISIT these assume *every* device supports DMA, but several
57  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
58  */
59 #define DEFINE_DEV(_name, _id)                                  \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
61 static struct platform_device _name##_id##_device = {           \
62         .name           = #_name,                               \
63         .id             = _id,                                  \
64         .dev            = {                                     \
65                 .dma_mask = &_name##_id##_dma_mask,             \
66                 .coherent_dma_mask = DMA_32BIT_MASK,            \
67         },                                                      \
68         .resource       = _name##_id##_resource,                \
69         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
70 }
71 #define DEFINE_DEV_DATA(_name, _id)                             \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
73 static struct platform_device _name##_id##_device = {           \
74         .name           = #_name,                               \
75         .id             = _id,                                  \
76         .dev            = {                                     \
77                 .dma_mask = &_name##_id##_dma_mask,             \
78                 .platform_data  = &_name##_id##_data,           \
79                 .coherent_dma_mask = DMA_32BIT_MASK,            \
80         },                                                      \
81         .resource       = _name##_id##_resource,                \
82         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
83 }
84
85 #define select_peripheral(pin, periph, flags)                   \
86         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
87
88 #define DEV_CLK(_name, devname, bus, _index)                    \
89 static struct clk devname##_##_name = {                         \
90         .name           = #_name,                               \
91         .dev            = &devname##_device.dev,                \
92         .parent         = &bus##_clk,                           \
93         .mode           = bus##_clk_mode,                       \
94         .get_rate       = bus##_clk_get_rate,                   \
95         .index          = _index,                               \
96 }
97
98 static DEFINE_SPINLOCK(pm_lock);
99
100 static struct clk osc0;
101 static struct clk osc1;
102
103 static unsigned long osc_get_rate(struct clk *clk)
104 {
105         return at32_board_osc_rates[clk->index];
106 }
107
108 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
109 {
110         unsigned long div, mul, rate;
111
112         div = PM_BFEXT(PLLDIV, control) + 1;
113         mul = PM_BFEXT(PLLMUL, control) + 1;
114
115         rate = clk->parent->get_rate(clk->parent);
116         rate = (rate + div / 2) / div;
117         rate *= mul;
118
119         return rate;
120 }
121
122 static long pll_set_rate(struct clk *clk, unsigned long rate,
123                          u32 *pll_ctrl)
124 {
125         unsigned long mul;
126         unsigned long mul_best_fit = 0;
127         unsigned long div;
128         unsigned long div_min;
129         unsigned long div_max;
130         unsigned long div_best_fit = 0;
131         unsigned long base;
132         unsigned long pll_in;
133         unsigned long actual = 0;
134         unsigned long rate_error;
135         unsigned long rate_error_prev = ~0UL;
136         u32 ctrl;
137
138         /* Rate must be between 80 MHz and 200 Mhz. */
139         if (rate < 80000000UL || rate > 200000000UL)
140                 return -EINVAL;
141
142         ctrl = PM_BF(PLLOPT, 4);
143         base = clk->parent->get_rate(clk->parent);
144
145         /* PLL input frequency must be between 6 MHz and 32 MHz. */
146         div_min = DIV_ROUND_UP(base, 32000000UL);
147         div_max = base / 6000000UL;
148
149         if (div_max < div_min)
150                 return -EINVAL;
151
152         for (div = div_min; div <= div_max; div++) {
153                 pll_in = (base + div / 2) / div;
154                 mul = (rate + pll_in / 2) / pll_in;
155
156                 if (mul == 0)
157                         continue;
158
159                 actual = pll_in * mul;
160                 rate_error = abs(actual - rate);
161
162                 if (rate_error < rate_error_prev) {
163                         mul_best_fit = mul;
164                         div_best_fit = div;
165                         rate_error_prev = rate_error;
166                 }
167
168                 if (rate_error == 0)
169                         break;
170         }
171
172         if (div_best_fit == 0)
173                 return -EINVAL;
174
175         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
176         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
177         ctrl |= PM_BF(PLLCOUNT, 16);
178
179         if (clk->parent == &osc1)
180                 ctrl |= PM_BIT(PLLOSC);
181
182         *pll_ctrl = ctrl;
183
184         return actual;
185 }
186
187 static unsigned long pll0_get_rate(struct clk *clk)
188 {
189         u32 control;
190
191         control = pm_readl(PLL0);
192
193         return pll_get_rate(clk, control);
194 }
195
196 static void pll1_mode(struct clk *clk, int enabled)
197 {
198         unsigned long timeout;
199         u32 status;
200         u32 ctrl;
201
202         ctrl = pm_readl(PLL1);
203
204         if (enabled) {
205                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
206                         pr_debug("clk %s: failed to enable, rate not set\n",
207                                         clk->name);
208                         return;
209                 }
210
211                 ctrl |= PM_BIT(PLLEN);
212                 pm_writel(PLL1, ctrl);
213
214                 /* Wait for PLL lock. */
215                 for (timeout = 10000; timeout; timeout--) {
216                         status = pm_readl(ISR);
217                         if (status & PM_BIT(LOCK1))
218                                 break;
219                         udelay(10);
220                 }
221
222                 if (!(status & PM_BIT(LOCK1)))
223                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
224                                         clk->name);
225         } else {
226                 ctrl &= ~PM_BIT(PLLEN);
227                 pm_writel(PLL1, ctrl);
228         }
229 }
230
231 static unsigned long pll1_get_rate(struct clk *clk)
232 {
233         u32 control;
234
235         control = pm_readl(PLL1);
236
237         return pll_get_rate(clk, control);
238 }
239
240 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
241 {
242         u32 ctrl = 0;
243         unsigned long actual_rate;
244
245         actual_rate = pll_set_rate(clk, rate, &ctrl);
246
247         if (apply) {
248                 if (actual_rate != rate)
249                         return -EINVAL;
250                 if (clk->users > 0)
251                         return -EBUSY;
252                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
253                                 clk->name, rate, actual_rate);
254                 pm_writel(PLL1, ctrl);
255         }
256
257         return actual_rate;
258 }
259
260 static int pll1_set_parent(struct clk *clk, struct clk *parent)
261 {
262         u32 ctrl;
263
264         if (clk->users > 0)
265                 return -EBUSY;
266
267         ctrl = pm_readl(PLL1);
268         WARN_ON(ctrl & PM_BIT(PLLEN));
269
270         if (parent == &osc0)
271                 ctrl &= ~PM_BIT(PLLOSC);
272         else if (parent == &osc1)
273                 ctrl |= PM_BIT(PLLOSC);
274         else
275                 return -EINVAL;
276
277         pm_writel(PLL1, ctrl);
278         clk->parent = parent;
279
280         return 0;
281 }
282
283 /*
284  * The AT32AP7000 has five primary clock sources: One 32kHz
285  * oscillator, two crystal oscillators and two PLLs.
286  */
287 static struct clk osc32k = {
288         .name           = "osc32k",
289         .get_rate       = osc_get_rate,
290         .users          = 1,
291         .index          = 0,
292 };
293 static struct clk osc0 = {
294         .name           = "osc0",
295         .get_rate       = osc_get_rate,
296         .users          = 1,
297         .index          = 1,
298 };
299 static struct clk osc1 = {
300         .name           = "osc1",
301         .get_rate       = osc_get_rate,
302         .index          = 2,
303 };
304 static struct clk pll0 = {
305         .name           = "pll0",
306         .get_rate       = pll0_get_rate,
307         .parent         = &osc0,
308 };
309 static struct clk pll1 = {
310         .name           = "pll1",
311         .mode           = pll1_mode,
312         .get_rate       = pll1_get_rate,
313         .set_rate       = pll1_set_rate,
314         .set_parent     = pll1_set_parent,
315         .parent         = &osc0,
316 };
317
318 /*
319  * The main clock can be either osc0 or pll0.  The boot loader may
320  * have chosen one for us, so we don't really know which one until we
321  * have a look at the SM.
322  */
323 static struct clk *main_clock;
324
325 /*
326  * Synchronous clocks are generated from the main clock. The clocks
327  * must satisfy the constraint
328  *   fCPU >= fHSB >= fPB
329  * i.e. each clock must not be faster than its parent.
330  */
331 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
332 {
333         return main_clock->get_rate(main_clock) >> shift;
334 };
335
336 static void cpu_clk_mode(struct clk *clk, int enabled)
337 {
338         unsigned long flags;
339         u32 mask;
340
341         spin_lock_irqsave(&pm_lock, flags);
342         mask = pm_readl(CPU_MASK);
343         if (enabled)
344                 mask |= 1 << clk->index;
345         else
346                 mask &= ~(1 << clk->index);
347         pm_writel(CPU_MASK, mask);
348         spin_unlock_irqrestore(&pm_lock, flags);
349 }
350
351 static unsigned long cpu_clk_get_rate(struct clk *clk)
352 {
353         unsigned long cksel, shift = 0;
354
355         cksel = pm_readl(CKSEL);
356         if (cksel & PM_BIT(CPUDIV))
357                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
358
359         return bus_clk_get_rate(clk, shift);
360 }
361
362 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
363 {
364         u32 control;
365         unsigned long parent_rate, child_div, actual_rate, div;
366
367         parent_rate = clk->parent->get_rate(clk->parent);
368         control = pm_readl(CKSEL);
369
370         if (control & PM_BIT(HSBDIV))
371                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
372         else
373                 child_div = 1;
374
375         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
376                 actual_rate = parent_rate;
377                 control &= ~PM_BIT(CPUDIV);
378         } else {
379                 unsigned int cpusel;
380                 div = (parent_rate + rate / 2) / rate;
381                 if (div > child_div)
382                         div = child_div;
383                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
384                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
385                 actual_rate = parent_rate / (1 << (cpusel + 1));
386         }
387
388         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
389                         clk->name, rate, actual_rate);
390
391         if (apply)
392                 pm_writel(CKSEL, control);
393
394         return actual_rate;
395 }
396
397 static void hsb_clk_mode(struct clk *clk, int enabled)
398 {
399         unsigned long flags;
400         u32 mask;
401
402         spin_lock_irqsave(&pm_lock, flags);
403         mask = pm_readl(HSB_MASK);
404         if (enabled)
405                 mask |= 1 << clk->index;
406         else
407                 mask &= ~(1 << clk->index);
408         pm_writel(HSB_MASK, mask);
409         spin_unlock_irqrestore(&pm_lock, flags);
410 }
411
412 static unsigned long hsb_clk_get_rate(struct clk *clk)
413 {
414         unsigned long cksel, shift = 0;
415
416         cksel = pm_readl(CKSEL);
417         if (cksel & PM_BIT(HSBDIV))
418                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
419
420         return bus_clk_get_rate(clk, shift);
421 }
422
423 static void pba_clk_mode(struct clk *clk, int enabled)
424 {
425         unsigned long flags;
426         u32 mask;
427
428         spin_lock_irqsave(&pm_lock, flags);
429         mask = pm_readl(PBA_MASK);
430         if (enabled)
431                 mask |= 1 << clk->index;
432         else
433                 mask &= ~(1 << clk->index);
434         pm_writel(PBA_MASK, mask);
435         spin_unlock_irqrestore(&pm_lock, flags);
436 }
437
438 static unsigned long pba_clk_get_rate(struct clk *clk)
439 {
440         unsigned long cksel, shift = 0;
441
442         cksel = pm_readl(CKSEL);
443         if (cksel & PM_BIT(PBADIV))
444                 shift = PM_BFEXT(PBASEL, cksel) + 1;
445
446         return bus_clk_get_rate(clk, shift);
447 }
448
449 static void pbb_clk_mode(struct clk *clk, int enabled)
450 {
451         unsigned long flags;
452         u32 mask;
453
454         spin_lock_irqsave(&pm_lock, flags);
455         mask = pm_readl(PBB_MASK);
456         if (enabled)
457                 mask |= 1 << clk->index;
458         else
459                 mask &= ~(1 << clk->index);
460         pm_writel(PBB_MASK, mask);
461         spin_unlock_irqrestore(&pm_lock, flags);
462 }
463
464 static unsigned long pbb_clk_get_rate(struct clk *clk)
465 {
466         unsigned long cksel, shift = 0;
467
468         cksel = pm_readl(CKSEL);
469         if (cksel & PM_BIT(PBBDIV))
470                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
471
472         return bus_clk_get_rate(clk, shift);
473 }
474
475 static struct clk cpu_clk = {
476         .name           = "cpu",
477         .get_rate       = cpu_clk_get_rate,
478         .set_rate       = cpu_clk_set_rate,
479         .users          = 1,
480 };
481 static struct clk hsb_clk = {
482         .name           = "hsb",
483         .parent         = &cpu_clk,
484         .get_rate       = hsb_clk_get_rate,
485 };
486 static struct clk pba_clk = {
487         .name           = "pba",
488         .parent         = &hsb_clk,
489         .mode           = hsb_clk_mode,
490         .get_rate       = pba_clk_get_rate,
491         .index          = 1,
492 };
493 static struct clk pbb_clk = {
494         .name           = "pbb",
495         .parent         = &hsb_clk,
496         .mode           = hsb_clk_mode,
497         .get_rate       = pbb_clk_get_rate,
498         .users          = 1,
499         .index          = 2,
500 };
501
502 /* --------------------------------------------------------------------
503  *  Generic Clock operations
504  * -------------------------------------------------------------------- */
505
506 static void genclk_mode(struct clk *clk, int enabled)
507 {
508         u32 control;
509
510         control = pm_readl(GCCTRL(clk->index));
511         if (enabled)
512                 control |= PM_BIT(CEN);
513         else
514                 control &= ~PM_BIT(CEN);
515         pm_writel(GCCTRL(clk->index), control);
516 }
517
518 static unsigned long genclk_get_rate(struct clk *clk)
519 {
520         u32 control;
521         unsigned long div = 1;
522
523         control = pm_readl(GCCTRL(clk->index));
524         if (control & PM_BIT(DIVEN))
525                 div = 2 * (PM_BFEXT(DIV, control) + 1);
526
527         return clk->parent->get_rate(clk->parent) / div;
528 }
529
530 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
531 {
532         u32 control;
533         unsigned long parent_rate, actual_rate, div;
534
535         parent_rate = clk->parent->get_rate(clk->parent);
536         control = pm_readl(GCCTRL(clk->index));
537
538         if (rate > 3 * parent_rate / 4) {
539                 actual_rate = parent_rate;
540                 control &= ~PM_BIT(DIVEN);
541         } else {
542                 div = (parent_rate + rate) / (2 * rate) - 1;
543                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
544                 actual_rate = parent_rate / (2 * (div + 1));
545         }
546
547         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
548                 clk->name, rate, actual_rate);
549
550         if (apply)
551                 pm_writel(GCCTRL(clk->index), control);
552
553         return actual_rate;
554 }
555
556 int genclk_set_parent(struct clk *clk, struct clk *parent)
557 {
558         u32 control;
559
560         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
561                 clk->name, parent->name, clk->parent->name);
562
563         control = pm_readl(GCCTRL(clk->index));
564
565         if (parent == &osc1 || parent == &pll1)
566                 control |= PM_BIT(OSCSEL);
567         else if (parent == &osc0 || parent == &pll0)
568                 control &= ~PM_BIT(OSCSEL);
569         else
570                 return -EINVAL;
571
572         if (parent == &pll0 || parent == &pll1)
573                 control |= PM_BIT(PLLSEL);
574         else
575                 control &= ~PM_BIT(PLLSEL);
576
577         pm_writel(GCCTRL(clk->index), control);
578         clk->parent = parent;
579
580         return 0;
581 }
582
583 static void __init genclk_init_parent(struct clk *clk)
584 {
585         u32 control;
586         struct clk *parent;
587
588         BUG_ON(clk->index > 7);
589
590         control = pm_readl(GCCTRL(clk->index));
591         if (control & PM_BIT(OSCSEL))
592                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
593         else
594                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
595
596         clk->parent = parent;
597 }
598
599 static struct dw_dma_platform_data dw_dmac0_data = {
600         .nr_channels    = 3,
601 };
602
603 static struct resource dw_dmac0_resource[] = {
604         PBMEM(0xff200000),
605         IRQ(2),
606 };
607 DEFINE_DEV_DATA(dw_dmac, 0);
608 DEV_CLK(hclk, dw_dmac0, hsb, 10);
609
610 /* --------------------------------------------------------------------
611  *  System peripherals
612  * -------------------------------------------------------------------- */
613 static struct resource at32_pm0_resource[] = {
614         {
615                 .start  = 0xfff00000,
616                 .end    = 0xfff0007f,
617                 .flags  = IORESOURCE_MEM,
618         },
619         IRQ(20),
620 };
621
622 static struct resource at32ap700x_rtc0_resource[] = {
623         {
624                 .start  = 0xfff00080,
625                 .end    = 0xfff000af,
626                 .flags  = IORESOURCE_MEM,
627         },
628         IRQ(21),
629 };
630
631 static struct resource at32_wdt0_resource[] = {
632         {
633                 .start  = 0xfff000b0,
634                 .end    = 0xfff000cf,
635                 .flags  = IORESOURCE_MEM,
636         },
637 };
638
639 static struct resource at32_eic0_resource[] = {
640         {
641                 .start  = 0xfff00100,
642                 .end    = 0xfff0013f,
643                 .flags  = IORESOURCE_MEM,
644         },
645         IRQ(19),
646 };
647
648 DEFINE_DEV(at32_pm, 0);
649 DEFINE_DEV(at32ap700x_rtc, 0);
650 DEFINE_DEV(at32_wdt, 0);
651 DEFINE_DEV(at32_eic, 0);
652
653 /*
654  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
655  * is always running.
656  */
657 static struct clk at32_pm_pclk = {
658         .name           = "pclk",
659         .dev            = &at32_pm0_device.dev,
660         .parent         = &pbb_clk,
661         .mode           = pbb_clk_mode,
662         .get_rate       = pbb_clk_get_rate,
663         .users          = 1,
664         .index          = 0,
665 };
666
667 static struct resource intc0_resource[] = {
668         PBMEM(0xfff00400),
669 };
670 struct platform_device at32_intc0_device = {
671         .name           = "intc",
672         .id             = 0,
673         .resource       = intc0_resource,
674         .num_resources  = ARRAY_SIZE(intc0_resource),
675 };
676 DEV_CLK(pclk, at32_intc0, pbb, 1);
677
678 static struct clk ebi_clk = {
679         .name           = "ebi",
680         .parent         = &hsb_clk,
681         .mode           = hsb_clk_mode,
682         .get_rate       = hsb_clk_get_rate,
683         .users          = 1,
684 };
685 static struct clk hramc_clk = {
686         .name           = "hramc",
687         .parent         = &hsb_clk,
688         .mode           = hsb_clk_mode,
689         .get_rate       = hsb_clk_get_rate,
690         .users          = 1,
691         .index          = 3,
692 };
693 static struct clk sdramc_clk = {
694         .name           = "sdramc_clk",
695         .parent         = &pbb_clk,
696         .mode           = pbb_clk_mode,
697         .get_rate       = pbb_clk_get_rate,
698         .users          = 1,
699         .index          = 14,
700 };
701
702 static struct resource smc0_resource[] = {
703         PBMEM(0xfff03400),
704 };
705 DEFINE_DEV(smc, 0);
706 DEV_CLK(pclk, smc0, pbb, 13);
707 DEV_CLK(mck, smc0, hsb, 0);
708
709 static struct platform_device pdc_device = {
710         .name           = "pdc",
711         .id             = 0,
712 };
713 DEV_CLK(hclk, pdc, hsb, 4);
714 DEV_CLK(pclk, pdc, pba, 16);
715
716 static struct clk pico_clk = {
717         .name           = "pico",
718         .parent         = &cpu_clk,
719         .mode           = cpu_clk_mode,
720         .get_rate       = cpu_clk_get_rate,
721         .users          = 1,
722 };
723
724 /* --------------------------------------------------------------------
725  * HMATRIX
726  * -------------------------------------------------------------------- */
727
728 struct clk at32_hmatrix_clk = {
729         .name           = "hmatrix_clk",
730         .parent         = &pbb_clk,
731         .mode           = pbb_clk_mode,
732         .get_rate       = pbb_clk_get_rate,
733         .index          = 2,
734         .users          = 1,
735 };
736
737 /*
738  * Set bits in the HMATRIX Special Function Register (SFR) used by the
739  * External Bus Interface (EBI). This can be used to enable special
740  * features like CompactFlash support, NAND Flash support, etc. on
741  * certain chipselects.
742  */
743 static inline void set_ebi_sfr_bits(u32 mask)
744 {
745         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
746 }
747
748 /* --------------------------------------------------------------------
749  *  Timer/Counter (TC)
750  * -------------------------------------------------------------------- */
751
752 static struct resource at32_tcb0_resource[] = {
753         PBMEM(0xfff00c00),
754         IRQ(22),
755 };
756 static struct platform_device at32_tcb0_device = {
757         .name           = "atmel_tcb",
758         .id             = 0,
759         .resource       = at32_tcb0_resource,
760         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
761 };
762 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
763
764 static struct resource at32_tcb1_resource[] = {
765         PBMEM(0xfff01000),
766         IRQ(23),
767 };
768 static struct platform_device at32_tcb1_device = {
769         .name           = "atmel_tcb",
770         .id             = 1,
771         .resource       = at32_tcb1_resource,
772         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
773 };
774 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
775
776 /* --------------------------------------------------------------------
777  *  PIO
778  * -------------------------------------------------------------------- */
779
780 static struct resource pio0_resource[] = {
781         PBMEM(0xffe02800),
782         IRQ(13),
783 };
784 DEFINE_DEV(pio, 0);
785 DEV_CLK(mck, pio0, pba, 10);
786
787 static struct resource pio1_resource[] = {
788         PBMEM(0xffe02c00),
789         IRQ(14),
790 };
791 DEFINE_DEV(pio, 1);
792 DEV_CLK(mck, pio1, pba, 11);
793
794 static struct resource pio2_resource[] = {
795         PBMEM(0xffe03000),
796         IRQ(15),
797 };
798 DEFINE_DEV(pio, 2);
799 DEV_CLK(mck, pio2, pba, 12);
800
801 static struct resource pio3_resource[] = {
802         PBMEM(0xffe03400),
803         IRQ(16),
804 };
805 DEFINE_DEV(pio, 3);
806 DEV_CLK(mck, pio3, pba, 13);
807
808 static struct resource pio4_resource[] = {
809         PBMEM(0xffe03800),
810         IRQ(17),
811 };
812 DEFINE_DEV(pio, 4);
813 DEV_CLK(mck, pio4, pba, 14);
814
815 void __init at32_add_system_devices(void)
816 {
817         platform_device_register(&at32_pm0_device);
818         platform_device_register(&at32_intc0_device);
819         platform_device_register(&at32ap700x_rtc0_device);
820         platform_device_register(&at32_wdt0_device);
821         platform_device_register(&at32_eic0_device);
822         platform_device_register(&smc0_device);
823         platform_device_register(&pdc_device);
824         platform_device_register(&dw_dmac0_device);
825
826         platform_device_register(&at32_tcb0_device);
827         platform_device_register(&at32_tcb1_device);
828
829         platform_device_register(&pio0_device);
830         platform_device_register(&pio1_device);
831         platform_device_register(&pio2_device);
832         platform_device_register(&pio3_device);
833         platform_device_register(&pio4_device);
834 }
835
836 /* --------------------------------------------------------------------
837  *  PSIF
838  * -------------------------------------------------------------------- */
839 static struct resource atmel_psif0_resource[] __initdata = {
840         {
841                 .start  = 0xffe03c00,
842                 .end    = 0xffe03cff,
843                 .flags  = IORESOURCE_MEM,
844         },
845         IRQ(18),
846 };
847 static struct clk atmel_psif0_pclk = {
848         .name           = "pclk",
849         .parent         = &pba_clk,
850         .mode           = pba_clk_mode,
851         .get_rate       = pba_clk_get_rate,
852         .index          = 15,
853 };
854
855 static struct resource atmel_psif1_resource[] __initdata = {
856         {
857                 .start  = 0xffe03d00,
858                 .end    = 0xffe03dff,
859                 .flags  = IORESOURCE_MEM,
860         },
861         IRQ(18),
862 };
863 static struct clk atmel_psif1_pclk = {
864         .name           = "pclk",
865         .parent         = &pba_clk,
866         .mode           = pba_clk_mode,
867         .get_rate       = pba_clk_get_rate,
868         .index          = 15,
869 };
870
871 struct platform_device *__init at32_add_device_psif(unsigned int id)
872 {
873         struct platform_device *pdev;
874
875         if (!(id == 0 || id == 1))
876                 return NULL;
877
878         pdev = platform_device_alloc("atmel_psif", id);
879         if (!pdev)
880                 return NULL;
881
882         switch (id) {
883         case 0:
884                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
885                                         ARRAY_SIZE(atmel_psif0_resource)))
886                         goto err_add_resources;
887                 atmel_psif0_pclk.dev = &pdev->dev;
888                 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
889                 select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
890                 break;
891         case 1:
892                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
893                                         ARRAY_SIZE(atmel_psif1_resource)))
894                         goto err_add_resources;
895                 atmel_psif1_pclk.dev = &pdev->dev;
896                 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
897                 select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
898                 break;
899         default:
900                 return NULL;
901         }
902
903         platform_device_add(pdev);
904         return pdev;
905
906 err_add_resources:
907         platform_device_put(pdev);
908         return NULL;
909 }
910
911 /* --------------------------------------------------------------------
912  *  USART
913  * -------------------------------------------------------------------- */
914
915 static struct atmel_uart_data atmel_usart0_data = {
916         .use_dma_tx     = 1,
917         .use_dma_rx     = 1,
918 };
919 static struct resource atmel_usart0_resource[] = {
920         PBMEM(0xffe00c00),
921         IRQ(6),
922 };
923 DEFINE_DEV_DATA(atmel_usart, 0);
924 DEV_CLK(usart, atmel_usart0, pba, 3);
925
926 static struct atmel_uart_data atmel_usart1_data = {
927         .use_dma_tx     = 1,
928         .use_dma_rx     = 1,
929 };
930 static struct resource atmel_usart1_resource[] = {
931         PBMEM(0xffe01000),
932         IRQ(7),
933 };
934 DEFINE_DEV_DATA(atmel_usart, 1);
935 DEV_CLK(usart, atmel_usart1, pba, 4);
936
937 static struct atmel_uart_data atmel_usart2_data = {
938         .use_dma_tx     = 1,
939         .use_dma_rx     = 1,
940 };
941 static struct resource atmel_usart2_resource[] = {
942         PBMEM(0xffe01400),
943         IRQ(8),
944 };
945 DEFINE_DEV_DATA(atmel_usart, 2);
946 DEV_CLK(usart, atmel_usart2, pba, 5);
947
948 static struct atmel_uart_data atmel_usart3_data = {
949         .use_dma_tx     = 1,
950         .use_dma_rx     = 1,
951 };
952 static struct resource atmel_usart3_resource[] = {
953         PBMEM(0xffe01800),
954         IRQ(9),
955 };
956 DEFINE_DEV_DATA(atmel_usart, 3);
957 DEV_CLK(usart, atmel_usart3, pba, 6);
958
959 static inline void configure_usart0_pins(void)
960 {
961         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
962         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
963 }
964
965 static inline void configure_usart1_pins(void)
966 {
967         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
968         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
969 }
970
971 static inline void configure_usart2_pins(void)
972 {
973         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
974         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
975 }
976
977 static inline void configure_usart3_pins(void)
978 {
979         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
980         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
981 }
982
983 static struct platform_device *__initdata at32_usarts[4];
984
985 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
986 {
987         struct platform_device *pdev;
988
989         switch (hw_id) {
990         case 0:
991                 pdev = &atmel_usart0_device;
992                 configure_usart0_pins();
993                 break;
994         case 1:
995                 pdev = &atmel_usart1_device;
996                 configure_usart1_pins();
997                 break;
998         case 2:
999                 pdev = &atmel_usart2_device;
1000                 configure_usart2_pins();
1001                 break;
1002         case 3:
1003                 pdev = &atmel_usart3_device;
1004                 configure_usart3_pins();
1005                 break;
1006         default:
1007                 return;
1008         }
1009
1010         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1011                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1012                 struct atmel_uart_data *data = pdev->dev.platform_data;
1013                 data->regs = (void __iomem *)pdev->resource[0].start;
1014         }
1015
1016         pdev->id = line;
1017         at32_usarts[line] = pdev;
1018 }
1019
1020 struct platform_device *__init at32_add_device_usart(unsigned int id)
1021 {
1022         platform_device_register(at32_usarts[id]);
1023         return at32_usarts[id];
1024 }
1025
1026 struct platform_device *atmel_default_console_device;
1027
1028 void __init at32_setup_serial_console(unsigned int usart_id)
1029 {
1030         atmel_default_console_device = at32_usarts[usart_id];
1031 }
1032
1033 /* --------------------------------------------------------------------
1034  *  Ethernet
1035  * -------------------------------------------------------------------- */
1036
1037 #ifdef CONFIG_CPU_AT32AP7000
1038 static struct eth_platform_data macb0_data;
1039 static struct resource macb0_resource[] = {
1040         PBMEM(0xfff01800),
1041         IRQ(25),
1042 };
1043 DEFINE_DEV_DATA(macb, 0);
1044 DEV_CLK(hclk, macb0, hsb, 8);
1045 DEV_CLK(pclk, macb0, pbb, 6);
1046
1047 static struct eth_platform_data macb1_data;
1048 static struct resource macb1_resource[] = {
1049         PBMEM(0xfff01c00),
1050         IRQ(26),
1051 };
1052 DEFINE_DEV_DATA(macb, 1);
1053 DEV_CLK(hclk, macb1, hsb, 9);
1054 DEV_CLK(pclk, macb1, pbb, 7);
1055
1056 struct platform_device *__init
1057 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1058 {
1059         struct platform_device *pdev;
1060
1061         switch (id) {
1062         case 0:
1063                 pdev = &macb0_device;
1064
1065                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
1066                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
1067                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1068                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1069                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1070                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1071                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1072                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1073                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1074                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1075
1076                 if (!data->is_rmii) {
1077                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1078                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1079                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1080                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1081                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1082                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1083                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1084                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1085                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1086                 }
1087                 break;
1088
1089         case 1:
1090                 pdev = &macb1_device;
1091
1092                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1093                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1094                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1095                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1096                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1097                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1098                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1099                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1100                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1101                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1102
1103                 if (!data->is_rmii) {
1104                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1105                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1106                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1107                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1108                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1109                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1110                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1111                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1112                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1113                 }
1114                 break;
1115
1116         default:
1117                 return NULL;
1118         }
1119
1120         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1121         platform_device_register(pdev);
1122
1123         return pdev;
1124 }
1125 #endif
1126
1127 /* --------------------------------------------------------------------
1128  *  SPI
1129  * -------------------------------------------------------------------- */
1130 static struct resource atmel_spi0_resource[] = {
1131         PBMEM(0xffe00000),
1132         IRQ(3),
1133 };
1134 DEFINE_DEV(atmel_spi, 0);
1135 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1136
1137 static struct resource atmel_spi1_resource[] = {
1138         PBMEM(0xffe00400),
1139         IRQ(4),
1140 };
1141 DEFINE_DEV(atmel_spi, 1);
1142 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1143
1144 static void __init
1145 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1146                       unsigned int n, const u8 *pins)
1147 {
1148         unsigned int pin, mode;
1149
1150         for (; n; n--, b++) {
1151                 b->bus_num = bus_num;
1152                 if (b->chip_select >= 4)
1153                         continue;
1154                 pin = (unsigned)b->controller_data;
1155                 if (!pin) {
1156                         pin = pins[b->chip_select];
1157                         b->controller_data = (void *)pin;
1158                 }
1159                 mode = AT32_GPIOF_OUTPUT;
1160                 if (!(b->mode & SPI_CS_HIGH))
1161                         mode |= AT32_GPIOF_HIGH;
1162                 at32_select_gpio(pin, mode);
1163         }
1164 }
1165
1166 struct platform_device *__init
1167 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1168 {
1169         /*
1170          * Manage the chipselects as GPIOs, normally using the same pins
1171          * the SPI controller expects; but boards can use other pins.
1172          */
1173         static u8 __initdata spi0_pins[] =
1174                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1175                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1176         static u8 __initdata spi1_pins[] =
1177                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1178                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1179         struct platform_device *pdev;
1180
1181         switch (id) {
1182         case 0:
1183                 pdev = &atmel_spi0_device;
1184                 /* pullup MISO so a level is always defined */
1185                 select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
1186                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1187                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1188                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1189                 break;
1190
1191         case 1:
1192                 pdev = &atmel_spi1_device;
1193                 /* pullup MISO so a level is always defined */
1194                 select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
1195                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1196                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1197                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1198                 break;
1199
1200         default:
1201                 return NULL;
1202         }
1203
1204         spi_register_board_info(b, n);
1205         platform_device_register(pdev);
1206         return pdev;
1207 }
1208
1209 /* --------------------------------------------------------------------
1210  *  TWI
1211  * -------------------------------------------------------------------- */
1212 static struct resource atmel_twi0_resource[] __initdata = {
1213         PBMEM(0xffe00800),
1214         IRQ(5),
1215 };
1216 static struct clk atmel_twi0_pclk = {
1217         .name           = "twi_pclk",
1218         .parent         = &pba_clk,
1219         .mode           = pba_clk_mode,
1220         .get_rate       = pba_clk_get_rate,
1221         .index          = 2,
1222 };
1223
1224 struct platform_device *__init at32_add_device_twi(unsigned int id,
1225                                                     struct i2c_board_info *b,
1226                                                     unsigned int n)
1227 {
1228         struct platform_device *pdev;
1229
1230         if (id != 0)
1231                 return NULL;
1232
1233         pdev = platform_device_alloc("atmel_twi", id);
1234         if (!pdev)
1235                 return NULL;
1236
1237         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1238                                 ARRAY_SIZE(atmel_twi0_resource)))
1239                 goto err_add_resources;
1240
1241         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1242         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1243
1244         atmel_twi0_pclk.dev = &pdev->dev;
1245
1246         if (b)
1247                 i2c_register_board_info(id, b, n);
1248
1249         platform_device_add(pdev);
1250         return pdev;
1251
1252 err_add_resources:
1253         platform_device_put(pdev);
1254         return NULL;
1255 }
1256
1257 /* --------------------------------------------------------------------
1258  * MMC
1259  * -------------------------------------------------------------------- */
1260 static struct resource atmel_mci0_resource[] __initdata = {
1261         PBMEM(0xfff02400),
1262         IRQ(28),
1263 };
1264 static struct clk atmel_mci0_pclk = {
1265         .name           = "mci_clk",
1266         .parent         = &pbb_clk,
1267         .mode           = pbb_clk_mode,
1268         .get_rate       = pbb_clk_get_rate,
1269         .index          = 9,
1270 };
1271
1272 struct platform_device *__init
1273 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1274 {
1275         struct platform_device          *pdev;
1276         struct dw_dma_slave             *dws;
1277
1278         if (id != 0 || !data)
1279                 return NULL;
1280
1281         /* Must have at least one usable slot */
1282         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1283                 return NULL;
1284
1285         pdev = platform_device_alloc("atmel_mci", id);
1286         if (!pdev)
1287                 goto fail;
1288
1289         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1290                                 ARRAY_SIZE(atmel_mci0_resource)))
1291                 goto fail;
1292
1293         if (data->dma_slave)
1294                 dws = kmemdup(to_dw_dma_slave(data->dma_slave),
1295                                 sizeof(struct dw_dma_slave), GFP_KERNEL);
1296         else
1297                 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1298
1299         dws->slave.dev = &pdev->dev;
1300         dws->slave.dma_dev = &dw_dmac0_device.dev;
1301         dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
1302         dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1303                                 | DWC_CFGH_DST_PER(1));
1304         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1305                                 | DWC_CFGL_HS_SRC_POL);
1306
1307         data->dma_slave = &dws->slave;
1308
1309         if (platform_device_add_data(pdev, data,
1310                                 sizeof(struct mci_platform_data)))
1311                 goto fail;
1312
1313         /* CLK line is common to both slots */
1314         select_peripheral(PA(10), PERIPH_A, 0);
1315
1316         switch (data->slot[0].bus_width) {
1317         case 4:
1318                 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1319                 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1320                 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1321                 /* fall through */
1322         case 1:
1323                 select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1324                 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1325
1326                 if (gpio_is_valid(data->slot[0].detect_pin))
1327                         at32_select_gpio(data->slot[0].detect_pin, 0);
1328                 if (gpio_is_valid(data->slot[0].wp_pin))
1329                         at32_select_gpio(data->slot[0].wp_pin, 0);
1330                 break;
1331         case 0:
1332                 /* Slot is unused */
1333                 break;
1334         default:
1335                 goto fail;
1336         }
1337
1338         switch (data->slot[1].bus_width) {
1339         case 4:
1340                 select_peripheral(PB(8),  PERIPH_B, 0); /* DATA1 */
1341                 select_peripheral(PB(9),  PERIPH_B, 0); /* DATA2 */
1342                 select_peripheral(PB(10), PERIPH_B, 0); /* DATA3 */
1343                 /* fall through */
1344         case 1:
1345                 select_peripheral(PB(6),  PERIPH_B, 0); /* CMD   */
1346                 select_peripheral(PB(7),  PERIPH_B, 0); /* DATA0 */
1347
1348                 if (gpio_is_valid(data->slot[1].detect_pin))
1349                         at32_select_gpio(data->slot[1].detect_pin, 0);
1350                 if (gpio_is_valid(data->slot[1].wp_pin))
1351                         at32_select_gpio(data->slot[1].wp_pin, 0);
1352                 break;
1353         case 0:
1354                 /* Slot is unused */
1355                 break;
1356         default:
1357                 if (!data->slot[0].bus_width)
1358                         goto fail;
1359
1360                 data->slot[1].bus_width = 0;
1361                 break;
1362         }
1363
1364         atmel_mci0_pclk.dev = &pdev->dev;
1365
1366         platform_device_add(pdev);
1367         return pdev;
1368
1369 fail:
1370         platform_device_put(pdev);
1371         return NULL;
1372 }
1373
1374 /* --------------------------------------------------------------------
1375  *  LCDC
1376  * -------------------------------------------------------------------- */
1377 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1378 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1379 static struct resource atmel_lcdfb0_resource[] = {
1380         {
1381                 .start          = 0xff000000,
1382                 .end            = 0xff000fff,
1383                 .flags          = IORESOURCE_MEM,
1384         },
1385         IRQ(1),
1386         {
1387                 /* Placeholder for pre-allocated fb memory */
1388                 .start          = 0x00000000,
1389                 .end            = 0x00000000,
1390                 .flags          = 0,
1391         },
1392 };
1393 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1394 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1395 static struct clk atmel_lcdfb0_pixclk = {
1396         .name           = "lcdc_clk",
1397         .dev            = &atmel_lcdfb0_device.dev,
1398         .mode           = genclk_mode,
1399         .get_rate       = genclk_get_rate,
1400         .set_rate       = genclk_set_rate,
1401         .set_parent     = genclk_set_parent,
1402         .index          = 7,
1403 };
1404
1405 struct platform_device *__init
1406 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1407                      unsigned long fbmem_start, unsigned long fbmem_len,
1408                      u64 pin_mask)
1409 {
1410         struct platform_device *pdev;
1411         struct atmel_lcdfb_info *info;
1412         struct fb_monspecs *monspecs;
1413         struct fb_videomode *modedb;
1414         unsigned int modedb_size;
1415         int i;
1416
1417         /*
1418          * Do a deep copy of the fb data, monspecs and modedb. Make
1419          * sure all allocations are done before setting up the
1420          * portmux.
1421          */
1422         monspecs = kmemdup(data->default_monspecs,
1423                            sizeof(struct fb_monspecs), GFP_KERNEL);
1424         if (!monspecs)
1425                 return NULL;
1426
1427         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1428         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1429         if (!modedb)
1430                 goto err_dup_modedb;
1431         monspecs->modedb = modedb;
1432
1433         switch (id) {
1434         case 0:
1435                 pdev = &atmel_lcdfb0_device;
1436
1437                 if (pin_mask == 0ULL)
1438                         /* Default to "full" lcdc control signals and 24bit */
1439                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1440
1441                 /* LCDC on port C */
1442                 for (i = 19; i < 32; i++) {
1443                         if (pin_mask & (1ULL << i))
1444                                 at32_select_periph(GPIO_PIOC_BASE + i,
1445                                                 GPIO_PERIPH_A, 0);
1446                 }
1447
1448                 /* LCDC on port D */
1449                 for (i = 0; i < 18; i++) {
1450                         if (pin_mask & (1ULL << i))
1451                                 at32_select_periph(GPIO_PIOD_BASE + i,
1452                                                 GPIO_PERIPH_A, 0);
1453                 }
1454
1455                 /* LCDC on port E */
1456                 for (i = 0; i < 19; i++) {
1457                         if (pin_mask & (1ULL << (i + 32)))
1458                                 at32_select_periph(GPIO_PIOE_BASE + i,
1459                                                 GPIO_PERIPH_B, 0);
1460                 }
1461
1462                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1463                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1464                 break;
1465
1466         default:
1467                 goto err_invalid_id;
1468         }
1469
1470         if (fbmem_len) {
1471                 pdev->resource[2].start = fbmem_start;
1472                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1473                 pdev->resource[2].flags = IORESOURCE_MEM;
1474         }
1475
1476         info = pdev->dev.platform_data;
1477         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1478         info->default_monspecs = monspecs;
1479
1480         platform_device_register(pdev);
1481         return pdev;
1482
1483 err_invalid_id:
1484         kfree(modedb);
1485 err_dup_modedb:
1486         kfree(monspecs);
1487         return NULL;
1488 }
1489 #endif
1490
1491 /* --------------------------------------------------------------------
1492  *  PWM
1493  * -------------------------------------------------------------------- */
1494 static struct resource atmel_pwm0_resource[] __initdata = {
1495         PBMEM(0xfff01400),
1496         IRQ(24),
1497 };
1498 static struct clk atmel_pwm0_mck = {
1499         .name           = "pwm_clk",
1500         .parent         = &pbb_clk,
1501         .mode           = pbb_clk_mode,
1502         .get_rate       = pbb_clk_get_rate,
1503         .index          = 5,
1504 };
1505
1506 struct platform_device *__init at32_add_device_pwm(u32 mask)
1507 {
1508         struct platform_device *pdev;
1509
1510         if (!mask)
1511                 return NULL;
1512
1513         pdev = platform_device_alloc("atmel_pwm", 0);
1514         if (!pdev)
1515                 return NULL;
1516
1517         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1518                                 ARRAY_SIZE(atmel_pwm0_resource)))
1519                 goto out_free_pdev;
1520
1521         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1522                 goto out_free_pdev;
1523
1524         if (mask & (1 << 0))
1525                 select_peripheral(PA(28), PERIPH_A, 0);
1526         if (mask & (1 << 1))
1527                 select_peripheral(PA(29), PERIPH_A, 0);
1528         if (mask & (1 << 2))
1529                 select_peripheral(PA(21), PERIPH_B, 0);
1530         if (mask & (1 << 3))
1531                 select_peripheral(PA(22), PERIPH_B, 0);
1532
1533         atmel_pwm0_mck.dev = &pdev->dev;
1534
1535         platform_device_add(pdev);
1536
1537         return pdev;
1538
1539 out_free_pdev:
1540         platform_device_put(pdev);
1541         return NULL;
1542 }
1543
1544 /* --------------------------------------------------------------------
1545  *  SSC
1546  * -------------------------------------------------------------------- */
1547 static struct resource ssc0_resource[] = {
1548         PBMEM(0xffe01c00),
1549         IRQ(10),
1550 };
1551 DEFINE_DEV(ssc, 0);
1552 DEV_CLK(pclk, ssc0, pba, 7);
1553
1554 static struct resource ssc1_resource[] = {
1555         PBMEM(0xffe02000),
1556         IRQ(11),
1557 };
1558 DEFINE_DEV(ssc, 1);
1559 DEV_CLK(pclk, ssc1, pba, 8);
1560
1561 static struct resource ssc2_resource[] = {
1562         PBMEM(0xffe02400),
1563         IRQ(12),
1564 };
1565 DEFINE_DEV(ssc, 2);
1566 DEV_CLK(pclk, ssc2, pba, 9);
1567
1568 struct platform_device *__init
1569 at32_add_device_ssc(unsigned int id, unsigned int flags)
1570 {
1571         struct platform_device *pdev;
1572
1573         switch (id) {
1574         case 0:
1575                 pdev = &ssc0_device;
1576                 if (flags & ATMEL_SSC_RF)
1577                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1578                 if (flags & ATMEL_SSC_RK)
1579                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1580                 if (flags & ATMEL_SSC_TK)
1581                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1582                 if (flags & ATMEL_SSC_TF)
1583                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1584                 if (flags & ATMEL_SSC_TD)
1585                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1586                 if (flags & ATMEL_SSC_RD)
1587                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1588                 break;
1589         case 1:
1590                 pdev = &ssc1_device;
1591                 if (flags & ATMEL_SSC_RF)
1592                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1593                 if (flags & ATMEL_SSC_RK)
1594                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1595                 if (flags & ATMEL_SSC_TK)
1596                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1597                 if (flags & ATMEL_SSC_TF)
1598                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1599                 if (flags & ATMEL_SSC_TD)
1600                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1601                 if (flags & ATMEL_SSC_RD)
1602                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1603                 break;
1604         case 2:
1605                 pdev = &ssc2_device;
1606                 if (flags & ATMEL_SSC_TD)
1607                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1608                 if (flags & ATMEL_SSC_RD)
1609                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1610                 if (flags & ATMEL_SSC_TK)
1611                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1612                 if (flags & ATMEL_SSC_TF)
1613                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1614                 if (flags & ATMEL_SSC_RF)
1615                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1616                 if (flags & ATMEL_SSC_RK)
1617                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1618                 break;
1619         default:
1620                 return NULL;
1621         }
1622
1623         platform_device_register(pdev);
1624         return pdev;
1625 }
1626
1627 /* --------------------------------------------------------------------
1628  *  USB Device Controller
1629  * -------------------------------------------------------------------- */
1630 static struct resource usba0_resource[] __initdata = {
1631         {
1632                 .start          = 0xff300000,
1633                 .end            = 0xff3fffff,
1634                 .flags          = IORESOURCE_MEM,
1635         }, {
1636                 .start          = 0xfff03000,
1637                 .end            = 0xfff033ff,
1638                 .flags          = IORESOURCE_MEM,
1639         },
1640         IRQ(31),
1641 };
1642 static struct clk usba0_pclk = {
1643         .name           = "pclk",
1644         .parent         = &pbb_clk,
1645         .mode           = pbb_clk_mode,
1646         .get_rate       = pbb_clk_get_rate,
1647         .index          = 12,
1648 };
1649 static struct clk usba0_hclk = {
1650         .name           = "hclk",
1651         .parent         = &hsb_clk,
1652         .mode           = hsb_clk_mode,
1653         .get_rate       = hsb_clk_get_rate,
1654         .index          = 6,
1655 };
1656
1657 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1658         [idx] = {                                               \
1659                 .name           = nam,                          \
1660                 .index          = idx,                          \
1661                 .fifo_size      = maxpkt,                       \
1662                 .nr_banks       = maxbk,                        \
1663                 .can_dma        = dma,                          \
1664                 .can_isoc       = isoc,                         \
1665         }
1666
1667 static struct usba_ep_data at32_usba_ep[] __initdata = {
1668         EP("ep0",     0,   64, 1, 0, 0),
1669         EP("ep1",     1,  512, 2, 1, 1),
1670         EP("ep2",     2,  512, 2, 1, 1),
1671         EP("ep3-int", 3,   64, 3, 1, 0),
1672         EP("ep4-int", 4,   64, 3, 1, 0),
1673         EP("ep5",     5, 1024, 3, 1, 1),
1674         EP("ep6",     6, 1024, 3, 1, 1),
1675 };
1676
1677 #undef EP
1678
1679 struct platform_device *__init
1680 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1681 {
1682         /*
1683          * pdata doesn't have room for any endpoints, so we need to
1684          * append room for the ones we need right after it.
1685          */
1686         struct {
1687                 struct usba_platform_data pdata;
1688                 struct usba_ep_data ep[7];
1689         } usba_data;
1690         struct platform_device *pdev;
1691
1692         if (id != 0)
1693                 return NULL;
1694
1695         pdev = platform_device_alloc("atmel_usba_udc", 0);
1696         if (!pdev)
1697                 return NULL;
1698
1699         if (platform_device_add_resources(pdev, usba0_resource,
1700                                           ARRAY_SIZE(usba0_resource)))
1701                 goto out_free_pdev;
1702
1703         if (data)
1704                 usba_data.pdata.vbus_pin = data->vbus_pin;
1705         else
1706                 usba_data.pdata.vbus_pin = -EINVAL;
1707
1708         data = &usba_data.pdata;
1709         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1710         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1711
1712         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1713                 goto out_free_pdev;
1714
1715         if (data->vbus_pin >= 0)
1716                 at32_select_gpio(data->vbus_pin, 0);
1717
1718         usba0_pclk.dev = &pdev->dev;
1719         usba0_hclk.dev = &pdev->dev;
1720
1721         platform_device_add(pdev);
1722
1723         return pdev;
1724
1725 out_free_pdev:
1726         platform_device_put(pdev);
1727         return NULL;
1728 }
1729
1730 /* --------------------------------------------------------------------
1731  * IDE / CompactFlash
1732  * -------------------------------------------------------------------- */
1733 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1734 static struct resource at32_smc_cs4_resource[] __initdata = {
1735         {
1736                 .start  = 0x04000000,
1737                 .end    = 0x07ffffff,
1738                 .flags  = IORESOURCE_MEM,
1739         },
1740         IRQ(~0UL), /* Magic IRQ will be overridden */
1741 };
1742 static struct resource at32_smc_cs5_resource[] __initdata = {
1743         {
1744                 .start  = 0x20000000,
1745                 .end    = 0x23ffffff,
1746                 .flags  = IORESOURCE_MEM,
1747         },
1748         IRQ(~0UL), /* Magic IRQ will be overridden */
1749 };
1750
1751 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1752                 unsigned int cs, unsigned int extint)
1753 {
1754         static unsigned int extint_pin_map[4] __initdata = {
1755                 GPIO_PIN_PB(25),
1756                 GPIO_PIN_PB(26),
1757                 GPIO_PIN_PB(27),
1758                 GPIO_PIN_PB(28),
1759         };
1760         static bool common_pins_initialized __initdata = false;
1761         unsigned int extint_pin;
1762         int ret;
1763
1764         if (extint >= ARRAY_SIZE(extint_pin_map))
1765                 return -EINVAL;
1766         extint_pin = extint_pin_map[extint];
1767
1768         switch (cs) {
1769         case 4:
1770                 ret = platform_device_add_resources(pdev,
1771                                 at32_smc_cs4_resource,
1772                                 ARRAY_SIZE(at32_smc_cs4_resource));
1773                 if (ret)
1774                         return ret;
1775
1776                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1777                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1778                 break;
1779         case 5:
1780                 ret = platform_device_add_resources(pdev,
1781                                 at32_smc_cs5_resource,
1782                                 ARRAY_SIZE(at32_smc_cs5_resource));
1783                 if (ret)
1784                         return ret;
1785
1786                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1787                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1788                 break;
1789         default:
1790                 return -EINVAL;
1791         }
1792
1793         if (!common_pins_initialized) {
1794                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1795                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1796                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1797                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1798                 common_pins_initialized = true;
1799         }
1800
1801         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1802
1803         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1804         pdev->resource[1].end = pdev->resource[1].start;
1805
1806         return 0;
1807 }
1808
1809 struct platform_device *__init
1810 at32_add_device_ide(unsigned int id, unsigned int extint,
1811                     struct ide_platform_data *data)
1812 {
1813         struct platform_device *pdev;
1814
1815         pdev = platform_device_alloc("at32_ide", id);
1816         if (!pdev)
1817                 goto fail;
1818
1819         if (platform_device_add_data(pdev, data,
1820                                 sizeof(struct ide_platform_data)))
1821                 goto fail;
1822
1823         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1824                 goto fail;
1825
1826         platform_device_add(pdev);
1827         return pdev;
1828
1829 fail:
1830         platform_device_put(pdev);
1831         return NULL;
1832 }
1833
1834 struct platform_device *__init
1835 at32_add_device_cf(unsigned int id, unsigned int extint,
1836                     struct cf_platform_data *data)
1837 {
1838         struct platform_device *pdev;
1839
1840         pdev = platform_device_alloc("at32_cf", id);
1841         if (!pdev)
1842                 goto fail;
1843
1844         if (platform_device_add_data(pdev, data,
1845                                 sizeof(struct cf_platform_data)))
1846                 goto fail;
1847
1848         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1849                 goto fail;
1850
1851         if (gpio_is_valid(data->detect_pin))
1852                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1853         if (gpio_is_valid(data->reset_pin))
1854                 at32_select_gpio(data->reset_pin, 0);
1855         if (gpio_is_valid(data->vcc_pin))
1856                 at32_select_gpio(data->vcc_pin, 0);
1857         /* READY is used as extint, so we can't select it as gpio */
1858
1859         platform_device_add(pdev);
1860         return pdev;
1861
1862 fail:
1863         platform_device_put(pdev);
1864         return NULL;
1865 }
1866 #endif
1867
1868 /* --------------------------------------------------------------------
1869  * NAND Flash / SmartMedia
1870  * -------------------------------------------------------------------- */
1871 static struct resource smc_cs3_resource[] __initdata = {
1872         {
1873                 .start  = 0x0c000000,
1874                 .end    = 0x0fffffff,
1875                 .flags  = IORESOURCE_MEM,
1876         }, {
1877                 .start  = 0xfff03c00,
1878                 .end    = 0xfff03fff,
1879                 .flags  = IORESOURCE_MEM,
1880         },
1881 };
1882
1883 struct platform_device *__init
1884 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1885 {
1886         struct platform_device *pdev;
1887
1888         if (id != 0 || !data)
1889                 return NULL;
1890
1891         pdev = platform_device_alloc("atmel_nand", id);
1892         if (!pdev)
1893                 goto fail;
1894
1895         if (platform_device_add_resources(pdev, smc_cs3_resource,
1896                                 ARRAY_SIZE(smc_cs3_resource)))
1897                 goto fail;
1898
1899         if (platform_device_add_data(pdev, data,
1900                                 sizeof(struct atmel_nand_data)))
1901                 goto fail;
1902
1903         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1904         if (data->enable_pin)
1905                 at32_select_gpio(data->enable_pin,
1906                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1907         if (data->rdy_pin)
1908                 at32_select_gpio(data->rdy_pin, 0);
1909         if (data->det_pin)
1910                 at32_select_gpio(data->det_pin, 0);
1911
1912         platform_device_add(pdev);
1913         return pdev;
1914
1915 fail:
1916         platform_device_put(pdev);
1917         return NULL;
1918 }
1919
1920 /* --------------------------------------------------------------------
1921  * AC97C
1922  * -------------------------------------------------------------------- */
1923 static struct resource atmel_ac97c0_resource[] __initdata = {
1924         PBMEM(0xfff02800),
1925         IRQ(29),
1926 };
1927 static struct clk atmel_ac97c0_pclk = {
1928         .name           = "pclk",
1929         .parent         = &pbb_clk,
1930         .mode           = pbb_clk_mode,
1931         .get_rate       = pbb_clk_get_rate,
1932         .index          = 10,
1933 };
1934
1935 struct platform_device *__init
1936 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1937 {
1938         struct platform_device *pdev;
1939         struct ac97c_platform_data _data;
1940
1941         if (id != 0)
1942                 return NULL;
1943
1944         pdev = platform_device_alloc("atmel_ac97c", id);
1945         if (!pdev)
1946                 return NULL;
1947
1948         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1949                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1950                 goto fail;
1951
1952         if (!data) {
1953                 data = &_data;
1954                 memset(data, 0, sizeof(struct ac97c_platform_data));
1955                 data->reset_pin = GPIO_PIN_NONE;
1956         }
1957
1958         data->dma_rx_periph_id = 3;
1959         data->dma_tx_periph_id = 4;
1960         data->dma_controller_id = 0;
1961
1962         if (platform_device_add_data(pdev, data,
1963                                 sizeof(struct ac97c_platform_data)))
1964                 goto fail;
1965
1966         select_peripheral(PB(20), PERIPH_B, 0); /* SDO  */
1967         select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
1968         select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
1969         select_peripheral(PB(23), PERIPH_B, 0); /* SDI  */
1970
1971         /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
1972         if (data->reset_pin != GPIO_PIN_NONE)
1973                 at32_select_gpio(data->reset_pin, 0);
1974
1975         atmel_ac97c0_pclk.dev = &pdev->dev;
1976
1977         platform_device_add(pdev);
1978         return pdev;
1979
1980 fail:
1981         platform_device_put(pdev);
1982         return NULL;
1983 }
1984
1985 /* --------------------------------------------------------------------
1986  * ABDAC
1987  * -------------------------------------------------------------------- */
1988 static struct resource abdac0_resource[] __initdata = {
1989         PBMEM(0xfff02000),
1990         IRQ(27),
1991 };
1992 static struct clk abdac0_pclk = {
1993         .name           = "pclk",
1994         .parent         = &pbb_clk,
1995         .mode           = pbb_clk_mode,
1996         .get_rate       = pbb_clk_get_rate,
1997         .index          = 8,
1998 };
1999 static struct clk abdac0_sample_clk = {
2000         .name           = "sample_clk",
2001         .mode           = genclk_mode,
2002         .get_rate       = genclk_get_rate,
2003         .set_rate       = genclk_set_rate,
2004         .set_parent     = genclk_set_parent,
2005         .index          = 6,
2006 };
2007
2008 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2009 {
2010         struct platform_device *pdev;
2011
2012         if (id != 0)
2013                 return NULL;
2014
2015         pdev = platform_device_alloc("abdac", id);
2016         if (!pdev)
2017                 return NULL;
2018
2019         if (platform_device_add_resources(pdev, abdac0_resource,
2020                                 ARRAY_SIZE(abdac0_resource)))
2021                 goto err_add_resources;
2022
2023         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
2024         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
2025         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
2026         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
2027
2028         abdac0_pclk.dev = &pdev->dev;
2029         abdac0_sample_clk.dev = &pdev->dev;
2030
2031         platform_device_add(pdev);
2032         return pdev;
2033
2034 err_add_resources:
2035         platform_device_put(pdev);
2036         return NULL;
2037 }
2038
2039 /* --------------------------------------------------------------------
2040  *  GCLK
2041  * -------------------------------------------------------------------- */
2042 static struct clk gclk0 = {
2043         .name           = "gclk0",
2044         .mode           = genclk_mode,
2045         .get_rate       = genclk_get_rate,
2046         .set_rate       = genclk_set_rate,
2047         .set_parent     = genclk_set_parent,
2048         .index          = 0,
2049 };
2050 static struct clk gclk1 = {
2051         .name           = "gclk1",
2052         .mode           = genclk_mode,
2053         .get_rate       = genclk_get_rate,
2054         .set_rate       = genclk_set_rate,
2055         .set_parent     = genclk_set_parent,
2056         .index          = 1,
2057 };
2058 static struct clk gclk2 = {
2059         .name           = "gclk2",
2060         .mode           = genclk_mode,
2061         .get_rate       = genclk_get_rate,
2062         .set_rate       = genclk_set_rate,
2063         .set_parent     = genclk_set_parent,
2064         .index          = 2,
2065 };
2066 static struct clk gclk3 = {
2067         .name           = "gclk3",
2068         .mode           = genclk_mode,
2069         .get_rate       = genclk_get_rate,
2070         .set_rate       = genclk_set_rate,
2071         .set_parent     = genclk_set_parent,
2072         .index          = 3,
2073 };
2074 static struct clk gclk4 = {
2075         .name           = "gclk4",
2076         .mode           = genclk_mode,
2077         .get_rate       = genclk_get_rate,
2078         .set_rate       = genclk_set_rate,
2079         .set_parent     = genclk_set_parent,
2080         .index          = 4,
2081 };
2082
2083 static __initdata struct clk *init_clocks[] = {
2084         &osc32k,
2085         &osc0,
2086         &osc1,
2087         &pll0,
2088         &pll1,
2089         &cpu_clk,
2090         &hsb_clk,
2091         &pba_clk,
2092         &pbb_clk,
2093         &at32_pm_pclk,
2094         &at32_intc0_pclk,
2095         &at32_hmatrix_clk,
2096         &ebi_clk,
2097         &hramc_clk,
2098         &sdramc_clk,
2099         &smc0_pclk,
2100         &smc0_mck,
2101         &pdc_hclk,
2102         &pdc_pclk,
2103         &dw_dmac0_hclk,
2104         &pico_clk,
2105         &pio0_mck,
2106         &pio1_mck,
2107         &pio2_mck,
2108         &pio3_mck,
2109         &pio4_mck,
2110         &at32_tcb0_t0_clk,
2111         &at32_tcb1_t0_clk,
2112         &atmel_psif0_pclk,
2113         &atmel_psif1_pclk,
2114         &atmel_usart0_usart,
2115         &atmel_usart1_usart,
2116         &atmel_usart2_usart,
2117         &atmel_usart3_usart,
2118         &atmel_pwm0_mck,
2119 #if defined(CONFIG_CPU_AT32AP7000)
2120         &macb0_hclk,
2121         &macb0_pclk,
2122         &macb1_hclk,
2123         &macb1_pclk,
2124 #endif
2125         &atmel_spi0_spi_clk,
2126         &atmel_spi1_spi_clk,
2127         &atmel_twi0_pclk,
2128         &atmel_mci0_pclk,
2129 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2130         &atmel_lcdfb0_hck1,
2131         &atmel_lcdfb0_pixclk,
2132 #endif
2133         &ssc0_pclk,
2134         &ssc1_pclk,
2135         &ssc2_pclk,
2136         &usba0_hclk,
2137         &usba0_pclk,
2138         &atmel_ac97c0_pclk,
2139         &abdac0_pclk,
2140         &abdac0_sample_clk,
2141         &gclk0,
2142         &gclk1,
2143         &gclk2,
2144         &gclk3,
2145         &gclk4,
2146 };
2147
2148 void __init setup_platform(void)
2149 {
2150         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2151         int i;
2152
2153         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2154                 main_clock = &pll0;
2155                 cpu_clk.parent = &pll0;
2156         } else {
2157                 main_clock = &osc0;
2158                 cpu_clk.parent = &osc0;
2159         }
2160
2161         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2162                 pll0.parent = &osc1;
2163         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2164                 pll1.parent = &osc1;
2165
2166         genclk_init_parent(&gclk0);
2167         genclk_init_parent(&gclk1);
2168         genclk_init_parent(&gclk2);
2169         genclk_init_parent(&gclk3);
2170         genclk_init_parent(&gclk4);
2171 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2172         genclk_init_parent(&atmel_lcdfb0_pixclk);
2173 #endif
2174         genclk_init_parent(&abdac0_sample_clk);
2175
2176         /*
2177          * Build initial dynamic clock list by registering all clocks
2178          * from the array.
2179          * At the same time, turn on all clocks that have at least one
2180          * user already, and turn off everything else. We only do this
2181          * for module clocks, and even though it isn't particularly
2182          * pretty to  check the address of the mode function, it should
2183          * do the trick...
2184          */
2185         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2186                 struct clk *clk = init_clocks[i];
2187
2188                 /* first, register clock */
2189                 at32_clk_register(clk);
2190
2191                 if (clk->users == 0)
2192                         continue;
2193
2194                 if (clk->mode == &cpu_clk_mode)
2195                         cpu_mask |= 1 << clk->index;
2196                 else if (clk->mode == &hsb_clk_mode)
2197                         hsb_mask |= 1 << clk->index;
2198                 else if (clk->mode == &pba_clk_mode)
2199                         pba_mask |= 1 << clk->index;
2200                 else if (clk->mode == &pbb_clk_mode)
2201                         pbb_mask |= 1 << clk->index;
2202         }
2203
2204         pm_writel(CPU_MASK, cpu_mask);
2205         pm_writel(HSB_MASK, hsb_mask);
2206         pm_writel(PBA_MASK, pba_mask);
2207         pm_writel(PBB_MASK, pbb_mask);
2208
2209         /* Initialize the port muxes */
2210         at32_init_pio(&pio0_device);
2211         at32_init_pio(&pio1_device);
2212         at32_init_pio(&pio2_device);
2213         at32_init_pio(&pio3_device);
2214         at32_init_pio(&pio4_device);
2215 }
2216
2217 struct gen_pool *sram_pool;
2218
2219 static int __init sram_init(void)
2220 {
2221         struct gen_pool *pool;
2222
2223         /* 1KiB granularity */
2224         pool = gen_pool_create(10, -1);
2225         if (!pool)
2226                 goto fail;
2227
2228         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2229                 goto err_pool_add;
2230
2231         sram_pool = pool;
2232         return 0;
2233
2234 err_pool_add:
2235         gen_pool_destroy(pool);
2236 fail:
2237         pr_err("Failed to create SRAM pool\n");
2238         return -ENOMEM;
2239 }
2240 core_initcall(sram_init);