[AVR32] Use per-controller spi_board_info structures
[linux-2.6.git] / arch / avr32 / mach-at32ap / at32ap7000.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/spi/spi.h>
12
13 #include <asm/io.h>
14
15 #include <asm/arch/at32ap7000.h>
16 #include <asm/arch/board.h>
17 #include <asm/arch/portmux.h>
18 #include <asm/arch/sm.h>
19
20 #include "clock.h"
21 #include "pio.h"
22 #include "sm.h"
23
24 #define PBMEM(base)                                     \
25         {                                               \
26                 .start          = base,                 \
27                 .end            = base + 0x3ff,         \
28                 .flags          = IORESOURCE_MEM,       \
29         }
30 #define IRQ(num)                                        \
31         {                                               \
32                 .start          = num,                  \
33                 .end            = num,                  \
34                 .flags          = IORESOURCE_IRQ,       \
35         }
36 #define NAMED_IRQ(num, _name)                           \
37         {                                               \
38                 .start          = num,                  \
39                 .end            = num,                  \
40                 .name           = _name,                \
41                 .flags          = IORESOURCE_IRQ,       \
42         }
43
44 #define DEFINE_DEV(_name, _id)                                  \
45 static struct platform_device _name##_id##_device = {           \
46         .name           = #_name,                               \
47         .id             = _id,                                  \
48         .resource       = _name##_id##_resource,                \
49         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
50 }
51 #define DEFINE_DEV_DATA(_name, _id)                             \
52 static struct platform_device _name##_id##_device = {           \
53         .name           = #_name,                               \
54         .id             = _id,                                  \
55         .dev            = {                                     \
56                 .platform_data  = &_name##_id##_data,           \
57         },                                                      \
58         .resource       = _name##_id##_resource,                \
59         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
60 }
61
62 #define select_peripheral(pin, periph, flags)                   \
63         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
64
65 #define DEV_CLK(_name, devname, bus, _index)                    \
66 static struct clk devname##_##_name = {                         \
67         .name           = #_name,                               \
68         .dev            = &devname##_device.dev,                \
69         .parent         = &bus##_clk,                           \
70         .mode           = bus##_clk_mode,                       \
71         .get_rate       = bus##_clk_get_rate,                   \
72         .index          = _index,                               \
73 }
74
75 unsigned long at32ap7000_osc_rates[3] = {
76         [0] = 32768,
77         /* FIXME: these are ATSTK1002-specific */
78         [1] = 20000000,
79         [2] = 12000000,
80 };
81
82 static unsigned long osc_get_rate(struct clk *clk)
83 {
84         return at32ap7000_osc_rates[clk->index];
85 }
86
87 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
88 {
89         unsigned long div, mul, rate;
90
91         if (!(control & SM_BIT(PLLEN)))
92                 return 0;
93
94         div = SM_BFEXT(PLLDIV, control) + 1;
95         mul = SM_BFEXT(PLLMUL, control) + 1;
96
97         rate = clk->parent->get_rate(clk->parent);
98         rate = (rate + div / 2) / div;
99         rate *= mul;
100
101         return rate;
102 }
103
104 static unsigned long pll0_get_rate(struct clk *clk)
105 {
106         u32 control;
107
108         control = sm_readl(&system_manager, PM_PLL0);
109
110         return pll_get_rate(clk, control);
111 }
112
113 static unsigned long pll1_get_rate(struct clk *clk)
114 {
115         u32 control;
116
117         control = sm_readl(&system_manager, PM_PLL1);
118
119         return pll_get_rate(clk, control);
120 }
121
122 /*
123  * The AT32AP7000 has five primary clock sources: One 32kHz
124  * oscillator, two crystal oscillators and two PLLs.
125  */
126 static struct clk osc32k = {
127         .name           = "osc32k",
128         .get_rate       = osc_get_rate,
129         .users          = 1,
130         .index          = 0,
131 };
132 static struct clk osc0 = {
133         .name           = "osc0",
134         .get_rate       = osc_get_rate,
135         .users          = 1,
136         .index          = 1,
137 };
138 static struct clk osc1 = {
139         .name           = "osc1",
140         .get_rate       = osc_get_rate,
141         .index          = 2,
142 };
143 static struct clk pll0 = {
144         .name           = "pll0",
145         .get_rate       = pll0_get_rate,
146         .parent         = &osc0,
147 };
148 static struct clk pll1 = {
149         .name           = "pll1",
150         .get_rate       = pll1_get_rate,
151         .parent         = &osc0,
152 };
153
154 /*
155  * The main clock can be either osc0 or pll0.  The boot loader may
156  * have chosen one for us, so we don't really know which one until we
157  * have a look at the SM.
158  */
159 static struct clk *main_clock;
160
161 /*
162  * Synchronous clocks are generated from the main clock. The clocks
163  * must satisfy the constraint
164  *   fCPU >= fHSB >= fPB
165  * i.e. each clock must not be faster than its parent.
166  */
167 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
168 {
169         return main_clock->get_rate(main_clock) >> shift;
170 };
171
172 static void cpu_clk_mode(struct clk *clk, int enabled)
173 {
174         struct at32_sm *sm = &system_manager;
175         unsigned long flags;
176         u32 mask;
177
178         spin_lock_irqsave(&sm->lock, flags);
179         mask = sm_readl(sm, PM_CPU_MASK);
180         if (enabled)
181                 mask |= 1 << clk->index;
182         else
183                 mask &= ~(1 << clk->index);
184         sm_writel(sm, PM_CPU_MASK, mask);
185         spin_unlock_irqrestore(&sm->lock, flags);
186 }
187
188 static unsigned long cpu_clk_get_rate(struct clk *clk)
189 {
190         unsigned long cksel, shift = 0;
191
192         cksel = sm_readl(&system_manager, PM_CKSEL);
193         if (cksel & SM_BIT(CPUDIV))
194                 shift = SM_BFEXT(CPUSEL, cksel) + 1;
195
196         return bus_clk_get_rate(clk, shift);
197 }
198
199 static void hsb_clk_mode(struct clk *clk, int enabled)
200 {
201         struct at32_sm *sm = &system_manager;
202         unsigned long flags;
203         u32 mask;
204
205         spin_lock_irqsave(&sm->lock, flags);
206         mask = sm_readl(sm, PM_HSB_MASK);
207         if (enabled)
208                 mask |= 1 << clk->index;
209         else
210                 mask &= ~(1 << clk->index);
211         sm_writel(sm, PM_HSB_MASK, mask);
212         spin_unlock_irqrestore(&sm->lock, flags);
213 }
214
215 static unsigned long hsb_clk_get_rate(struct clk *clk)
216 {
217         unsigned long cksel, shift = 0;
218
219         cksel = sm_readl(&system_manager, PM_CKSEL);
220         if (cksel & SM_BIT(HSBDIV))
221                 shift = SM_BFEXT(HSBSEL, cksel) + 1;
222
223         return bus_clk_get_rate(clk, shift);
224 }
225
226 static void pba_clk_mode(struct clk *clk, int enabled)
227 {
228         struct at32_sm *sm = &system_manager;
229         unsigned long flags;
230         u32 mask;
231
232         spin_lock_irqsave(&sm->lock, flags);
233         mask = sm_readl(sm, PM_PBA_MASK);
234         if (enabled)
235                 mask |= 1 << clk->index;
236         else
237                 mask &= ~(1 << clk->index);
238         sm_writel(sm, PM_PBA_MASK, mask);
239         spin_unlock_irqrestore(&sm->lock, flags);
240 }
241
242 static unsigned long pba_clk_get_rate(struct clk *clk)
243 {
244         unsigned long cksel, shift = 0;
245
246         cksel = sm_readl(&system_manager, PM_CKSEL);
247         if (cksel & SM_BIT(PBADIV))
248                 shift = SM_BFEXT(PBASEL, cksel) + 1;
249
250         return bus_clk_get_rate(clk, shift);
251 }
252
253 static void pbb_clk_mode(struct clk *clk, int enabled)
254 {
255         struct at32_sm *sm = &system_manager;
256         unsigned long flags;
257         u32 mask;
258
259         spin_lock_irqsave(&sm->lock, flags);
260         mask = sm_readl(sm, PM_PBB_MASK);
261         if (enabled)
262                 mask |= 1 << clk->index;
263         else
264                 mask &= ~(1 << clk->index);
265         sm_writel(sm, PM_PBB_MASK, mask);
266         spin_unlock_irqrestore(&sm->lock, flags);
267 }
268
269 static unsigned long pbb_clk_get_rate(struct clk *clk)
270 {
271         unsigned long cksel, shift = 0;
272
273         cksel = sm_readl(&system_manager, PM_CKSEL);
274         if (cksel & SM_BIT(PBBDIV))
275                 shift = SM_BFEXT(PBBSEL, cksel) + 1;
276
277         return bus_clk_get_rate(clk, shift);
278 }
279
280 static struct clk cpu_clk = {
281         .name           = "cpu",
282         .get_rate       = cpu_clk_get_rate,
283         .users          = 1,
284 };
285 static struct clk hsb_clk = {
286         .name           = "hsb",
287         .parent         = &cpu_clk,
288         .get_rate       = hsb_clk_get_rate,
289 };
290 static struct clk pba_clk = {
291         .name           = "pba",
292         .parent         = &hsb_clk,
293         .mode           = hsb_clk_mode,
294         .get_rate       = pba_clk_get_rate,
295         .index          = 1,
296 };
297 static struct clk pbb_clk = {
298         .name           = "pbb",
299         .parent         = &hsb_clk,
300         .mode           = hsb_clk_mode,
301         .get_rate       = pbb_clk_get_rate,
302         .users          = 1,
303         .index          = 2,
304 };
305
306 /* --------------------------------------------------------------------
307  *  Generic Clock operations
308  * -------------------------------------------------------------------- */
309
310 static void genclk_mode(struct clk *clk, int enabled)
311 {
312         u32 control;
313
314         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
315         if (enabled)
316                 control |= SM_BIT(CEN);
317         else
318                 control &= ~SM_BIT(CEN);
319         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
320 }
321
322 static unsigned long genclk_get_rate(struct clk *clk)
323 {
324         u32 control;
325         unsigned long div = 1;
326
327         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
328         if (control & SM_BIT(DIVEN))
329                 div = 2 * (SM_BFEXT(DIV, control) + 1);
330
331         return clk->parent->get_rate(clk->parent) / div;
332 }
333
334 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
335 {
336         u32 control;
337         unsigned long parent_rate, actual_rate, div;
338
339         parent_rate = clk->parent->get_rate(clk->parent);
340         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
341
342         if (rate > 3 * parent_rate / 4) {
343                 actual_rate = parent_rate;
344                 control &= ~SM_BIT(DIVEN);
345         } else {
346                 div = (parent_rate + rate) / (2 * rate) - 1;
347                 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
348                 actual_rate = parent_rate / (2 * (div + 1));
349         }
350
351         printk("clk %s: new rate %lu (actual rate %lu)\n",
352                clk->name, rate, actual_rate);
353
354         if (apply)
355                 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
356                           control);
357
358         return actual_rate;
359 }
360
361 int genclk_set_parent(struct clk *clk, struct clk *parent)
362 {
363         u32 control;
364
365         printk("clk %s: new parent %s (was %s)\n",
366                clk->name, parent->name, clk->parent->name);
367
368         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
369
370         if (parent == &osc1 || parent == &pll1)
371                 control |= SM_BIT(OSCSEL);
372         else if (parent == &osc0 || parent == &pll0)
373                 control &= ~SM_BIT(OSCSEL);
374         else
375                 return -EINVAL;
376
377         if (parent == &pll0 || parent == &pll1)
378                 control |= SM_BIT(PLLSEL);
379         else
380                 control &= ~SM_BIT(PLLSEL);
381
382         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
383         clk->parent = parent;
384
385         return 0;
386 }
387
388 static void __init genclk_init_parent(struct clk *clk)
389 {
390         u32 control;
391         struct clk *parent;
392
393         BUG_ON(clk->index > 7);
394
395         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
396         if (control & SM_BIT(OSCSEL))
397                 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
398         else
399                 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
400
401         clk->parent = parent;
402 }
403
404 /* --------------------------------------------------------------------
405  *  System peripherals
406  * -------------------------------------------------------------------- */
407 static struct resource sm_resource[] = {
408         PBMEM(0xfff00000),
409         NAMED_IRQ(19, "eim"),
410         NAMED_IRQ(20, "pm"),
411         NAMED_IRQ(21, "rtc"),
412 };
413 struct platform_device at32_sm_device = {
414         .name           = "sm",
415         .id             = 0,
416         .resource       = sm_resource,
417         .num_resources  = ARRAY_SIZE(sm_resource),
418 };
419 DEV_CLK(pclk, at32_sm, pbb, 0);
420
421 static struct resource intc0_resource[] = {
422         PBMEM(0xfff00400),
423 };
424 struct platform_device at32_intc0_device = {
425         .name           = "intc",
426         .id             = 0,
427         .resource       = intc0_resource,
428         .num_resources  = ARRAY_SIZE(intc0_resource),
429 };
430 DEV_CLK(pclk, at32_intc0, pbb, 1);
431
432 static struct clk ebi_clk = {
433         .name           = "ebi",
434         .parent         = &hsb_clk,
435         .mode           = hsb_clk_mode,
436         .get_rate       = hsb_clk_get_rate,
437         .users          = 1,
438 };
439 static struct clk hramc_clk = {
440         .name           = "hramc",
441         .parent         = &hsb_clk,
442         .mode           = hsb_clk_mode,
443         .get_rate       = hsb_clk_get_rate,
444         .users          = 1,
445 };
446
447 static struct resource smc0_resource[] = {
448         PBMEM(0xfff03400),
449 };
450 DEFINE_DEV(smc, 0);
451 DEV_CLK(pclk, smc0, pbb, 13);
452 DEV_CLK(mck, smc0, hsb, 0);
453
454 static struct platform_device pdc_device = {
455         .name           = "pdc",
456         .id             = 0,
457 };
458 DEV_CLK(hclk, pdc, hsb, 4);
459 DEV_CLK(pclk, pdc, pba, 16);
460
461 static struct clk pico_clk = {
462         .name           = "pico",
463         .parent         = &cpu_clk,
464         .mode           = cpu_clk_mode,
465         .get_rate       = cpu_clk_get_rate,
466         .users          = 1,
467 };
468
469 /* --------------------------------------------------------------------
470  *  PIO
471  * -------------------------------------------------------------------- */
472
473 static struct resource pio0_resource[] = {
474         PBMEM(0xffe02800),
475         IRQ(13),
476 };
477 DEFINE_DEV(pio, 0);
478 DEV_CLK(mck, pio0, pba, 10);
479
480 static struct resource pio1_resource[] = {
481         PBMEM(0xffe02c00),
482         IRQ(14),
483 };
484 DEFINE_DEV(pio, 1);
485 DEV_CLK(mck, pio1, pba, 11);
486
487 static struct resource pio2_resource[] = {
488         PBMEM(0xffe03000),
489         IRQ(15),
490 };
491 DEFINE_DEV(pio, 2);
492 DEV_CLK(mck, pio2, pba, 12);
493
494 static struct resource pio3_resource[] = {
495         PBMEM(0xffe03400),
496         IRQ(16),
497 };
498 DEFINE_DEV(pio, 3);
499 DEV_CLK(mck, pio3, pba, 13);
500
501 static struct resource pio4_resource[] = {
502         PBMEM(0xffe03800),
503         IRQ(17),
504 };
505 DEFINE_DEV(pio, 4);
506 DEV_CLK(mck, pio4, pba, 14);
507
508 void __init at32_add_system_devices(void)
509 {
510         system_manager.eim_first_irq = EIM_IRQ_BASE;
511
512         platform_device_register(&at32_sm_device);
513         platform_device_register(&at32_intc0_device);
514         platform_device_register(&smc0_device);
515         platform_device_register(&pdc_device);
516
517         platform_device_register(&pio0_device);
518         platform_device_register(&pio1_device);
519         platform_device_register(&pio2_device);
520         platform_device_register(&pio3_device);
521         platform_device_register(&pio4_device);
522 }
523
524 /* --------------------------------------------------------------------
525  *  USART
526  * -------------------------------------------------------------------- */
527
528 static struct atmel_uart_data atmel_usart0_data = {
529         .use_dma_tx     = 1,
530         .use_dma_rx     = 1,
531 };
532 static struct resource atmel_usart0_resource[] = {
533         PBMEM(0xffe00c00),
534         IRQ(6),
535 };
536 DEFINE_DEV_DATA(atmel_usart, 0);
537 DEV_CLK(usart, atmel_usart0, pba, 4);
538
539 static struct atmel_uart_data atmel_usart1_data = {
540         .use_dma_tx     = 1,
541         .use_dma_rx     = 1,
542 };
543 static struct resource atmel_usart1_resource[] = {
544         PBMEM(0xffe01000),
545         IRQ(7),
546 };
547 DEFINE_DEV_DATA(atmel_usart, 1);
548 DEV_CLK(usart, atmel_usart1, pba, 4);
549
550 static struct atmel_uart_data atmel_usart2_data = {
551         .use_dma_tx     = 1,
552         .use_dma_rx     = 1,
553 };
554 static struct resource atmel_usart2_resource[] = {
555         PBMEM(0xffe01400),
556         IRQ(8),
557 };
558 DEFINE_DEV_DATA(atmel_usart, 2);
559 DEV_CLK(usart, atmel_usart2, pba, 5);
560
561 static struct atmel_uart_data atmel_usart3_data = {
562         .use_dma_tx     = 1,
563         .use_dma_rx     = 1,
564 };
565 static struct resource atmel_usart3_resource[] = {
566         PBMEM(0xffe01800),
567         IRQ(9),
568 };
569 DEFINE_DEV_DATA(atmel_usart, 3);
570 DEV_CLK(usart, atmel_usart3, pba, 6);
571
572 static inline void configure_usart0_pins(void)
573 {
574         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
575         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
576 }
577
578 static inline void configure_usart1_pins(void)
579 {
580         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
581         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
582 }
583
584 static inline void configure_usart2_pins(void)
585 {
586         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
587         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
588 }
589
590 static inline void configure_usart3_pins(void)
591 {
592         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
593         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
594 }
595
596 static struct platform_device *__initdata at32_usarts[4];
597
598 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
599 {
600         struct platform_device *pdev;
601
602         switch (hw_id) {
603         case 0:
604                 pdev = &atmel_usart0_device;
605                 configure_usart0_pins();
606                 break;
607         case 1:
608                 pdev = &atmel_usart1_device;
609                 configure_usart1_pins();
610                 break;
611         case 2:
612                 pdev = &atmel_usart2_device;
613                 configure_usart2_pins();
614                 break;
615         case 3:
616                 pdev = &atmel_usart3_device;
617                 configure_usart3_pins();
618                 break;
619         default:
620                 return;
621         }
622
623         if (PXSEG(pdev->resource[0].start) == P4SEG) {
624                 /* Addresses in the P4 segment are permanently mapped 1:1 */
625                 struct atmel_uart_data *data = pdev->dev.platform_data;
626                 data->regs = (void __iomem *)pdev->resource[0].start;
627         }
628
629         pdev->id = line;
630         at32_usarts[line] = pdev;
631 }
632
633 struct platform_device *__init at32_add_device_usart(unsigned int id)
634 {
635         platform_device_register(at32_usarts[id]);
636         return at32_usarts[id];
637 }
638
639 struct platform_device *atmel_default_console_device;
640
641 void __init at32_setup_serial_console(unsigned int usart_id)
642 {
643         atmel_default_console_device = at32_usarts[usart_id];
644 }
645
646 /* --------------------------------------------------------------------
647  *  Ethernet
648  * -------------------------------------------------------------------- */
649
650 static struct eth_platform_data macb0_data;
651 static struct resource macb0_resource[] = {
652         PBMEM(0xfff01800),
653         IRQ(25),
654 };
655 DEFINE_DEV_DATA(macb, 0);
656 DEV_CLK(hclk, macb0, hsb, 8);
657 DEV_CLK(pclk, macb0, pbb, 6);
658
659 static struct eth_platform_data macb1_data;
660 static struct resource macb1_resource[] = {
661         PBMEM(0xfff01c00),
662         IRQ(26),
663 };
664 DEFINE_DEV_DATA(macb, 1);
665 DEV_CLK(hclk, macb1, hsb, 9);
666 DEV_CLK(pclk, macb1, pbb, 7);
667
668 struct platform_device *__init
669 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
670 {
671         struct platform_device *pdev;
672
673         switch (id) {
674         case 0:
675                 pdev = &macb0_device;
676
677                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
678                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
679                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
680                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
681                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
682                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
683                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
684                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
685                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
686                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
687
688                 if (!data->is_rmii) {
689                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
690                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
691                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
692                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
693                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
694                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
695                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
696                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
697                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
698                 }
699                 break;
700
701         case 1:
702                 pdev = &macb1_device;
703
704                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
705                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
706                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
707                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
708                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
709                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
710                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
711                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
712                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
713                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
714
715                 if (!data->is_rmii) {
716                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
717                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
718                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
719                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
720                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
721                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
722                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
723                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
724                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
725                 }
726                 break;
727
728         default:
729                 return NULL;
730         }
731
732         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
733         platform_device_register(pdev);
734
735         return pdev;
736 }
737
738 /* --------------------------------------------------------------------
739  *  SPI
740  * -------------------------------------------------------------------- */
741 static struct resource atmel_spi0_resource[] = {
742         PBMEM(0xffe00000),
743         IRQ(3),
744 };
745 DEFINE_DEV(atmel_spi, 0);
746 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
747
748 static struct resource atmel_spi1_resource[] = {
749         PBMEM(0xffe00400),
750         IRQ(4),
751 };
752 DEFINE_DEV(atmel_spi, 1);
753 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
754
755 static void
756 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
757                       unsigned int n, const u8 *pins)
758 {
759         unsigned int pin, mode;
760
761         for (; n; n--, b++) {
762                 b->bus_num = bus_num;
763                 if (b->chip_select >= 4)
764                         continue;
765                 pin = (unsigned)b->controller_data;
766                 if (!pin) {
767                         pin = pins[b->chip_select];
768                         b->controller_data = (void *)pin;
769                 }
770                 mode = AT32_GPIOF_OUTPUT;
771                 if (!(b->mode & SPI_CS_HIGH))
772                         mode |= AT32_GPIOF_HIGH;
773                 at32_select_gpio(pin, mode);
774         }
775 }
776
777 struct platform_device *__init
778 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
779 {
780         /*
781          * Manage the chipselects as GPIOs, normally using the same pins
782          * the SPI controller expects; but boards can use other pins.
783          */
784         static u8 __initdata spi0_pins[] =
785                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
786                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
787         static u8 __initdata spi1_pins[] =
788                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
789                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
790         struct platform_device *pdev;
791
792         switch (id) {
793         case 0:
794                 pdev = &atmel_spi0_device;
795                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
796                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
797                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
798                 at32_spi_setup_slaves(0, b, n, spi0_pins);
799                 break;
800
801         case 1:
802                 pdev = &atmel_spi1_device;
803                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
804                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
805                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
806                 at32_spi_setup_slaves(1, b, n, spi1_pins);
807                 break;
808
809         default:
810                 return NULL;
811         }
812
813         spi_register_board_info(b, n);
814         platform_device_register(pdev);
815         return pdev;
816 }
817
818 /* --------------------------------------------------------------------
819  *  LCDC
820  * -------------------------------------------------------------------- */
821 static struct lcdc_platform_data lcdc0_data;
822 static struct resource lcdc0_resource[] = {
823         {
824                 .start          = 0xff000000,
825                 .end            = 0xff000fff,
826                 .flags          = IORESOURCE_MEM,
827         },
828         IRQ(1),
829 };
830 DEFINE_DEV_DATA(lcdc, 0);
831 DEV_CLK(hclk, lcdc0, hsb, 7);
832 static struct clk lcdc0_pixclk = {
833         .name           = "pixclk",
834         .dev            = &lcdc0_device.dev,
835         .mode           = genclk_mode,
836         .get_rate       = genclk_get_rate,
837         .set_rate       = genclk_set_rate,
838         .set_parent     = genclk_set_parent,
839         .index          = 7,
840 };
841
842 struct platform_device *__init
843 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
844 {
845         struct platform_device *pdev;
846
847         switch (id) {
848         case 0:
849                 pdev = &lcdc0_device;
850                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
851                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
852                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
853                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
854                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
855                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
856                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
857                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
858                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
859                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
860                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
861                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
862                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
863                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
864                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
865                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
866                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
867                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
868                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
869                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
870                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
871                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
872                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
873                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
874                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
875                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
876                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
877                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
878                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
879                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
880                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
881
882                 clk_set_parent(&lcdc0_pixclk, &pll0);
883                 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
884                 break;
885
886         default:
887                 return NULL;
888         }
889
890         memcpy(pdev->dev.platform_data, data,
891                sizeof(struct lcdc_platform_data));
892
893         platform_device_register(pdev);
894         return pdev;
895 }
896
897 /* --------------------------------------------------------------------
898  *  GCLK
899  * -------------------------------------------------------------------- */
900 static struct clk gclk0 = {
901         .name           = "gclk0",
902         .mode           = genclk_mode,
903         .get_rate       = genclk_get_rate,
904         .set_rate       = genclk_set_rate,
905         .set_parent     = genclk_set_parent,
906         .index          = 0,
907 };
908 static struct clk gclk1 = {
909         .name           = "gclk1",
910         .mode           = genclk_mode,
911         .get_rate       = genclk_get_rate,
912         .set_rate       = genclk_set_rate,
913         .set_parent     = genclk_set_parent,
914         .index          = 1,
915 };
916 static struct clk gclk2 = {
917         .name           = "gclk2",
918         .mode           = genclk_mode,
919         .get_rate       = genclk_get_rate,
920         .set_rate       = genclk_set_rate,
921         .set_parent     = genclk_set_parent,
922         .index          = 2,
923 };
924 static struct clk gclk3 = {
925         .name           = "gclk3",
926         .mode           = genclk_mode,
927         .get_rate       = genclk_get_rate,
928         .set_rate       = genclk_set_rate,
929         .set_parent     = genclk_set_parent,
930         .index          = 3,
931 };
932 static struct clk gclk4 = {
933         .name           = "gclk4",
934         .mode           = genclk_mode,
935         .get_rate       = genclk_get_rate,
936         .set_rate       = genclk_set_rate,
937         .set_parent     = genclk_set_parent,
938         .index          = 4,
939 };
940
941 struct clk *at32_clock_list[] = {
942         &osc32k,
943         &osc0,
944         &osc1,
945         &pll0,
946         &pll1,
947         &cpu_clk,
948         &hsb_clk,
949         &pba_clk,
950         &pbb_clk,
951         &at32_sm_pclk,
952         &at32_intc0_pclk,
953         &ebi_clk,
954         &hramc_clk,
955         &smc0_pclk,
956         &smc0_mck,
957         &pdc_hclk,
958         &pdc_pclk,
959         &pico_clk,
960         &pio0_mck,
961         &pio1_mck,
962         &pio2_mck,
963         &pio3_mck,
964         &pio4_mck,
965         &atmel_usart0_usart,
966         &atmel_usart1_usart,
967         &atmel_usart2_usart,
968         &atmel_usart3_usart,
969         &macb0_hclk,
970         &macb0_pclk,
971         &macb1_hclk,
972         &macb1_pclk,
973         &atmel_spi0_spi_clk,
974         &atmel_spi1_spi_clk,
975         &lcdc0_hclk,
976         &lcdc0_pixclk,
977         &gclk0,
978         &gclk1,
979         &gclk2,
980         &gclk3,
981         &gclk4,
982 };
983 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
984
985 void __init at32_portmux_init(void)
986 {
987         at32_init_pio(&pio0_device);
988         at32_init_pio(&pio1_device);
989         at32_init_pio(&pio2_device);
990         at32_init_pio(&pio3_device);
991         at32_init_pio(&pio4_device);
992 }
993
994 void __init at32_clock_init(void)
995 {
996         struct at32_sm *sm = &system_manager;
997         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
998         int i;
999
1000         if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1001                 main_clock = &pll0;
1002         else
1003                 main_clock = &osc0;
1004
1005         if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1006                 pll0.parent = &osc1;
1007         if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1008                 pll1.parent = &osc1;
1009
1010         genclk_init_parent(&gclk0);
1011         genclk_init_parent(&gclk1);
1012         genclk_init_parent(&gclk2);
1013         genclk_init_parent(&gclk3);
1014         genclk_init_parent(&gclk4);
1015         genclk_init_parent(&lcdc0_pixclk);
1016
1017         /*
1018          * Turn on all clocks that have at least one user already, and
1019          * turn off everything else. We only do this for module
1020          * clocks, and even though it isn't particularly pretty to
1021          * check the address of the mode function, it should do the
1022          * trick...
1023          */
1024         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1025                 struct clk *clk = at32_clock_list[i];
1026
1027                 if (clk->mode == &cpu_clk_mode)
1028                         cpu_mask |= 1 << clk->index;
1029                 else if (clk->mode == &hsb_clk_mode)
1030                         hsb_mask |= 1 << clk->index;
1031                 else if (clk->mode == &pba_clk_mode)
1032                         pba_mask |= 1 << clk->index;
1033                 else if (clk->mode == &pbb_clk_mode)
1034                         pbb_mask |= 1 << clk->index;
1035         }
1036
1037         sm_writel(sm, PM_CPU_MASK, cpu_mask);
1038         sm_writel(sm, PM_HSB_MASK, hsb_mask);
1039         sm_writel(sm, PM_PBA_MASK, pba_mask);
1040         sm_writel(sm, PM_PBB_MASK, pbb_mask);
1041 }