Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm...
[linux-2.6.git] / arch / arm / plat-s3c24xx / cpu.c
1 /* linux/arch/arm/plat-s3c24xx/cpu.c
2  *
3  * Copyright (c) 2004-2005 Simtec Electronics
4  *      http://www.simtec.co.uk/products/SWLINUX/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * S3C24XX CPU Support
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22 */
23
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/io.h>
33
34 #include <mach/hardware.h>
35 #include <mach/regs-clock.h>
36 #include <asm/irq.h>
37 #include <asm/cacheflush.h>
38 #include <asm/system_info.h>
39
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42
43 #include <mach/regs-gpio.h>
44 #include <plat/regs-serial.h>
45
46 #include <plat/cpu.h>
47 #include <plat/devs.h>
48 #include <plat/clock.h>
49 #include <plat/s3c2410.h>
50 #include <plat/s3c2412.h>
51 #include <plat/s3c2416.h>
52 #include <plat/s3c244x.h>
53 #include <plat/s3c2443.h>
54
55 /* table of supported CPUs */
56
57 static const char name_s3c2410[]  = "S3C2410";
58 static const char name_s3c2412[]  = "S3C2412";
59 static const char name_s3c2416[]  = "S3C2416/S3C2450";
60 static const char name_s3c2440[]  = "S3C2440";
61 static const char name_s3c2442[]  = "S3C2442";
62 static const char name_s3c2442b[]  = "S3C2442B";
63 static const char name_s3c2443[]  = "S3C2443";
64 static const char name_s3c2410a[] = "S3C2410A";
65 static const char name_s3c2440a[] = "S3C2440A";
66
67 static struct cpu_table cpu_ids[] __initdata = {
68         {
69                 .idcode         = 0x32410000,
70                 .idmask         = 0xffffffff,
71                 .map_io         = s3c2410_map_io,
72                 .init_clocks    = s3c2410_init_clocks,
73                 .init_uarts     = s3c2410_init_uarts,
74                 .init           = s3c2410_init,
75                 .name           = name_s3c2410
76         },
77         {
78                 .idcode         = 0x32410002,
79                 .idmask         = 0xffffffff,
80                 .map_io         = s3c2410_map_io,
81                 .init_clocks    = s3c2410_init_clocks,
82                 .init_uarts     = s3c2410_init_uarts,
83                 .init           = s3c2410a_init,
84                 .name           = name_s3c2410a
85         },
86         {
87                 .idcode         = 0x32440000,
88                 .idmask         = 0xffffffff,
89                 .map_io         = s3c2440_map_io,
90                 .init_clocks    = s3c244x_init_clocks,
91                 .init_uarts     = s3c244x_init_uarts,
92                 .init           = s3c2440_init,
93                 .name           = name_s3c2440
94         },
95         {
96                 .idcode         = 0x32440001,
97                 .idmask         = 0xffffffff,
98                 .map_io         = s3c2440_map_io,
99                 .init_clocks    = s3c244x_init_clocks,
100                 .init_uarts     = s3c244x_init_uarts,
101                 .init           = s3c2440_init,
102                 .name           = name_s3c2440a
103         },
104         {
105                 .idcode         = 0x32440aaa,
106                 .idmask         = 0xffffffff,
107                 .map_io         = s3c2442_map_io,
108                 .init_clocks    = s3c244x_init_clocks,
109                 .init_uarts     = s3c244x_init_uarts,
110                 .init           = s3c2442_init,
111                 .name           = name_s3c2442
112         },
113         {
114                 .idcode         = 0x32440aab,
115                 .idmask         = 0xffffffff,
116                 .map_io         = s3c2442_map_io,
117                 .init_clocks    = s3c244x_init_clocks,
118                 .init_uarts     = s3c244x_init_uarts,
119                 .init           = s3c2442_init,
120                 .name           = name_s3c2442b
121         },
122         {
123                 .idcode         = 0x32412001,
124                 .idmask         = 0xffffffff,
125                 .map_io         = s3c2412_map_io,
126                 .init_clocks    = s3c2412_init_clocks,
127                 .init_uarts     = s3c2412_init_uarts,
128                 .init           = s3c2412_init,
129                 .name           = name_s3c2412,
130         },
131         {                       /* a newer version of the s3c2412 */
132                 .idcode         = 0x32412003,
133                 .idmask         = 0xffffffff,
134                 .map_io         = s3c2412_map_io,
135                 .init_clocks    = s3c2412_init_clocks,
136                 .init_uarts     = s3c2412_init_uarts,
137                 .init           = s3c2412_init,
138                 .name           = name_s3c2412,
139         },
140         {                       /* a strange version of the s3c2416 */
141                 .idcode         = 0x32450003,
142                 .idmask         = 0xffffffff,
143                 .map_io         = s3c2416_map_io,
144                 .init_clocks    = s3c2416_init_clocks,
145                 .init_uarts     = s3c2416_init_uarts,
146                 .init           = s3c2416_init,
147                 .name           = name_s3c2416,
148         },
149         {
150                 .idcode         = 0x32443001,
151                 .idmask         = 0xffffffff,
152                 .map_io         = s3c2443_map_io,
153                 .init_clocks    = s3c2443_init_clocks,
154                 .init_uarts     = s3c2443_init_uarts,
155                 .init           = s3c2443_init,
156                 .name           = name_s3c2443,
157         },
158 };
159
160 /* minimal IO mapping */
161
162 static struct map_desc s3c_iodesc[] __initdata = {
163         IODESC_ENT(GPIO),
164         IODESC_ENT(IRQ),
165         IODESC_ENT(MEMCTRL),
166         IODESC_ENT(UART)
167 };
168
169 /* read cpu identificaiton code */
170
171 static unsigned long s3c24xx_read_idcode_v5(void)
172 {
173 #if defined(CONFIG_CPU_S3C2416)
174         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
175
176         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
177
178         /* test for s3c2416 or similar device */
179         if ((gs >> 16) == 0x3245)
180                 return gs;
181 #endif
182
183 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
184         return __raw_readl(S3C2412_GSTATUS1);
185 #else
186         return 1UL;     /* don't look like an 2400 */
187 #endif
188 }
189
190 static unsigned long s3c24xx_read_idcode_v4(void)
191 {
192         return __raw_readl(S3C2410_GSTATUS1);
193 }
194
195 static void s3c24xx_default_idle(void)
196 {
197         unsigned long tmp;
198         int i;
199
200         /* idle the system by using the idle mode which will wait for an
201          * interrupt to happen before restarting the system.
202          */
203
204         /* Warning: going into idle state upsets jtag scanning */
205
206         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
207                      S3C2410_CLKCON);
208
209         /* the samsung port seems to do a loop and then unset idle.. */
210         for (i = 0; i < 50; i++)
211                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
212
213         /* this bit is not cleared on re-start... */
214
215         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
216                      S3C2410_CLKCON);
217 }
218
219 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
220 {
221         arm_pm_idle = s3c24xx_default_idle;
222
223         /* initialise the io descriptors we need for initialisation */
224         iotable_init(mach_desc, size);
225         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
226
227         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
228                 samsung_cpu_id = s3c24xx_read_idcode_v5();
229         } else {
230                 samsung_cpu_id = s3c24xx_read_idcode_v4();
231         }
232         s3c24xx_init_cpu();
233
234         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
235 }