ARM: 6408/1: omap: Map only available sram memory
[linux-2.6.git] / arch / arm / plat-omap / sram.c
1 /*
2  * linux/arch/arm/plat-omap/sram.c
3  *
4  * OMAP SRAM detection and management
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Written by Tony Lindgren <tony@atomide.com>
8  *
9  * Copyright (C) 2009 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16 #undef DEBUG
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22
23 #include <asm/tlb.h>
24 #include <asm/cacheflush.h>
25
26 #include <asm/mach/map.h>
27
28 #include <plat/sram.h>
29 #include <plat/board.h>
30 #include <plat/cpu.h>
31 #include <plat/vram.h>
32
33 #include <plat/control.h>
34
35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
36 # include "../mach-omap2/prm.h"
37 # include "../mach-omap2/cm.h"
38 # include "../mach-omap2/sdrc.h"
39 #endif
40
41 #define OMAP1_SRAM_PA           0x20000000
42 #define OMAP1_SRAM_VA           VMALLOC_END
43 #define OMAP2_SRAM_PA           0x40200000
44 #define OMAP2_SRAM_PUB_PA       0x4020f800
45 #define OMAP2_SRAM_VA           0xfe400000
46 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
47 #define OMAP3_SRAM_PA           0x40200000
48 #define OMAP3_SRAM_VA           0xfe400000
49 #define OMAP3_SRAM_PUB_PA       0x40208000
50 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
51 #define OMAP4_SRAM_PA           0x40300000
52 #define OMAP4_SRAM_VA           0xfe400000
53 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
54 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
55
56 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
57 #define SRAM_BOOTLOADER_SZ      0x00
58 #else
59 #define SRAM_BOOTLOADER_SZ      0x80
60 #endif
61
62 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
63 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
64 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
65
66 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
67 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
68 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
69 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
70 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
71 #define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
72
73 #define GP_DEVICE               0x300
74
75 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
76
77 static unsigned long omap_sram_start;
78 static unsigned long omap_sram_base;
79 static unsigned long omap_sram_size;
80 static unsigned long omap_sram_ceil;
81
82 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
83                                          unsigned long sram_vstart,
84                                          unsigned long sram_size,
85                                          unsigned long pstart_avail,
86                                          unsigned long size_avail);
87
88 /*
89  * Depending on the target RAMFS firewall setup, the public usable amount of
90  * SRAM varies.  The default accessible size for all device types is 2k. A GP
91  * device allows ARM11 but not other initiators for full size. This
92  * functionality seems ok until some nice security API happens.
93  */
94 static int is_sram_locked(void)
95 {
96         int type = 0;
97
98         if (cpu_is_omap44xx())
99                 /* Not yet supported */
100                 return 0;
101
102         if (cpu_is_omap242x())
103                 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
104
105         if (type == GP_DEVICE) {
106                 /* RAMFW: R/W access to all initiators for all qualifier sets */
107                 if (cpu_is_omap242x()) {
108                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
109                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
110                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
111                 }
112                 if (cpu_is_omap34xx()) {
113                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
114                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
115                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
116                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
117                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
118                 }
119                 return 0;
120         } else
121                 return 1; /* assume locked with no PPA or security driver */
122 }
123
124 /*
125  * The amount of SRAM depends on the core type.
126  * Note that we cannot try to test for SRAM here because writes
127  * to secure SRAM will hang the system. Also the SRAM is not
128  * yet mapped at this point.
129  */
130 void __init omap_detect_sram(void)
131 {
132         unsigned long reserved;
133
134         if (cpu_class_is_omap2()) {
135                 if (is_sram_locked()) {
136                         if (cpu_is_omap34xx()) {
137                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
138                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
139                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
140                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
141                                         omap_sram_size = 0x7000; /* 28K */
142                                 } else {
143                                         omap_sram_size = 0x8000; /* 32K */
144                                 }
145                         } else if (cpu_is_omap44xx()) {
146                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
147                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
148                                 omap_sram_size = 0xa000; /* 40K */
149                         } else {
150                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
151                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
152                                 omap_sram_size = 0x800; /* 2K */
153                         }
154                 } else {
155                         if (cpu_is_omap34xx()) {
156                                 omap_sram_base = OMAP3_SRAM_VA;
157                                 omap_sram_start = OMAP3_SRAM_PA;
158                                 omap_sram_size = 0x10000; /* 64K */
159                         } else if (cpu_is_omap44xx()) {
160                                 omap_sram_base = OMAP4_SRAM_VA;
161                                 omap_sram_start = OMAP4_SRAM_PA;
162                                 omap_sram_size = 0xe000; /* 56K */
163                         } else {
164                                 omap_sram_base = OMAP2_SRAM_VA;
165                                 omap_sram_start = OMAP2_SRAM_PA;
166                                 if (cpu_is_omap242x())
167                                         omap_sram_size = 0xa0000; /* 640K */
168                                 else if (cpu_is_omap243x())
169                                         omap_sram_size = 0x10000; /* 64K */
170                         }
171                 }
172         } else {
173                 omap_sram_base = OMAP1_SRAM_VA;
174                 omap_sram_start = OMAP1_SRAM_PA;
175
176                 if (cpu_is_omap7xx())
177                         omap_sram_size = 0x32000;       /* 200K */
178                 else if (cpu_is_omap15xx())
179                         omap_sram_size = 0x30000;       /* 192K */
180                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
181                      cpu_is_omap1710())
182                         omap_sram_size = 0x4000;        /* 16K */
183                 else if (cpu_is_omap1611())
184                         omap_sram_size = 0x3e800;       /* 250K */
185                 else {
186                         printk(KERN_ERR "Could not detect SRAM size\n");
187                         omap_sram_size = 0x4000;
188                 }
189         }
190         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
191                                        omap_sram_size,
192                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
193                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
194         omap_sram_size -= reserved;
195
196         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
197                         omap_sram_size,
198                         omap_sram_start + SRAM_BOOTLOADER_SZ,
199                         omap_sram_size - SRAM_BOOTLOADER_SZ);
200         omap_sram_size -= reserved;
201
202         omap_sram_ceil = omap_sram_base + omap_sram_size;
203 }
204
205 static struct map_desc omap_sram_io_desc[] __initdata = {
206         {       /* .length gets filled in at runtime */
207                 .virtual        = OMAP1_SRAM_VA,
208                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
209                 .type           = MT_MEMORY
210         }
211 };
212
213 /*
214  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
215  */
216 void __init omap_map_sram(void)
217 {
218         unsigned long base;
219
220         if (omap_sram_size == 0)
221                 return;
222
223         if (cpu_is_omap34xx()) {
224                 /*
225                  * SRAM must be marked as non-cached on OMAP3 since the
226                  * CORE DPLL M2 divider change code (in SRAM) runs with the
227                  * SDRAM controller disabled, and if it is marked cached,
228                  * the ARM may attempt to write cache lines back to SDRAM
229                  * which will cause the system to hang.
230                  */
231                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
232         }
233
234         omap_sram_io_desc[0].virtual = omap_sram_base;
235         base = omap_sram_start;
236         base = ROUND_DOWN(base, PAGE_SIZE);
237         omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
238         omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
239         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
240
241         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
242         __pfn_to_phys(omap_sram_io_desc[0].pfn),
243         omap_sram_io_desc[0].virtual,
244                omap_sram_io_desc[0].length);
245
246         /*
247          * Normally devicemaps_init() would flush caches and tlb after
248          * mdesc->map_io(), but since we're called from map_io(), we
249          * must do it here.
250          */
251         local_flush_tlb_all();
252         flush_cache_all();
253
254         /*
255          * Looks like we need to preserve some bootloader code at the
256          * beginning of SRAM for jumping to flash for reboot to work...
257          */
258         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
259                omap_sram_size - SRAM_BOOTLOADER_SZ);
260 }
261
262 void * omap_sram_push(void * start, unsigned long size)
263 {
264         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
265                 printk(KERN_ERR "Not enough space in SRAM\n");
266                 return NULL;
267         }
268
269         omap_sram_ceil -= size;
270         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
271         memcpy((void *)omap_sram_ceil, start, size);
272         flush_icache_range((unsigned long)omap_sram_ceil,
273                 (unsigned long)(omap_sram_ceil + size));
274
275         return (void *)omap_sram_ceil;
276 }
277
278 #ifdef CONFIG_ARCH_OMAP1
279
280 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
281
282 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
283 {
284         BUG_ON(!_omap_sram_reprogram_clock);
285         _omap_sram_reprogram_clock(dpllctl, ckctl);
286 }
287
288 int __init omap1_sram_init(void)
289 {
290         _omap_sram_reprogram_clock =
291                         omap_sram_push(omap1_sram_reprogram_clock,
292                                         omap1_sram_reprogram_clock_sz);
293
294         return 0;
295 }
296
297 #else
298 #define omap1_sram_init()       do {} while (0)
299 #endif
300
301 #if defined(CONFIG_ARCH_OMAP2)
302
303 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
304                               u32 base_cs, u32 force_unlock);
305
306 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
307                    u32 base_cs, u32 force_unlock)
308 {
309         BUG_ON(!_omap2_sram_ddr_init);
310         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
311                              base_cs, force_unlock);
312 }
313
314 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
315                                           u32 mem_type);
316
317 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
318 {
319         BUG_ON(!_omap2_sram_reprogram_sdrc);
320         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
321 }
322
323 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
324
325 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
326 {
327         BUG_ON(!_omap2_set_prcm);
328         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
329 }
330 #endif
331
332 #ifdef CONFIG_ARCH_OMAP2420
333 int __init omap242x_sram_init(void)
334 {
335         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
336                                         omap242x_sram_ddr_init_sz);
337
338         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
339                                             omap242x_sram_reprogram_sdrc_sz);
340
341         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
342                                          omap242x_sram_set_prcm_sz);
343
344         return 0;
345 }
346 #else
347 static inline int omap242x_sram_init(void)
348 {
349         return 0;
350 }
351 #endif
352
353 #ifdef CONFIG_ARCH_OMAP2430
354 int __init omap243x_sram_init(void)
355 {
356         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
357                                         omap243x_sram_ddr_init_sz);
358
359         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
360                                             omap243x_sram_reprogram_sdrc_sz);
361
362         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
363                                          omap243x_sram_set_prcm_sz);
364
365         return 0;
366 }
367 #else
368 static inline int omap243x_sram_init(void)
369 {
370         return 0;
371 }
372 #endif
373
374 #ifdef CONFIG_ARCH_OMAP3
375
376 static u32 (*_omap3_sram_configure_core_dpll)(
377                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
378                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
379                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
380                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
381                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
382
383 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
384                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
385                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
386                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
387                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
388 {
389         BUG_ON(!_omap3_sram_configure_core_dpll);
390         return _omap3_sram_configure_core_dpll(
391                         m2, unlock_dll, f, inc,
392                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
393                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
394                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
395                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
396 }
397
398 #ifdef CONFIG_PM
399 void omap3_sram_restore_context(void)
400 {
401         omap_sram_ceil = omap_sram_base + omap_sram_size;
402
403         _omap3_sram_configure_core_dpll =
404                 omap_sram_push(omap3_sram_configure_core_dpll,
405                                omap3_sram_configure_core_dpll_sz);
406         omap_push_sram_idle();
407 }
408 #endif /* CONFIG_PM */
409
410 int __init omap34xx_sram_init(void)
411 {
412         _omap3_sram_configure_core_dpll =
413                 omap_sram_push(omap3_sram_configure_core_dpll,
414                                omap3_sram_configure_core_dpll_sz);
415         omap_push_sram_idle();
416         return 0;
417 }
418 #else
419 static inline int omap34xx_sram_init(void)
420 {
421         return 0;
422 }
423 #endif
424
425 #ifdef CONFIG_ARCH_OMAP4
426 int __init omap44xx_sram_init(void)
427 {
428         printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
429
430         return -ENODEV;
431 }
432 #else
433 static inline int omap44xx_sram_init(void)
434 {
435         return 0;
436 }
437 #endif
438
439 int __init omap_sram_init(void)
440 {
441         omap_detect_sram();
442         omap_map_sram();
443
444         if (!(cpu_class_is_omap2()))
445                 omap1_sram_init();
446         else if (cpu_is_omap242x())
447                 omap242x_sram_init();
448         else if (cpu_is_omap2430())
449                 omap243x_sram_init();
450         else if (cpu_is_omap34xx())
451                 omap34xx_sram_init();
452         else if (cpu_is_omap44xx())
453                 omap44xx_sram_init();
454
455         return 0;
456 }