Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6.git] / arch / arm / plat-omap / mcbsp.c
1 /*
2  * linux/arch/arm/plat-omap/mcbsp.c
3  *
4  * Copyright (C) 2004 Nokia Corporation
5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6  *
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * Multichannel mode not supported.
13  */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <plat/dma.h>
29 #include <plat/mcbsp.h>
30
31 #include "../mach-omap2/cm-regbits-34xx.h"
32
33 struct omap_mcbsp **mcbsp_ptr;
34 int omap_mcbsp_count, omap_mcbsp_cache_size;
35
36 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37 {
38         if (cpu_class_is_omap1()) {
39                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
40                 __raw_writew((u16)val, mcbsp->io_base + reg);
41         } else if (cpu_is_omap2420()) {
42                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
43                 __raw_writew((u16)val, mcbsp->io_base + reg);
44         } else {
45                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
46                 __raw_writel(val, mcbsp->io_base + reg);
47         }
48 }
49
50 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51 {
52         if (cpu_class_is_omap1()) {
53                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
54                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
55         } else if (cpu_is_omap2420()) {
56                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
57                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58         } else {
59                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
60                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
61         }
62 }
63
64 #ifdef CONFIG_ARCH_OMAP3
65 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66 {
67         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68 }
69
70 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71 {
72         return __raw_readl(mcbsp->st_data->io_base_st + reg);
73 }
74 #endif
75
76 #define MCBSP_READ(mcbsp, reg) \
77                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
78 #define MCBSP_WRITE(mcbsp, reg, val) \
79                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
80 #define MCBSP_READ_CACHE(mcbsp, reg) \
81                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82
83 #define MCBSP_ST_READ(mcbsp, reg) \
84                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
85 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
86                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
87
88 static void omap_mcbsp_dump_reg(u8 id)
89 {
90         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
91
92         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
93         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
94                         MCBSP_READ(mcbsp, DRR2));
95         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
96                         MCBSP_READ(mcbsp, DRR1));
97         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
98                         MCBSP_READ(mcbsp, DXR2));
99         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
100                         MCBSP_READ(mcbsp, DXR1));
101         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
102                         MCBSP_READ(mcbsp, SPCR2));
103         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
104                         MCBSP_READ(mcbsp, SPCR1));
105         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
106                         MCBSP_READ(mcbsp, RCR2));
107         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
108                         MCBSP_READ(mcbsp, RCR1));
109         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
110                         MCBSP_READ(mcbsp, XCR2));
111         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
112                         MCBSP_READ(mcbsp, XCR1));
113         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
114                         MCBSP_READ(mcbsp, SRGR2));
115         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
116                         MCBSP_READ(mcbsp, SRGR1));
117         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
118                         MCBSP_READ(mcbsp, PCR0));
119         dev_dbg(mcbsp->dev, "***********************\n");
120 }
121
122 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
123 {
124         struct omap_mcbsp *mcbsp_tx = dev_id;
125         u16 irqst_spcr2;
126
127         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
128         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
129
130         if (irqst_spcr2 & XSYNC_ERR) {
131                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
132                         irqst_spcr2);
133                 /* Writing zero to XSYNC_ERR clears the IRQ */
134                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
135         } else {
136                 complete(&mcbsp_tx->tx_irq_completion);
137         }
138
139         return IRQ_HANDLED;
140 }
141
142 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
143 {
144         struct omap_mcbsp *mcbsp_rx = dev_id;
145         u16 irqst_spcr1;
146
147         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
148         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
149
150         if (irqst_spcr1 & RSYNC_ERR) {
151                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
152                         irqst_spcr1);
153                 /* Writing zero to RSYNC_ERR clears the IRQ */
154                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
155         } else {
156                 complete(&mcbsp_rx->rx_irq_completion);
157         }
158
159         return IRQ_HANDLED;
160 }
161
162 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
163 {
164         struct omap_mcbsp *mcbsp_dma_tx = data;
165
166         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
167                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
168
169         /* We can free the channels */
170         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
171         mcbsp_dma_tx->dma_tx_lch = -1;
172
173         complete(&mcbsp_dma_tx->tx_dma_completion);
174 }
175
176 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
177 {
178         struct omap_mcbsp *mcbsp_dma_rx = data;
179
180         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
181                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
182
183         /* We can free the channels */
184         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
185         mcbsp_dma_rx->dma_rx_lch = -1;
186
187         complete(&mcbsp_dma_rx->rx_dma_completion);
188 }
189
190 /*
191  * omap_mcbsp_config simply write a config to the
192  * appropriate McBSP.
193  * You either call this function or set the McBSP registers
194  * by yourself before calling omap_mcbsp_start().
195  */
196 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
197 {
198         struct omap_mcbsp *mcbsp;
199
200         if (!omap_mcbsp_check_valid_id(id)) {
201                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
202                 return;
203         }
204         mcbsp = id_to_mcbsp_ptr(id);
205
206         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
207                         mcbsp->id, mcbsp->phys_base);
208
209         /* We write the given config */
210         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
211         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
212         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
213         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
214         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
215         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
216         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
217         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
218         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
219         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
220         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
221         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
222                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
223                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
224         }
225 }
226 EXPORT_SYMBOL(omap_mcbsp_config);
227
228 #ifdef CONFIG_ARCH_OMAP3
229 static void omap_st_on(struct omap_mcbsp *mcbsp)
230 {
231         unsigned int w;
232
233         /*
234          * Sidetone uses McBSP ICLK - which must not idle when sidetones
235          * are enabled or sidetones start sounding ugly.
236          */
237         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
238         w &= ~(1 << (mcbsp->id - 2));
239         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
240
241         /* Enable McBSP Sidetone */
242         w = MCBSP_READ(mcbsp, SSELCR);
243         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
244
245         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
246         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
247
248         /* Enable Sidetone from Sidetone Core */
249         w = MCBSP_ST_READ(mcbsp, SSELCR);
250         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
251 }
252
253 static void omap_st_off(struct omap_mcbsp *mcbsp)
254 {
255         unsigned int w;
256
257         w = MCBSP_ST_READ(mcbsp, SSELCR);
258         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
259
260         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
261         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
262
263         w = MCBSP_READ(mcbsp, SSELCR);
264         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
265
266         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
267         w |= 1 << (mcbsp->id - 2);
268         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
269 }
270
271 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
272 {
273         u16 val, i;
274
275         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
276         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
277
278         val = MCBSP_ST_READ(mcbsp, SSELCR);
279
280         if (val & ST_COEFFWREN)
281                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
282
283         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
284
285         for (i = 0; i < 128; i++)
286                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
287
288         i = 0;
289
290         val = MCBSP_ST_READ(mcbsp, SSELCR);
291         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
292                 val = MCBSP_ST_READ(mcbsp, SSELCR);
293
294         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
295
296         if (i == 1000)
297                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
298 }
299
300 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
301 {
302         u16 w;
303         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
304
305         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
306         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
307
308         w = MCBSP_ST_READ(mcbsp, SSELCR);
309
310         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
311                       ST_CH1GAIN(st_data->ch1gain));
312 }
313
314 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
315 {
316         struct omap_mcbsp *mcbsp;
317         struct omap_mcbsp_st_data *st_data;
318         int ret = 0;
319
320         if (!omap_mcbsp_check_valid_id(id)) {
321                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
322                 return -ENODEV;
323         }
324
325         mcbsp = id_to_mcbsp_ptr(id);
326         st_data = mcbsp->st_data;
327
328         if (!st_data)
329                 return -ENOENT;
330
331         spin_lock_irq(&mcbsp->lock);
332         if (channel == 0)
333                 st_data->ch0gain = chgain;
334         else if (channel == 1)
335                 st_data->ch1gain = chgain;
336         else
337                 ret = -EINVAL;
338
339         if (st_data->enabled)
340                 omap_st_chgain(mcbsp);
341         spin_unlock_irq(&mcbsp->lock);
342
343         return ret;
344 }
345 EXPORT_SYMBOL(omap_st_set_chgain);
346
347 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
348 {
349         struct omap_mcbsp *mcbsp;
350         struct omap_mcbsp_st_data *st_data;
351         int ret = 0;
352
353         if (!omap_mcbsp_check_valid_id(id)) {
354                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
355                 return -ENODEV;
356         }
357
358         mcbsp = id_to_mcbsp_ptr(id);
359         st_data = mcbsp->st_data;
360
361         if (!st_data)
362                 return -ENOENT;
363
364         spin_lock_irq(&mcbsp->lock);
365         if (channel == 0)
366                 *chgain = st_data->ch0gain;
367         else if (channel == 1)
368                 *chgain = st_data->ch1gain;
369         else
370                 ret = -EINVAL;
371         spin_unlock_irq(&mcbsp->lock);
372
373         return ret;
374 }
375 EXPORT_SYMBOL(omap_st_get_chgain);
376
377 static int omap_st_start(struct omap_mcbsp *mcbsp)
378 {
379         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
380
381         if (st_data && st_data->enabled && !st_data->running) {
382                 omap_st_fir_write(mcbsp, st_data->taps);
383                 omap_st_chgain(mcbsp);
384
385                 if (!mcbsp->free) {
386                         omap_st_on(mcbsp);
387                         st_data->running = 1;
388                 }
389         }
390
391         return 0;
392 }
393
394 int omap_st_enable(unsigned int id)
395 {
396         struct omap_mcbsp *mcbsp;
397         struct omap_mcbsp_st_data *st_data;
398
399         if (!omap_mcbsp_check_valid_id(id)) {
400                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
401                 return -ENODEV;
402         }
403
404         mcbsp = id_to_mcbsp_ptr(id);
405         st_data = mcbsp->st_data;
406
407         if (!st_data)
408                 return -ENODEV;
409
410         spin_lock_irq(&mcbsp->lock);
411         st_data->enabled = 1;
412         omap_st_start(mcbsp);
413         spin_unlock_irq(&mcbsp->lock);
414
415         return 0;
416 }
417 EXPORT_SYMBOL(omap_st_enable);
418
419 static int omap_st_stop(struct omap_mcbsp *mcbsp)
420 {
421         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
422
423         if (st_data && st_data->running) {
424                 if (!mcbsp->free) {
425                         omap_st_off(mcbsp);
426                         st_data->running = 0;
427                 }
428         }
429
430         return 0;
431 }
432
433 int omap_st_disable(unsigned int id)
434 {
435         struct omap_mcbsp *mcbsp;
436         struct omap_mcbsp_st_data *st_data;
437         int ret = 0;
438
439         if (!omap_mcbsp_check_valid_id(id)) {
440                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
441                 return -ENODEV;
442         }
443
444         mcbsp = id_to_mcbsp_ptr(id);
445         st_data = mcbsp->st_data;
446
447         if (!st_data)
448                 return -ENODEV;
449
450         spin_lock_irq(&mcbsp->lock);
451         omap_st_stop(mcbsp);
452         st_data->enabled = 0;
453         spin_unlock_irq(&mcbsp->lock);
454
455         return ret;
456 }
457 EXPORT_SYMBOL(omap_st_disable);
458
459 int omap_st_is_enabled(unsigned int id)
460 {
461         struct omap_mcbsp *mcbsp;
462         struct omap_mcbsp_st_data *st_data;
463
464         if (!omap_mcbsp_check_valid_id(id)) {
465                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
466                 return -ENODEV;
467         }
468
469         mcbsp = id_to_mcbsp_ptr(id);
470         st_data = mcbsp->st_data;
471
472         if (!st_data)
473                 return -ENODEV;
474
475
476         return st_data->enabled;
477 }
478 EXPORT_SYMBOL(omap_st_is_enabled);
479
480 /*
481  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
482  * The threshold parameter is 1 based, and it is converted (threshold - 1)
483  * for the THRSH2 register.
484  */
485 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
486 {
487         struct omap_mcbsp *mcbsp;
488
489         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
490                 return;
491
492         if (!omap_mcbsp_check_valid_id(id)) {
493                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
494                 return;
495         }
496         mcbsp = id_to_mcbsp_ptr(id);
497
498         if (threshold && threshold <= mcbsp->max_tx_thres)
499                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
500 }
501 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
502
503 /*
504  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
505  * The threshold parameter is 1 based, and it is converted (threshold - 1)
506  * for the THRSH1 register.
507  */
508 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
509 {
510         struct omap_mcbsp *mcbsp;
511
512         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
513                 return;
514
515         if (!omap_mcbsp_check_valid_id(id)) {
516                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
517                 return;
518         }
519         mcbsp = id_to_mcbsp_ptr(id);
520
521         if (threshold && threshold <= mcbsp->max_rx_thres)
522                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
523 }
524 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
525
526 /*
527  * omap_mcbsp_get_max_tx_thres just return the current configured
528  * maximum threshold for transmission
529  */
530 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
531 {
532         struct omap_mcbsp *mcbsp;
533
534         if (!omap_mcbsp_check_valid_id(id)) {
535                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
536                 return -ENODEV;
537         }
538         mcbsp = id_to_mcbsp_ptr(id);
539
540         return mcbsp->max_tx_thres;
541 }
542 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
543
544 /*
545  * omap_mcbsp_get_max_rx_thres just return the current configured
546  * maximum threshold for reception
547  */
548 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
549 {
550         struct omap_mcbsp *mcbsp;
551
552         if (!omap_mcbsp_check_valid_id(id)) {
553                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
554                 return -ENODEV;
555         }
556         mcbsp = id_to_mcbsp_ptr(id);
557
558         return mcbsp->max_rx_thres;
559 }
560 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
561
562 u16 omap_mcbsp_get_fifo_size(unsigned int id)
563 {
564         struct omap_mcbsp *mcbsp;
565
566         if (!omap_mcbsp_check_valid_id(id)) {
567                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
568                 return -ENODEV;
569         }
570         mcbsp = id_to_mcbsp_ptr(id);
571
572         return mcbsp->pdata->buffer_size;
573 }
574 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
575
576 /*
577  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
578  */
579 u16 omap_mcbsp_get_tx_delay(unsigned int id)
580 {
581         struct omap_mcbsp *mcbsp;
582         u16 buffstat;
583
584         if (!omap_mcbsp_check_valid_id(id)) {
585                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
586                 return -ENODEV;
587         }
588         mcbsp = id_to_mcbsp_ptr(id);
589
590         /* Returns the number of free locations in the buffer */
591         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
592
593         /* Number of slots are different in McBSP ports */
594         return mcbsp->pdata->buffer_size - buffstat;
595 }
596 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
597
598 /*
599  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
600  * to reach the threshold value (when the DMA will be triggered to read it)
601  */
602 u16 omap_mcbsp_get_rx_delay(unsigned int id)
603 {
604         struct omap_mcbsp *mcbsp;
605         u16 buffstat, threshold;
606
607         if (!omap_mcbsp_check_valid_id(id)) {
608                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
609                 return -ENODEV;
610         }
611         mcbsp = id_to_mcbsp_ptr(id);
612
613         /* Returns the number of used locations in the buffer */
614         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
615         /* RX threshold */
616         threshold = MCBSP_READ(mcbsp, THRSH1);
617
618         /* Return the number of location till we reach the threshold limit */
619         if (threshold <= buffstat)
620                 return 0;
621         else
622                 return threshold - buffstat;
623 }
624 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
625
626 /*
627  * omap_mcbsp_get_dma_op_mode just return the current configured
628  * operating mode for the mcbsp channel
629  */
630 int omap_mcbsp_get_dma_op_mode(unsigned int id)
631 {
632         struct omap_mcbsp *mcbsp;
633         int dma_op_mode;
634
635         if (!omap_mcbsp_check_valid_id(id)) {
636                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
637                 return -ENODEV;
638         }
639         mcbsp = id_to_mcbsp_ptr(id);
640
641         dma_op_mode = mcbsp->dma_op_mode;
642
643         return dma_op_mode;
644 }
645 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
646
647 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
648 {
649         /*
650          * Enable wakup behavior, smart idle and all wakeups
651          * REVISIT: some wakeups may be unnecessary
652          */
653         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
654                 u16 syscon;
655
656                 syscon = MCBSP_READ(mcbsp, SYSCON);
657                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
658
659                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
660                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
661                                         CLOCKACTIVITY(0x02));
662                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
663                 } else {
664                         syscon |= SIDLEMODE(0x01);
665                 }
666
667                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
668         }
669 }
670
671 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
672 {
673         /*
674          * Disable wakup behavior, smart idle and all wakeups
675          */
676         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
677                 u16 syscon;
678
679                 syscon = MCBSP_READ(mcbsp, SYSCON);
680                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
681                 /*
682                  * HW bug workaround - If no_idle mode is taken, we need to
683                  * go to smart_idle before going to always_idle, or the
684                  * device will not hit retention anymore.
685                  */
686                 syscon |= SIDLEMODE(0x02);
687                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
688
689                 syscon &= ~(SIDLEMODE(0x03));
690                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
691
692                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
693         }
694 }
695 #else
696 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
697 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
698 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
699 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
700 #endif
701
702 /*
703  * We can choose between IRQ based or polled IO.
704  * This needs to be called before omap_mcbsp_request().
705  */
706 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
707 {
708         struct omap_mcbsp *mcbsp;
709
710         if (!omap_mcbsp_check_valid_id(id)) {
711                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
712                 return -ENODEV;
713         }
714         mcbsp = id_to_mcbsp_ptr(id);
715
716         spin_lock(&mcbsp->lock);
717
718         if (!mcbsp->free) {
719                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
720                         mcbsp->id);
721                 spin_unlock(&mcbsp->lock);
722                 return -EINVAL;
723         }
724
725         mcbsp->io_type = io_type;
726
727         spin_unlock(&mcbsp->lock);
728
729         return 0;
730 }
731 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
732
733 int omap_mcbsp_request(unsigned int id)
734 {
735         struct omap_mcbsp *mcbsp;
736         void *reg_cache;
737         int err;
738
739         if (!omap_mcbsp_check_valid_id(id)) {
740                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
741                 return -ENODEV;
742         }
743         mcbsp = id_to_mcbsp_ptr(id);
744
745         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
746         if (!reg_cache) {
747                 return -ENOMEM;
748         }
749
750         spin_lock(&mcbsp->lock);
751         if (!mcbsp->free) {
752                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
753                         mcbsp->id);
754                 err = -EBUSY;
755                 goto err_kfree;
756         }
757
758         mcbsp->free = 0;
759         mcbsp->reg_cache = reg_cache;
760         spin_unlock(&mcbsp->lock);
761
762         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
763                 mcbsp->pdata->ops->request(id);
764
765         clk_enable(mcbsp->iclk);
766         clk_enable(mcbsp->fclk);
767
768         /* Do procedure specific to omap34xx arch, if applicable */
769         omap34xx_mcbsp_request(mcbsp);
770
771         /*
772          * Make sure that transmitter, receiver and sample-rate generator are
773          * not running before activating IRQs.
774          */
775         MCBSP_WRITE(mcbsp, SPCR1, 0);
776         MCBSP_WRITE(mcbsp, SPCR2, 0);
777
778         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
779                 /* We need to get IRQs here */
780                 init_completion(&mcbsp->tx_irq_completion);
781                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
782                                         0, "McBSP", (void *)mcbsp);
783                 if (err != 0) {
784                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
785                                         "for McBSP%d\n", mcbsp->tx_irq,
786                                         mcbsp->id);
787                         goto err_clk_disable;
788                 }
789
790                 if (mcbsp->rx_irq) {
791                         init_completion(&mcbsp->rx_irq_completion);
792                         err = request_irq(mcbsp->rx_irq,
793                                         omap_mcbsp_rx_irq_handler,
794                                         0, "McBSP", (void *)mcbsp);
795                         if (err != 0) {
796                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
797                                                 "for McBSP%d\n", mcbsp->rx_irq,
798                                                 mcbsp->id);
799                                 goto err_free_irq;
800                         }
801                 }
802         }
803
804         return 0;
805 err_free_irq:
806         free_irq(mcbsp->tx_irq, (void *)mcbsp);
807 err_clk_disable:
808         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
809                 mcbsp->pdata->ops->free(id);
810
811         /* Do procedure specific to omap34xx arch, if applicable */
812         omap34xx_mcbsp_free(mcbsp);
813
814         clk_disable(mcbsp->fclk);
815         clk_disable(mcbsp->iclk);
816
817         spin_lock(&mcbsp->lock);
818         mcbsp->free = 1;
819         mcbsp->reg_cache = NULL;
820 err_kfree:
821         spin_unlock(&mcbsp->lock);
822         kfree(reg_cache);
823
824         return err;
825 }
826 EXPORT_SYMBOL(omap_mcbsp_request);
827
828 void omap_mcbsp_free(unsigned int id)
829 {
830         struct omap_mcbsp *mcbsp;
831         void *reg_cache;
832
833         if (!omap_mcbsp_check_valid_id(id)) {
834                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
835                 return;
836         }
837         mcbsp = id_to_mcbsp_ptr(id);
838
839         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
840                 mcbsp->pdata->ops->free(id);
841
842         /* Do procedure specific to omap34xx arch, if applicable */
843         omap34xx_mcbsp_free(mcbsp);
844
845         clk_disable(mcbsp->fclk);
846         clk_disable(mcbsp->iclk);
847
848         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
849                 /* Free IRQs */
850                 if (mcbsp->rx_irq)
851                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
852                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
853         }
854
855         reg_cache = mcbsp->reg_cache;
856
857         spin_lock(&mcbsp->lock);
858         if (mcbsp->free)
859                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
860         else
861                 mcbsp->free = 1;
862         mcbsp->reg_cache = NULL;
863         spin_unlock(&mcbsp->lock);
864
865         if (reg_cache)
866                 kfree(reg_cache);
867 }
868 EXPORT_SYMBOL(omap_mcbsp_free);
869
870 /*
871  * Here we start the McBSP, by enabling transmitter, receiver or both.
872  * If no transmitter or receiver is active prior calling, then sample-rate
873  * generator and frame sync are started.
874  */
875 void omap_mcbsp_start(unsigned int id, int tx, int rx)
876 {
877         struct omap_mcbsp *mcbsp;
878         int enable_srg = 0;
879         u16 w;
880
881         if (!omap_mcbsp_check_valid_id(id)) {
882                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
883                 return;
884         }
885         mcbsp = id_to_mcbsp_ptr(id);
886
887         if (cpu_is_omap34xx())
888                 omap_st_start(mcbsp);
889
890         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
891         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
892
893         /* Only enable SRG, if McBSP is master */
894         w = MCBSP_READ_CACHE(mcbsp, PCR0);
895         if (w & (FSXM | FSRM | CLKXM | CLKRM))
896                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
897                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
898
899         if (enable_srg) {
900                 /* Start the sample generator */
901                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
902                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
903         }
904
905         /* Enable transmitter and receiver */
906         tx &= 1;
907         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
908         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
909
910         rx &= 1;
911         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
912         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
913
914         /*
915          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
916          * REVISIT: 100us may give enough time for two CLKSRG, however
917          * due to some unknown PM related, clock gating etc. reason it
918          * is now at 500us.
919          */
920         udelay(500);
921
922         if (enable_srg) {
923                 /* Start frame sync */
924                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
925                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
926         }
927
928         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
929                 /* Release the transmitter and receiver */
930                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
931                 w &= ~(tx ? XDISABLE : 0);
932                 MCBSP_WRITE(mcbsp, XCCR, w);
933                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
934                 w &= ~(rx ? RDISABLE : 0);
935                 MCBSP_WRITE(mcbsp, RCCR, w);
936         }
937
938         /* Dump McBSP Regs */
939         omap_mcbsp_dump_reg(id);
940 }
941 EXPORT_SYMBOL(omap_mcbsp_start);
942
943 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
944 {
945         struct omap_mcbsp *mcbsp;
946         int idle;
947         u16 w;
948
949         if (!omap_mcbsp_check_valid_id(id)) {
950                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
951                 return;
952         }
953
954         mcbsp = id_to_mcbsp_ptr(id);
955
956         /* Reset transmitter */
957         tx &= 1;
958         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
959                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
960                 w |= (tx ? XDISABLE : 0);
961                 MCBSP_WRITE(mcbsp, XCCR, w);
962         }
963         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
964         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
965
966         /* Reset receiver */
967         rx &= 1;
968         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
969                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
970                 w |= (rx ? RDISABLE : 0);
971                 MCBSP_WRITE(mcbsp, RCCR, w);
972         }
973         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
974         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
975
976         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
977                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
978
979         if (idle) {
980                 /* Reset the sample rate generator */
981                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
982                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
983         }
984
985         if (cpu_is_omap34xx())
986                 omap_st_stop(mcbsp);
987 }
988 EXPORT_SYMBOL(omap_mcbsp_stop);
989
990 /* polled mcbsp i/o operations */
991 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
992 {
993         struct omap_mcbsp *mcbsp;
994
995         if (!omap_mcbsp_check_valid_id(id)) {
996                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
997                 return -ENODEV;
998         }
999
1000         mcbsp = id_to_mcbsp_ptr(id);
1001
1002         MCBSP_WRITE(mcbsp, DXR1, buf);
1003         /* if frame sync error - clear the error */
1004         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1005                 /* clear error */
1006                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1007                 /* resend */
1008                 return -1;
1009         } else {
1010                 /* wait for transmit confirmation */
1011                 int attemps = 0;
1012                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1013                         if (attemps++ > 1000) {
1014                                 MCBSP_WRITE(mcbsp, SPCR2,
1015                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1016                                                 (~XRST));
1017                                 udelay(10);
1018                                 MCBSP_WRITE(mcbsp, SPCR2,
1019                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1020                                                 (XRST));
1021                                 udelay(10);
1022                                 dev_err(mcbsp->dev, "Could not write to"
1023                                         " McBSP%d Register\n", mcbsp->id);
1024                                 return -2;
1025                         }
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1032
1033 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1034 {
1035         struct omap_mcbsp *mcbsp;
1036
1037         if (!omap_mcbsp_check_valid_id(id)) {
1038                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1039                 return -ENODEV;
1040         }
1041         mcbsp = id_to_mcbsp_ptr(id);
1042
1043         /* if frame sync error - clear the error */
1044         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1045                 /* clear error */
1046                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1047                 /* resend */
1048                 return -1;
1049         } else {
1050                 /* wait for recieve confirmation */
1051                 int attemps = 0;
1052                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1053                         if (attemps++ > 1000) {
1054                                 MCBSP_WRITE(mcbsp, SPCR1,
1055                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1056                                                 (~RRST));
1057                                 udelay(10);
1058                                 MCBSP_WRITE(mcbsp, SPCR1,
1059                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1060                                                 (RRST));
1061                                 udelay(10);
1062                                 dev_err(mcbsp->dev, "Could not read from"
1063                                         " McBSP%d Register\n", mcbsp->id);
1064                                 return -2;
1065                         }
1066                 }
1067         }
1068         *buf = MCBSP_READ(mcbsp, DRR1);
1069
1070         return 0;
1071 }
1072 EXPORT_SYMBOL(omap_mcbsp_pollread);
1073
1074 /*
1075  * IRQ based word transmission.
1076  */
1077 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1078 {
1079         struct omap_mcbsp *mcbsp;
1080         omap_mcbsp_word_length word_length;
1081
1082         if (!omap_mcbsp_check_valid_id(id)) {
1083                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1084                 return;
1085         }
1086
1087         mcbsp = id_to_mcbsp_ptr(id);
1088         word_length = mcbsp->tx_word_length;
1089
1090         wait_for_completion(&mcbsp->tx_irq_completion);
1091
1092         if (word_length > OMAP_MCBSP_WORD_16)
1093                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1094         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1095 }
1096 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1097
1098 u32 omap_mcbsp_recv_word(unsigned int id)
1099 {
1100         struct omap_mcbsp *mcbsp;
1101         u16 word_lsb, word_msb = 0;
1102         omap_mcbsp_word_length word_length;
1103
1104         if (!omap_mcbsp_check_valid_id(id)) {
1105                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1106                 return -ENODEV;
1107         }
1108         mcbsp = id_to_mcbsp_ptr(id);
1109
1110         word_length = mcbsp->rx_word_length;
1111
1112         wait_for_completion(&mcbsp->rx_irq_completion);
1113
1114         if (word_length > OMAP_MCBSP_WORD_16)
1115                 word_msb = MCBSP_READ(mcbsp, DRR2);
1116         word_lsb = MCBSP_READ(mcbsp, DRR1);
1117
1118         return (word_lsb | (word_msb << 16));
1119 }
1120 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1121
1122 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1123 {
1124         struct omap_mcbsp *mcbsp;
1125         omap_mcbsp_word_length tx_word_length;
1126         omap_mcbsp_word_length rx_word_length;
1127         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1128
1129         if (!omap_mcbsp_check_valid_id(id)) {
1130                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1131                 return -ENODEV;
1132         }
1133         mcbsp = id_to_mcbsp_ptr(id);
1134         tx_word_length = mcbsp->tx_word_length;
1135         rx_word_length = mcbsp->rx_word_length;
1136
1137         if (tx_word_length != rx_word_length)
1138                 return -EINVAL;
1139
1140         /* First we wait for the transmitter to be ready */
1141         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1142         while (!(spcr2 & XRDY)) {
1143                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1144                 if (attempts++ > 1000) {
1145                         /* We must reset the transmitter */
1146                         MCBSP_WRITE(mcbsp, SPCR2,
1147                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1148                         udelay(10);
1149                         MCBSP_WRITE(mcbsp, SPCR2,
1150                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1151                         udelay(10);
1152                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1153                                 "ready\n", mcbsp->id);
1154                         return -EAGAIN;
1155                 }
1156         }
1157
1158         /* Now we can push the data */
1159         if (tx_word_length > OMAP_MCBSP_WORD_16)
1160                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1161         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1162
1163         /* We wait for the receiver to be ready */
1164         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1165         while (!(spcr1 & RRDY)) {
1166                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1167                 if (attempts++ > 1000) {
1168                         /* We must reset the receiver */
1169                         MCBSP_WRITE(mcbsp, SPCR1,
1170                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1171                         udelay(10);
1172                         MCBSP_WRITE(mcbsp, SPCR1,
1173                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1174                         udelay(10);
1175                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1176                                 "ready\n", mcbsp->id);
1177                         return -EAGAIN;
1178                 }
1179         }
1180
1181         /* Receiver is ready, let's read the dummy data */
1182         if (rx_word_length > OMAP_MCBSP_WORD_16)
1183                 word_msb = MCBSP_READ(mcbsp, DRR2);
1184         word_lsb = MCBSP_READ(mcbsp, DRR1);
1185
1186         return 0;
1187 }
1188 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1189
1190 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1191 {
1192         struct omap_mcbsp *mcbsp;
1193         u32 clock_word = 0;
1194         omap_mcbsp_word_length tx_word_length;
1195         omap_mcbsp_word_length rx_word_length;
1196         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1197
1198         if (!omap_mcbsp_check_valid_id(id)) {
1199                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1200                 return -ENODEV;
1201         }
1202
1203         mcbsp = id_to_mcbsp_ptr(id);
1204
1205         tx_word_length = mcbsp->tx_word_length;
1206         rx_word_length = mcbsp->rx_word_length;
1207
1208         if (tx_word_length != rx_word_length)
1209                 return -EINVAL;
1210
1211         /* First we wait for the transmitter to be ready */
1212         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1213         while (!(spcr2 & XRDY)) {
1214                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1215                 if (attempts++ > 1000) {
1216                         /* We must reset the transmitter */
1217                         MCBSP_WRITE(mcbsp, SPCR2,
1218                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1219                         udelay(10);
1220                         MCBSP_WRITE(mcbsp, SPCR2,
1221                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1222                         udelay(10);
1223                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1224                                 "ready\n", mcbsp->id);
1225                         return -EAGAIN;
1226                 }
1227         }
1228
1229         /* We first need to enable the bus clock */
1230         if (tx_word_length > OMAP_MCBSP_WORD_16)
1231                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1232         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1233
1234         /* We wait for the receiver to be ready */
1235         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1236         while (!(spcr1 & RRDY)) {
1237                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1238                 if (attempts++ > 1000) {
1239                         /* We must reset the receiver */
1240                         MCBSP_WRITE(mcbsp, SPCR1,
1241                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1242                         udelay(10);
1243                         MCBSP_WRITE(mcbsp, SPCR1,
1244                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1245                         udelay(10);
1246                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1247                                 "ready\n", mcbsp->id);
1248                         return -EAGAIN;
1249                 }
1250         }
1251
1252         /* Receiver is ready, there is something for us */
1253         if (rx_word_length > OMAP_MCBSP_WORD_16)
1254                 word_msb = MCBSP_READ(mcbsp, DRR2);
1255         word_lsb = MCBSP_READ(mcbsp, DRR1);
1256
1257         word[0] = (word_lsb | (word_msb << 16));
1258
1259         return 0;
1260 }
1261 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1262
1263 /*
1264  * Simple DMA based buffer rx/tx routines.
1265  * Nothing fancy, just a single buffer tx/rx through DMA.
1266  * The DMA resources are released once the transfer is done.
1267  * For anything fancier, you should use your own customized DMA
1268  * routines and callbacks.
1269  */
1270 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1271                                 unsigned int length)
1272 {
1273         struct omap_mcbsp *mcbsp;
1274         int dma_tx_ch;
1275         int src_port = 0;
1276         int dest_port = 0;
1277         int sync_dev = 0;
1278
1279         if (!omap_mcbsp_check_valid_id(id)) {
1280                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1281                 return -ENODEV;
1282         }
1283         mcbsp = id_to_mcbsp_ptr(id);
1284
1285         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1286                                 omap_mcbsp_tx_dma_callback,
1287                                 mcbsp,
1288                                 &dma_tx_ch)) {
1289                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1290                                 "McBSP%d TX. Trying IRQ based TX\n",
1291                                 mcbsp->id);
1292                 return -EAGAIN;
1293         }
1294         mcbsp->dma_tx_lch = dma_tx_ch;
1295
1296         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1297                 dma_tx_ch);
1298
1299         init_completion(&mcbsp->tx_dma_completion);
1300
1301         if (cpu_class_is_omap1()) {
1302                 src_port = OMAP_DMA_PORT_TIPB;
1303                 dest_port = OMAP_DMA_PORT_EMIFF;
1304         }
1305         if (cpu_class_is_omap2())
1306                 sync_dev = mcbsp->dma_tx_sync;
1307
1308         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1309                                      OMAP_DMA_DATA_TYPE_S16,
1310                                      length >> 1, 1,
1311                                      OMAP_DMA_SYNC_ELEMENT,
1312          sync_dev, 0);
1313
1314         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1315                                  src_port,
1316                                  OMAP_DMA_AMODE_CONSTANT,
1317                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1318                                  0, 0);
1319
1320         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1321                                 dest_port,
1322                                 OMAP_DMA_AMODE_POST_INC,
1323                                 buffer,
1324                                 0, 0);
1325
1326         omap_start_dma(mcbsp->dma_tx_lch);
1327         wait_for_completion(&mcbsp->tx_dma_completion);
1328
1329         return 0;
1330 }
1331 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1332
1333 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1334                                 unsigned int length)
1335 {
1336         struct omap_mcbsp *mcbsp;
1337         int dma_rx_ch;
1338         int src_port = 0;
1339         int dest_port = 0;
1340         int sync_dev = 0;
1341
1342         if (!omap_mcbsp_check_valid_id(id)) {
1343                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1344                 return -ENODEV;
1345         }
1346         mcbsp = id_to_mcbsp_ptr(id);
1347
1348         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1349                                 omap_mcbsp_rx_dma_callback,
1350                                 mcbsp,
1351                                 &dma_rx_ch)) {
1352                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1353                                 "McBSP%d RX. Trying IRQ based RX\n",
1354                                 mcbsp->id);
1355                 return -EAGAIN;
1356         }
1357         mcbsp->dma_rx_lch = dma_rx_ch;
1358
1359         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1360                 dma_rx_ch);
1361
1362         init_completion(&mcbsp->rx_dma_completion);
1363
1364         if (cpu_class_is_omap1()) {
1365                 src_port = OMAP_DMA_PORT_TIPB;
1366                 dest_port = OMAP_DMA_PORT_EMIFF;
1367         }
1368         if (cpu_class_is_omap2())
1369                 sync_dev = mcbsp->dma_rx_sync;
1370
1371         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1372                                         OMAP_DMA_DATA_TYPE_S16,
1373                                         length >> 1, 1,
1374                                         OMAP_DMA_SYNC_ELEMENT,
1375                                         sync_dev, 0);
1376
1377         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1378                                 src_port,
1379                                 OMAP_DMA_AMODE_CONSTANT,
1380                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1381                                 0, 0);
1382
1383         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1384                                         dest_port,
1385                                         OMAP_DMA_AMODE_POST_INC,
1386                                         buffer,
1387                                         0, 0);
1388
1389         omap_start_dma(mcbsp->dma_rx_lch);
1390         wait_for_completion(&mcbsp->rx_dma_completion);
1391
1392         return 0;
1393 }
1394 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1395
1396 /*
1397  * SPI wrapper.
1398  * Since SPI setup is much simpler than the generic McBSP one,
1399  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1400  * Once this is done, you can call omap_mcbsp_start().
1401  */
1402 void omap_mcbsp_set_spi_mode(unsigned int id,
1403                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1404 {
1405         struct omap_mcbsp *mcbsp;
1406         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1407
1408         if (!omap_mcbsp_check_valid_id(id)) {
1409                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1410                 return;
1411         }
1412         mcbsp = id_to_mcbsp_ptr(id);
1413
1414         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1415
1416         /* SPI has only one frame */
1417         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1418         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1419
1420         /* Clock stop mode */
1421         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1422                 mcbsp_cfg.spcr1 |= (1 << 12);
1423         else
1424                 mcbsp_cfg.spcr1 |= (3 << 11);
1425
1426         /* Set clock parities */
1427         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1428                 mcbsp_cfg.pcr0 |= CLKRP;
1429         else
1430                 mcbsp_cfg.pcr0 &= ~CLKRP;
1431
1432         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1433                 mcbsp_cfg.pcr0 &= ~CLKXP;
1434         else
1435                 mcbsp_cfg.pcr0 |= CLKXP;
1436
1437         /* Set SCLKME to 0 and CLKSM to 1 */
1438         mcbsp_cfg.pcr0 &= ~SCLKME;
1439         mcbsp_cfg.srgr2 |= CLKSM;
1440
1441         /* Set FSXP */
1442         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1443                 mcbsp_cfg.pcr0 &= ~FSXP;
1444         else
1445                 mcbsp_cfg.pcr0 |= FSXP;
1446
1447         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1448                 mcbsp_cfg.pcr0 |= CLKXM;
1449                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1450                 mcbsp_cfg.pcr0 |= FSXM;
1451                 mcbsp_cfg.srgr2 &= ~FSGM;
1452                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1453                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1454         } else {
1455                 mcbsp_cfg.pcr0 &= ~CLKXM;
1456                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1457                 mcbsp_cfg.pcr0 &= ~FSXM;
1458                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1459                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1460         }
1461
1462         mcbsp_cfg.xcr2 &= ~XPHASE;
1463         mcbsp_cfg.rcr2 &= ~RPHASE;
1464
1465         omap_mcbsp_config(id, &mcbsp_cfg);
1466 }
1467 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1468
1469 #ifdef CONFIG_ARCH_OMAP3
1470 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1471 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1472 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1473 static ssize_t prop##_show(struct device *dev,                          \
1474                         struct device_attribute *attr, char *buf)       \
1475 {                                                                       \
1476         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1477                                                                         \
1478         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1479 }                                                                       \
1480                                                                         \
1481 static ssize_t prop##_store(struct device *dev,                         \
1482                                 struct device_attribute *attr,          \
1483                                 const char *buf, size_t size)           \
1484 {                                                                       \
1485         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1486         unsigned long val;                                              \
1487         int status;                                                     \
1488                                                                         \
1489         status = strict_strtoul(buf, 0, &val);                          \
1490         if (status)                                                     \
1491                 return status;                                          \
1492                                                                         \
1493         if (!valid_threshold(mcbsp, val))                               \
1494                 return -EDOM;                                           \
1495                                                                         \
1496         mcbsp->prop = val;                                              \
1497         return size;                                                    \
1498 }                                                                       \
1499                                                                         \
1500 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1501
1502 THRESHOLD_PROP_BUILDER(max_tx_thres);
1503 THRESHOLD_PROP_BUILDER(max_rx_thres);
1504
1505 static const char *dma_op_modes[] = {
1506         "element", "threshold", "frame",
1507 };
1508
1509 static ssize_t dma_op_mode_show(struct device *dev,
1510                         struct device_attribute *attr, char *buf)
1511 {
1512         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1513         int dma_op_mode, i = 0;
1514         ssize_t len = 0;
1515         const char * const *s;
1516
1517         dma_op_mode = mcbsp->dma_op_mode;
1518
1519         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1520                 if (dma_op_mode == i)
1521                         len += sprintf(buf + len, "[%s] ", *s);
1522                 else
1523                         len += sprintf(buf + len, "%s ", *s);
1524         }
1525         len += sprintf(buf + len, "\n");
1526
1527         return len;
1528 }
1529
1530 static ssize_t dma_op_mode_store(struct device *dev,
1531                                 struct device_attribute *attr,
1532                                 const char *buf, size_t size)
1533 {
1534         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1535         const char * const *s;
1536         int i = 0;
1537
1538         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1539                 if (sysfs_streq(buf, *s))
1540                         break;
1541
1542         if (i == ARRAY_SIZE(dma_op_modes))
1543                 return -EINVAL;
1544
1545         spin_lock_irq(&mcbsp->lock);
1546         if (!mcbsp->free) {
1547                 size = -EBUSY;
1548                 goto unlock;
1549         }
1550         mcbsp->dma_op_mode = i;
1551
1552 unlock:
1553         spin_unlock_irq(&mcbsp->lock);
1554
1555         return size;
1556 }
1557
1558 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1559
1560 static ssize_t st_taps_show(struct device *dev,
1561                             struct device_attribute *attr, char *buf)
1562 {
1563         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1564         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1565         ssize_t status = 0;
1566         int i;
1567
1568         spin_lock_irq(&mcbsp->lock);
1569         for (i = 0; i < st_data->nr_taps; i++)
1570                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1571                                   st_data->taps[i]);
1572         if (i)
1573                 status += sprintf(&buf[status], "\n");
1574         spin_unlock_irq(&mcbsp->lock);
1575
1576         return status;
1577 }
1578
1579 static ssize_t st_taps_store(struct device *dev,
1580                              struct device_attribute *attr,
1581                              const char *buf, size_t size)
1582 {
1583         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1584         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1585         int val, tmp, status, i = 0;
1586
1587         spin_lock_irq(&mcbsp->lock);
1588         memset(st_data->taps, 0, sizeof(st_data->taps));
1589         st_data->nr_taps = 0;
1590
1591         do {
1592                 status = sscanf(buf, "%d%n", &val, &tmp);
1593                 if (status < 0 || status == 0) {
1594                         size = -EINVAL;
1595                         goto out;
1596                 }
1597                 if (val < -32768 || val > 32767) {
1598                         size = -EINVAL;
1599                         goto out;
1600                 }
1601                 st_data->taps[i++] = val;
1602                 buf += tmp;
1603                 if (*buf != ',')
1604                         break;
1605                 buf++;
1606         } while (1);
1607
1608         st_data->nr_taps = i;
1609
1610 out:
1611         spin_unlock_irq(&mcbsp->lock);
1612
1613         return size;
1614 }
1615
1616 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1617
1618 static const struct attribute *additional_attrs[] = {
1619         &dev_attr_max_tx_thres.attr,
1620         &dev_attr_max_rx_thres.attr,
1621         &dev_attr_dma_op_mode.attr,
1622         NULL,
1623 };
1624
1625 static const struct attribute_group additional_attr_group = {
1626         .attrs = (struct attribute **)additional_attrs,
1627 };
1628
1629 static inline int __devinit omap_additional_add(struct device *dev)
1630 {
1631         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1632 }
1633
1634 static inline void __devexit omap_additional_remove(struct device *dev)
1635 {
1636         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1637 }
1638
1639 static const struct attribute *sidetone_attrs[] = {
1640         &dev_attr_st_taps.attr,
1641         NULL,
1642 };
1643
1644 static const struct attribute_group sidetone_attr_group = {
1645         .attrs = (struct attribute **)sidetone_attrs,
1646 };
1647
1648 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1649 {
1650         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1651         struct omap_mcbsp_st_data *st_data;
1652         int err;
1653
1654         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1655         if (!st_data) {
1656                 err = -ENOMEM;
1657                 goto err1;
1658         }
1659
1660         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1661         if (!st_data->io_base_st) {
1662                 err = -ENOMEM;
1663                 goto err2;
1664         }
1665
1666         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1667         if (err)
1668                 goto err3;
1669
1670         mcbsp->st_data = st_data;
1671         return 0;
1672
1673 err3:
1674         iounmap(st_data->io_base_st);
1675 err2:
1676         kfree(st_data);
1677 err1:
1678         return err;
1679
1680 }
1681
1682 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1683 {
1684         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1685
1686         if (st_data) {
1687                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1688                 iounmap(st_data->io_base_st);
1689                 kfree(st_data);
1690         }
1691 }
1692
1693 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1694 {
1695         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1696         if (cpu_is_omap34xx()) {
1697                 /*
1698                  * Initially configure the maximum thresholds to a safe value.
1699                  * The McBSP FIFO usage with these values should not go under
1700                  * 16 locations.
1701                  * If the whole FIFO without safety buffer is used, than there
1702                  * is a possibility that the DMA will be not able to push the
1703                  * new data on time, causing channel shifts in runtime.
1704                  */
1705                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1706                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1707                 /*
1708                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1709                  * for mcbsp2 instances.
1710                  */
1711                 if (omap_additional_add(mcbsp->dev))
1712                         dev_warn(mcbsp->dev,
1713                                 "Unable to create additional controls\n");
1714
1715                 if (mcbsp->id == 2 || mcbsp->id == 3)
1716                         if (omap_st_add(mcbsp))
1717                                 dev_warn(mcbsp->dev,
1718                                  "Unable to create sidetone controls\n");
1719
1720         } else {
1721                 mcbsp->max_tx_thres = -EINVAL;
1722                 mcbsp->max_rx_thres = -EINVAL;
1723         }
1724 }
1725
1726 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1727 {
1728         if (cpu_is_omap34xx()) {
1729                 omap_additional_remove(mcbsp->dev);
1730
1731                 if (mcbsp->id == 2 || mcbsp->id == 3)
1732                         omap_st_remove(mcbsp);
1733         }
1734 }
1735 #else
1736 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1737 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1738 #endif /* CONFIG_ARCH_OMAP3 */
1739
1740 /*
1741  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1742  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1743  */
1744 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1745 {
1746         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1747         struct omap_mcbsp *mcbsp;
1748         int id = pdev->id - 1;
1749         int ret = 0;
1750
1751         if (!pdata) {
1752                 dev_err(&pdev->dev, "McBSP device initialized without"
1753                                 "platform data\n");
1754                 ret = -EINVAL;
1755                 goto exit;
1756         }
1757
1758         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1759
1760         if (id >= omap_mcbsp_count) {
1761                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1762                 ret = -EINVAL;
1763                 goto exit;
1764         }
1765
1766         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1767         if (!mcbsp) {
1768                 ret = -ENOMEM;
1769                 goto exit;
1770         }
1771
1772         spin_lock_init(&mcbsp->lock);
1773         mcbsp->id = id + 1;
1774         mcbsp->free = 1;
1775         mcbsp->dma_tx_lch = -1;
1776         mcbsp->dma_rx_lch = -1;
1777
1778         mcbsp->phys_base = pdata->phys_base;
1779         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1780         if (!mcbsp->io_base) {
1781                 ret = -ENOMEM;
1782                 goto err_ioremap;
1783         }
1784
1785         /* Default I/O is IRQ based */
1786         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1787         mcbsp->tx_irq = pdata->tx_irq;
1788         mcbsp->rx_irq = pdata->rx_irq;
1789         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1790         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1791
1792         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1793         if (IS_ERR(mcbsp->iclk)) {
1794                 ret = PTR_ERR(mcbsp->iclk);
1795                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1796                 goto err_iclk;
1797         }
1798
1799         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1800         if (IS_ERR(mcbsp->fclk)) {
1801                 ret = PTR_ERR(mcbsp->fclk);
1802                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1803                 goto err_fclk;
1804         }
1805
1806         mcbsp->pdata = pdata;
1807         mcbsp->dev = &pdev->dev;
1808         mcbsp_ptr[id] = mcbsp;
1809         platform_set_drvdata(pdev, mcbsp);
1810
1811         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1812         omap34xx_device_init(mcbsp);
1813
1814         return 0;
1815
1816 err_fclk:
1817         clk_put(mcbsp->iclk);
1818 err_iclk:
1819         iounmap(mcbsp->io_base);
1820 err_ioremap:
1821         kfree(mcbsp);
1822 exit:
1823         return ret;
1824 }
1825
1826 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1827 {
1828         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1829
1830         platform_set_drvdata(pdev, NULL);
1831         if (mcbsp) {
1832
1833                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1834                                 mcbsp->pdata->ops->free)
1835                         mcbsp->pdata->ops->free(mcbsp->id);
1836
1837                 omap34xx_device_exit(mcbsp);
1838
1839                 clk_disable(mcbsp->fclk);
1840                 clk_disable(mcbsp->iclk);
1841                 clk_put(mcbsp->fclk);
1842                 clk_put(mcbsp->iclk);
1843
1844                 iounmap(mcbsp->io_base);
1845
1846                 mcbsp->fclk = NULL;
1847                 mcbsp->iclk = NULL;
1848                 mcbsp->free = 0;
1849                 mcbsp->dev = NULL;
1850         }
1851
1852         return 0;
1853 }
1854
1855 static struct platform_driver omap_mcbsp_driver = {
1856         .probe          = omap_mcbsp_probe,
1857         .remove         = __devexit_p(omap_mcbsp_remove),
1858         .driver         = {
1859                 .name   = "omap-mcbsp",
1860         },
1861 };
1862
1863 int __init omap_mcbsp_init(void)
1864 {
1865         /* Register the McBSP driver */
1866         return platform_driver_register(&omap_mcbsp_driver);
1867 }