omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2
[linux-2.6.git] / arch / arm / plat-omap / include / plat / mux.h
1 /*
2  * arch/arm/plat-omap/include/mach/mux.h
3  *
4  * Table of the Omap register configurations for the FUNC_MUX and
5  * PULL_DWN combinations.
6  *
7  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8  * Copyright (C) 2003 - 2008 Nokia Corporation
9  *
10  * Written by Tony Lindgren
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25  *
26  * NOTE: Please use the following naming style for new pin entries.
27  *       For example, W8_1610_MMC2_DAT0, where:
28  *       - W8        = ball
29  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
30  *       - MMC2_DAT0 = function
31  */
32
33 #ifndef __ASM_ARCH_MUX_H
34 #define __ASM_ARCH_MUX_H
35
36 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
37 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
38
39 #ifdef  CONFIG_OMAP_MUX_DEBUG
40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
42                                         .mask_offset = mode_offset, \
43                                         .mask = mode,
44
45 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
46                                         .pull_reg = PULL_DWN_CTRL_##reg, \
47                                         .pull_bit = bit, \
48                                         .pull_val = status,
49
50 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
51                                         .pu_pd_reg = PU_PD_SEL_##reg, \
52                                         .pu_pd_val = status,
53
54 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
56                                         .mask_offset = mode_offset, \
57                                         .mask = mode,
58
59 #define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60                                         .pull_reg = OMAP7XX_IO_CONF_##reg, \
61                                         .pull_bit = bit, \
62                                         .pull_val = status,
63
64 #else
65
66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
67                                         .mask_offset = mode_offset, \
68                                         .mask = mode,
69
70 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
71                                         .pull_bit = bit, \
72                                         .pull_val = status,
73
74 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
75                                         .pu_pd_val = status,
76
77 #define MUX_REG_7XX(reg, mode_offset, mode) \
78                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
79                                         .mask_offset = mode_offset, \
80                                         .mask = mode,
81
82 #define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
83                                         .pull_bit = bit, \
84                                         .pull_val = status,
85
86 #endif /* CONFIG_OMAP_MUX_DEBUG */
87
88 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
89                 pull_reg, pull_bit, pull_status,        \
90                 pu_pd_reg, pu_pd_status, debug_status)  \
91 {                                                       \
92         .name =  desc,                                  \
93         .debug = debug_status,                          \
94         MUX_REG(mux_reg, mode_offset, mode)             \
95         PULL_REG(pull_reg, pull_bit, pull_status)       \
96         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
97 },
98
99
100 /*
101  * OMAP730/850 has a slightly different config for the pin mux.
102  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
103  *   not the FUNC_MUX_CTRL_x regs from hardware.h
104  * - for pull-up/down, only has one enable bit which is is in the same register
105  *   as mux config
106  */
107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
108                    pull_bit, pull_status, debug_status)\
109 {                                                       \
110         .name =  desc,                                  \
111         .debug = debug_status,                          \
112         MUX_REG_7XX(mux_reg, mode_offset, mode)         \
113         PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
114         PU_PD_REG(NA, 0)                \
115 },
116
117 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
118                                 pull_en, pull_mode, dbg)        \
119 {                                                               \
120         .name           = desc,                                 \
121         .debug          = dbg,                                  \
122         .mux_reg        = reg_offset,                           \
123         .mask           = mode,                                 \
124         .pull_val       = pull_en,                              \
125         .pu_pd_val      = pull_mode,                            \
126 },
127
128 /* 24xx/34xx mux bit defines */
129 #define OMAP2_PULL_ENA          (1 << 3)
130 #define OMAP2_PULL_UP           (1 << 4)
131 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
132
133 /* 34xx specific mux bit defines */
134 #define OMAP3_INPUT_EN          (1 << 8)
135 #define OMAP3_OFF_EN            (1 << 9)
136 #define OMAP3_OFFOUT_EN         (1 << 10)
137 #define OMAP3_OFFOUT_VAL        (1 << 11)
138 #define OMAP3_OFF_PULL_EN       (1 << 12)
139 #define OMAP3_OFF_PULL_UP       (1 << 13)
140 #define OMAP3_WAKEUP_EN         (1 << 14)
141
142 /* 34xx mux mode options for each pin. See TRM for options */
143 #define OMAP34XX_MUX_MODE0      0
144 #define OMAP34XX_MUX_MODE1      1
145 #define OMAP34XX_MUX_MODE2      2
146 #define OMAP34XX_MUX_MODE3      3
147 #define OMAP34XX_MUX_MODE4      4
148 #define OMAP34XX_MUX_MODE5      5
149 #define OMAP34XX_MUX_MODE6      6
150 #define OMAP34XX_MUX_MODE7      7
151
152 /* 34xx active pin states */
153 #define OMAP34XX_PIN_OUTPUT             0
154 #define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
155 #define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156                                                 | OMAP2_PULL_UP)
157 #define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159 /* 34xx off mode states */
160 #define OMAP34XX_PIN_OFF_NONE           0
161 #define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162                                                 | OMAP3_OFFOUT_VAL)
163 #define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164 #define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165                                                 | OMAP3_OFF_PULL_UP)
166 #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167 #define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
168
169 #define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
170         .name           = desc,                                 \
171         .debug          = 0,                                    \
172         .mux_reg        = reg_offset,                           \
173         .mux_val        = mux_value                             \
174 },
175
176 struct pin_config {
177         char                    *name;
178         const unsigned int      mux_reg;
179         unsigned char           debug;
180
181 #if     defined(CONFIG_ARCH_OMAP34XX)
182         u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
183 #endif
184
185 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
186         const unsigned char mask_offset;
187         const unsigned char mask;
188
189         const char *pull_name;
190         const unsigned int pull_reg;
191         const unsigned char pull_val;
192         const unsigned char pull_bit;
193
194         const char *pu_pd_name;
195         const unsigned int pu_pd_reg;
196         const unsigned char pu_pd_val;
197 #endif
198
199 #if     defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200         const char *mux_reg_name;
201 #endif
202
203 };
204
205 enum omap7xx_index {
206         /* OMAP 730 keyboard */
207         E2_7XX_KBR0,
208         J7_7XX_KBR1,
209         E1_7XX_KBR2,
210         F3_7XX_KBR3,
211         D2_7XX_KBR4,
212         C2_7XX_KBC0,
213         D3_7XX_KBC1,
214         E4_7XX_KBC2,
215         F4_7XX_KBC3,
216         E3_7XX_KBC4,
217
218         /* USB */
219         AA17_7XX_USB_DM,
220         W16_7XX_USB_PU_EN,
221         W17_7XX_USB_VBUSI,
222 };
223
224 enum omap1xxx_index {
225         /* UART1 (BT_UART_GATING)*/
226         UART1_TX = 0,
227         UART1_RTS,
228
229         /* UART2 (COM_UART_GATING)*/
230         UART2_TX,
231         UART2_RX,
232         UART2_CTS,
233         UART2_RTS,
234
235         /* UART3 (GIGA_UART_GATING) */
236         UART3_TX,
237         UART3_RX,
238         UART3_CTS,
239         UART3_RTS,
240         UART3_CLKREQ,
241         UART3_BCLK,     /* 12MHz clock out */
242         Y15_1610_UART3_RTS,
243
244         /* PWT & PWL */
245         PWT,
246         PWL,
247
248         /* USB master generic */
249         R18_USB_VBUS,
250         R18_1510_USB_GPIO0,
251         W4_USB_PUEN,
252         W4_USB_CLKO,
253         W4_USB_HIGHZ,
254         W4_GPIO58,
255
256         /* USB1 master */
257         USB1_SUSP,
258         USB1_SEO,
259         W13_1610_USB1_SE0,
260         USB1_TXEN,
261         USB1_TXD,
262         USB1_VP,
263         USB1_VM,
264         USB1_RCV,
265         USB1_SPEED,
266         R13_1610_USB1_SPEED,
267         R13_1710_USB1_SE0,
268
269         /* USB2 master */
270         USB2_SUSP,
271         USB2_VP,
272         USB2_TXEN,
273         USB2_VM,
274         USB2_RCV,
275         USB2_SEO,
276         USB2_TXD,
277
278         /* OMAP-1510 GPIO */
279         R18_1510_GPIO0,
280         R19_1510_GPIO1,
281         M14_1510_GPIO2,
282
283         /* OMAP1610 GPIO */
284         P18_1610_GPIO3,
285         Y15_1610_GPIO17,
286
287         /* OMAP-1710 GPIO */
288         R18_1710_GPIO0,
289         V2_1710_GPIO10,
290         N21_1710_GPIO14,
291         W15_1710_GPIO40,
292
293         /* MPUIO */
294         MPUIO2,
295         N15_1610_MPUIO2,
296         MPUIO4,
297         MPUIO5,
298         T20_1610_MPUIO5,
299         W11_1610_MPUIO6,
300         V10_1610_MPUIO7,
301         W11_1610_MPUIO9,
302         V10_1610_MPUIO10,
303         W10_1610_MPUIO11,
304         E20_1610_MPUIO13,
305         U20_1610_MPUIO14,
306         E19_1610_MPUIO15,
307
308         /* MCBSP2 */
309         MCBSP2_CLKR,
310         MCBSP2_CLKX,
311         MCBSP2_DR,
312         MCBSP2_DX,
313         MCBSP2_FSR,
314         MCBSP2_FSX,
315
316         /* MCBSP3 */
317         MCBSP3_CLKX,
318
319         /* Misc ballouts */
320         BALLOUT_V8_ARMIO3,
321         N20_HDQ,
322
323         /* OMAP-1610 MMC2 */
324         W8_1610_MMC2_DAT0,
325         V8_1610_MMC2_DAT1,
326         W15_1610_MMC2_DAT2,
327         R10_1610_MMC2_DAT3,
328         Y10_1610_MMC2_CLK,
329         Y8_1610_MMC2_CMD,
330         V9_1610_MMC2_CMDDIR,
331         V5_1610_MMC2_DATDIR0,
332         W19_1610_MMC2_DATDIR1,
333         R18_1610_MMC2_CLKIN,
334
335         /* OMAP-1610 External Trace Interface */
336         M19_1610_ETM_PSTAT0,
337         L15_1610_ETM_PSTAT1,
338         L18_1610_ETM_PSTAT2,
339         L19_1610_ETM_D0,
340         J19_1610_ETM_D6,
341         J18_1610_ETM_D7,
342
343         /* OMAP16XX GPIO */
344         P20_1610_GPIO4,
345         V9_1610_GPIO7,
346         W8_1610_GPIO9,
347         N20_1610_GPIO11,
348         N19_1610_GPIO13,
349         P10_1610_GPIO22,
350         V5_1610_GPIO24,
351         AA20_1610_GPIO_41,
352         W19_1610_GPIO48,
353         M7_1610_GPIO62,
354         V14_16XX_GPIO37,
355         R9_16XX_GPIO18,
356         L14_16XX_GPIO49,
357
358         /* OMAP-1610 uWire */
359         V19_1610_UWIRE_SCLK,
360         U18_1610_UWIRE_SDI,
361         W21_1610_UWIRE_SDO,
362         N14_1610_UWIRE_CS0,
363         P15_1610_UWIRE_CS3,
364         N15_1610_UWIRE_CS1,
365
366         /* OMAP-1610 SPI */
367         U19_1610_SPIF_SCK,
368         U18_1610_SPIF_DIN,
369         P20_1610_SPIF_DIN,
370         W21_1610_SPIF_DOUT,
371         R18_1610_SPIF_DOUT,
372         N14_1610_SPIF_CS0,
373         N15_1610_SPIF_CS1,
374         T19_1610_SPIF_CS2,
375         P15_1610_SPIF_CS3,
376
377         /* OMAP-1610 Flash */
378         L3_1610_FLASH_CS2B_OE,
379         M8_1610_FLASH_CS2B_WE,
380
381         /* First MMC */
382         MMC_CMD,
383         MMC_DAT1,
384         MMC_DAT2,
385         MMC_DAT0,
386         MMC_CLK,
387         MMC_DAT3,
388
389         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
390         M15_1710_MMC_CLKI,
391         P19_1710_MMC_CMDDIR,
392         P20_1710_MMC_DATDIR0,
393
394         /* OMAP-1610 USB0 alternate pin configuration */
395         W9_USB0_TXEN,
396         AA9_USB0_VP,
397         Y5_USB0_RCV,
398         R9_USB0_VM,
399         V6_USB0_TXD,
400         W5_USB0_SE0,
401         V9_USB0_SPEED,
402         V9_USB0_SUSP,
403
404         /* USB2 */
405         W9_USB2_TXEN,
406         AA9_USB2_VP,
407         Y5_USB2_RCV,
408         R9_USB2_VM,
409         V6_USB2_TXD,
410         W5_USB2_SE0,
411
412         /* 16XX UART */
413         R13_1610_UART1_TX,
414         V14_16XX_UART1_RX,
415         R14_1610_UART1_CTS,
416         AA15_1610_UART1_RTS,
417         R9_16XX_UART2_RX,
418         L14_16XX_UART3_RX,
419
420         /* I2C OMAP-1610 */
421         I2C_SCL,
422         I2C_SDA,
423
424         /* Keypad */
425         F18_1610_KBC0,
426         D20_1610_KBC1,
427         D19_1610_KBC2,
428         E18_1610_KBC3,
429         C21_1610_KBC4,
430         G18_1610_KBR0,
431         F19_1610_KBR1,
432         H14_1610_KBR2,
433         E20_1610_KBR3,
434         E19_1610_KBR4,
435         N19_1610_KBR5,
436
437         /* Power management */
438         T20_1610_LOW_PWR,
439
440         /* MCLK Settings */
441         V5_1710_MCLK_ON,
442         V5_1710_MCLK_OFF,
443         R10_1610_MCLK_ON,
444         R10_1610_MCLK_OFF,
445
446         /* CompactFlash controller */
447         P11_1610_CF_CD2,
448         R11_1610_CF_IOIS16,
449         V10_1610_CF_IREQ,
450         W10_1610_CF_RESET,
451         W11_1610_CF_CD1,
452
453         /* parallel camera */
454         J15_1610_CAM_LCLK,
455         J18_1610_CAM_D7,
456         J19_1610_CAM_D6,
457         J14_1610_CAM_D5,
458         K18_1610_CAM_D4,
459         K19_1610_CAM_D3,
460         K15_1610_CAM_D2,
461         K14_1610_CAM_D1,
462         L19_1610_CAM_D0,
463         L18_1610_CAM_VS,
464         L15_1610_CAM_HS,
465         M19_1610_CAM_RSTZ,
466         Y15_1610_CAM_OUTCLK,
467
468         /* serial camera */
469         H19_1610_CAM_EXCLK,
470         Y12_1610_CCP_CLKP,
471         W13_1610_CCP_CLKM,
472         W14_1610_CCP_DATAP,
473         Y14_1610_CCP_DATAM,
474
475 };
476
477 enum omap24xx_index {
478         /* 24xx I2C */
479         M19_24XX_I2C1_SCL,
480         L15_24XX_I2C1_SDA,
481         J15_24XX_I2C2_SCL,
482         H19_24XX_I2C2_SDA,
483
484         /* 24xx Menelaus interrupt */
485         W19_24XX_SYS_NIRQ,
486
487         /* 24xx clock */
488         W14_24XX_SYS_CLKOUT,
489
490         /* 24xx GPMC chipselects, wait pin monitoring */
491         E2_GPMC_NCS2,
492         L2_GPMC_NCS7,
493         L3_GPMC_WAIT0,
494         N7_GPMC_WAIT1,
495         M1_GPMC_WAIT2,
496         P1_GPMC_WAIT3,
497
498         /* 242X McBSP */
499         Y15_24XX_MCBSP2_CLKX,
500         R14_24XX_MCBSP2_FSX,
501         W15_24XX_MCBSP2_DR,
502         V15_24XX_MCBSP2_DX,
503
504         /* 24xx GPIO */
505         M21_242X_GPIO11,
506         P21_242X_GPIO12,
507         AA10_242X_GPIO13,
508         AA6_242X_GPIO14,
509         AA4_242X_GPIO15,
510         Y11_242X_GPIO16,
511         AA12_242X_GPIO17,
512         AA8_242X_GPIO58,
513         Y20_24XX_GPIO60,
514         W4__24XX_GPIO74,
515         N15_24XX_GPIO85,
516         M15_24XX_GPIO92,
517         P20_24XX_GPIO93,
518         P18_24XX_GPIO95,
519         M18_24XX_GPIO96,
520         L14_24XX_GPIO97,
521         J15_24XX_GPIO99,
522         V14_24XX_GPIO117,
523         P14_24XX_GPIO125,
524
525         /* 242x DBG GPIO */
526         V4_242X_GPIO49,
527         W2_242X_GPIO50,
528         U4_242X_GPIO51,
529         V3_242X_GPIO52,
530         V2_242X_GPIO53,
531         V6_242X_GPIO53,
532         T4_242X_GPIO54,
533         Y4_242X_GPIO54,
534         T3_242X_GPIO55,
535         U2_242X_GPIO56,
536
537         /* 24xx external DMA requests */
538         AA10_242X_DMAREQ0,
539         AA6_242X_DMAREQ1,
540         E4_242X_DMAREQ2,
541         G4_242X_DMAREQ3,
542         D3_242X_DMAREQ4,
543         E3_242X_DMAREQ5,
544
545         /* UART3 */
546         K15_24XX_UART3_TX,
547         K14_24XX_UART3_RX,
548
549         /* MMC/SDIO */
550         G19_24XX_MMC_CLKO,
551         H18_24XX_MMC_CMD,
552         F20_24XX_MMC_DAT0,
553         H14_24XX_MMC_DAT1,
554         E19_24XX_MMC_DAT2,
555         D19_24XX_MMC_DAT3,
556         F19_24XX_MMC_DAT_DIR0,
557         E20_24XX_MMC_DAT_DIR1,
558         F18_24XX_MMC_DAT_DIR2,
559         E18_24XX_MMC_DAT_DIR3,
560         G18_24XX_MMC_CMD_DIR,
561         H15_24XX_MMC_CLKI,
562
563         /* Full speed USB */
564         J20_24XX_USB0_PUEN,
565         J19_24XX_USB0_VP,
566         K20_24XX_USB0_VM,
567         J18_24XX_USB0_RCV,
568         K19_24XX_USB0_TXEN,
569         J14_24XX_USB0_SE0,
570         K18_24XX_USB0_DAT,
571
572         N14_24XX_USB1_SE0,
573         W12_24XX_USB1_SE0,
574         P15_24XX_USB1_DAT,
575         R13_24XX_USB1_DAT,
576         W20_24XX_USB1_TXEN,
577         P13_24XX_USB1_TXEN,
578         V19_24XX_USB1_RCV,
579         V12_24XX_USB1_RCV,
580
581         AA10_24XX_USB2_SE0,
582         Y11_24XX_USB2_DAT,
583         AA12_24XX_USB2_TXEN,
584         AA6_24XX_USB2_RCV,
585         AA4_24XX_USB2_TLLSE0,
586
587         /* Keypad GPIO*/
588         T19_24XX_KBR0,
589         R19_24XX_KBR1,
590         V18_24XX_KBR2,
591         M21_24XX_KBR3,
592         E5__24XX_KBR4,
593         M18_24XX_KBR5,
594         R20_24XX_KBC0,
595         M14_24XX_KBC1,
596         H19_24XX_KBC2,
597         V17_24XX_KBC3,
598         P21_24XX_KBC4,
599         L14_24XX_KBC5,
600         N19_24XX_KBC6,
601
602         /* 24xx Menelaus Keypad GPIO */
603         B3__24XX_KBR5,
604         AA4_24XX_KBC2,
605         B13_24XX_KBC6,
606
607         /* 2430 USB */
608         AD9_2430_USB0_PUEN,
609         Y11_2430_USB0_VP,
610         AD7_2430_USB0_VM,
611         AE7_2430_USB0_RCV,
612         AD4_2430_USB0_TXEN,
613         AF9_2430_USB0_SE0,
614         AE6_2430_USB0_DAT,
615         AD24_2430_USB1_SE0,
616         AB24_2430_USB1_RCV,
617         Y25_2430_USB1_TXEN,
618         AA26_2430_USB1_DAT,
619
620         /* 2430 HS-USB */
621         AD9_2430_USB0HS_DATA3,
622         Y11_2430_USB0HS_DATA4,
623         AD7_2430_USB0HS_DATA5,
624         AE7_2430_USB0HS_DATA6,
625         AD4_2430_USB0HS_DATA2,
626         AF9_2430_USB0HS_DATA0,
627         AE6_2430_USB0HS_DATA1,
628         AE8_2430_USB0HS_CLK,
629         AD8_2430_USB0HS_DIR,
630         AE5_2430_USB0HS_STP,
631         AE9_2430_USB0HS_NXT,
632         AC7_2430_USB0HS_DATA7,
633
634         /* 2430 McBSP */
635         AD6_2430_MCBSP_CLKS,
636
637         AB2_2430_MCBSP1_CLKR,
638         AD5_2430_MCBSP1_FSR,
639         AA1_2430_MCBSP1_DX,
640         AF3_2430_MCBSP1_DR,
641         AB3_2430_MCBSP1_FSX,
642         Y9_2430_MCBSP1_CLKX,
643
644         AC10_2430_MCBSP2_FSX,
645         AD16_2430_MCBSP2_CLX,
646         AE13_2430_MCBSP2_DX,
647         AD13_2430_MCBSP2_DR,
648         AC10_2430_MCBSP2_FSX_OFF,
649         AD16_2430_MCBSP2_CLX_OFF,
650         AE13_2430_MCBSP2_DX_OFF,
651         AD13_2430_MCBSP2_DR_OFF,
652
653         AC9_2430_MCBSP3_CLKX,
654         AE4_2430_MCBSP3_FSX,
655         AE2_2430_MCBSP3_DR,
656         AF4_2430_MCBSP3_DX,
657
658         N3_2430_MCBSP4_CLKX,
659         AD23_2430_MCBSP4_DR,
660         AB25_2430_MCBSP4_DX,
661         AC25_2430_MCBSP4_FSX,
662
663         AE16_2430_MCBSP5_CLKX,
664         AF12_2430_MCBSP5_FSX,
665         K7_2430_MCBSP5_DX,
666         M1_2430_MCBSP5_DR,
667
668         /* 2430 McSPI*/
669         Y18_2430_MCSPI1_CLK,
670         AD15_2430_MCSPI1_SIMO,
671         AE17_2430_MCSPI1_SOMI,
672         U1_2430_MCSPI1_CS0,
673
674         /* Touchscreen GPIO */
675         AF19_2430_GPIO_85,
676
677 };
678
679 enum omap34xx_index {
680         /* 34xx I2C */
681         K21_34XX_I2C1_SCL,
682         J21_34XX_I2C1_SDA,
683         AF15_34XX_I2C2_SCL,
684         AE15_34XX_I2C2_SDA,
685         AF14_34XX_I2C3_SCL,
686         AG14_34XX_I2C3_SDA,
687         AD26_34XX_I2C4_SCL,
688         AE26_34XX_I2C4_SDA,
689
690         /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
691         Y8_3430_USB1HS_PHY_CLK,
692         Y9_3430_USB1HS_PHY_STP,
693         AA14_3430_USB1HS_PHY_DIR,
694         AA11_3430_USB1HS_PHY_NXT,
695         W13_3430_USB1HS_PHY_DATA0,
696         W12_3430_USB1HS_PHY_DATA1,
697         W11_3430_USB1HS_PHY_DATA2,
698         Y11_3430_USB1HS_PHY_DATA3,
699         W9_3430_USB1HS_PHY_DATA4,
700         Y12_3430_USB1HS_PHY_DATA5,
701         W8_3430_USB1HS_PHY_DATA6,
702         Y13_3430_USB1HS_PHY_DATA7,
703
704         /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
705         AA8_3430_USB2HS_PHY_CLK,
706         AA10_3430_USB2HS_PHY_STP,
707         AA9_3430_USB2HS_PHY_DIR,
708         AB11_3430_USB2HS_PHY_NXT,
709         AB10_3430_USB2HS_PHY_DATA0,
710         AB9_3430_USB2HS_PHY_DATA1,
711         W3_3430_USB2HS_PHY_DATA2,
712         T4_3430_USB2HS_PHY_DATA3,
713         T3_3430_USB2HS_PHY_DATA4,
714         R3_3430_USB2HS_PHY_DATA5,
715         R4_3430_USB2HS_PHY_DATA6,
716         T2_3430_USB2HS_PHY_DATA7,
717
718
719         /* TLL - HSUSB: 12-pin TLL Port 1*/
720         Y8_3430_USB1HS_TLL_CLK,
721         Y9_3430_USB1HS_TLL_STP,
722         AA14_3430_USB1HS_TLL_DIR,
723         AA11_3430_USB1HS_TLL_NXT,
724         W13_3430_USB1HS_TLL_DATA0,
725         W12_3430_USB1HS_TLL_DATA1,
726         W11_3430_USB1HS_TLL_DATA2,
727         Y11_3430_USB1HS_TLL_DATA3,
728         W9_3430_USB1HS_TLL_DATA4,
729         Y12_3430_USB1HS_TLL_DATA5,
730         W8_3430_USB1HS_TLL_DATA6,
731         Y13_3430_USB1HS_TLL_DATA7,
732
733         /* TLL - HSUSB: 12-pin TLL Port 2*/
734         AA8_3430_USB2HS_TLL_CLK,
735         AA10_3430_USB2HS_TLL_STP,
736         AA9_3430_USB2HS_TLL_DIR,
737         AB11_3430_USB2HS_TLL_NXT,
738         AB10_3430_USB2HS_TLL_DATA0,
739         AB9_3430_USB2HS_TLL_DATA1,
740         W3_3430_USB2HS_TLL_DATA2,
741         T4_3430_USB2HS_TLL_DATA3,
742         T3_3430_USB2HS_TLL_DATA4,
743         R3_3430_USB2HS_TLL_DATA5,
744         R4_3430_USB2HS_TLL_DATA6,
745         T2_3430_USB2HS_TLL_DATA7,
746
747         /* TLL - HSUSB: 12-pin TLL Port 3*/
748         AA6_3430_USB3HS_TLL_CLK,
749         AB3_3430_USB3HS_TLL_STP,
750         AA3_3430_USB3HS_TLL_DIR,
751         Y3_3430_USB3HS_TLL_NXT,
752         AA5_3430_USB3HS_TLL_DATA0,
753         Y4_3430_USB3HS_TLL_DATA1,
754         Y5_3430_USB3HS_TLL_DATA2,
755         W5_3430_USB3HS_TLL_DATA3,
756         AB12_3430_USB3HS_TLL_DATA4,
757         AB13_3430_USB3HS_TLL_DATA5,
758         AA13_3430_USB3HS_TLL_DATA6,
759         AA12_3430_USB3HS_TLL_DATA7,
760
761         /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
762         AF10_3430_USB1FS_PHY_MM1_RXDP,
763         AG9_3430_USB1FS_PHY_MM1_RXDM,
764         W13_3430_USB1FS_PHY_MM1_RXRCV,
765         W12_3430_USB1FS_PHY_MM1_TXSE0,
766         W11_3430_USB1FS_PHY_MM1_TXDAT,
767         Y11_3430_USB1FS_PHY_MM1_TXEN_N,
768
769         /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
770         AF7_3430_USB2FS_PHY_MM2_RXDP,
771         AH7_3430_USB2FS_PHY_MM2_RXDM,
772         AB10_3430_USB2FS_PHY_MM2_RXRCV,
773         AB9_3430_USB2FS_PHY_MM2_TXSE0,
774         W3_3430_USB2FS_PHY_MM2_TXDAT,
775         T4_3430_USB2FS_PHY_MM2_TXEN_N,
776
777         /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
778         AH3_3430_USB3FS_PHY_MM3_RXDP,
779         AE3_3430_USB3FS_PHY_MM3_RXDM,
780         AD1_3430_USB3FS_PHY_MM3_RXRCV,
781         AE1_3430_USB3FS_PHY_MM3_TXSE0,
782         AD2_3430_USB3FS_PHY_MM3_TXDAT,
783         AC1_3430_USB3FS_PHY_MM3_TXEN_N,
784
785         /* 34xx GPIO
786          *  - normally these are bidirectional, no internal pullup/pulldown
787          *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
788          *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
789          *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
790          */
791         AF26_34XX_GPIO0,
792         AF22_34XX_GPIO9,
793         AG9_34XX_GPIO23,
794         AH8_34XX_GPIO29,
795         U8_34XX_GPIO54_OUT,
796         U8_34XX_GPIO54_DOWN,
797         L8_34XX_GPIO63,
798         G25_34XX_GPIO86_OUT,
799         AG4_34XX_GPIO134_OUT,
800         AF4_34XX_GPIO135_OUT,
801         AE4_34XX_GPIO136_OUT,
802         AF6_34XX_GPIO140_UP,
803         AE6_34XX_GPIO141,
804         AF5_34XX_GPIO142,
805         AE5_34XX_GPIO143,
806         H19_34XX_GPIO164_OUT,
807         J25_34XX_GPIO170,
808
809         /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
810         H16_34XX_SDRC_CKE0,
811         H17_34XX_SDRC_CKE1,
812
813         /* MMC1 */
814         N28_3430_MMC1_CLK,
815         M27_3430_MMC1_CMD,
816         N27_3430_MMC1_DAT0,
817         N26_3430_MMC1_DAT1,
818         N25_3430_MMC1_DAT2,
819         P28_3430_MMC1_DAT3,
820         P27_3430_MMC1_DAT4,
821         P26_3430_MMC1_DAT5,
822         R27_3430_MMC1_DAT6,
823         R25_3430_MMC1_DAT7,
824
825         /* MMC2 */
826         AE2_3430_MMC2_CLK,
827         AG5_3430_MMC2_CMD,
828         AH5_3430_MMC2_DAT0,
829         AH4_3430_MMC2_DAT1,
830         AG4_3430_MMC2_DAT2,
831         AF4_3430_MMC2_DAT3,
832
833         /* MMC3 */
834         AF10_3430_MMC3_CLK,
835         AC3_3430_MMC3_CMD,
836         AE11_3430_MMC3_DAT0,
837         AH9_3430_MMC3_DAT1,
838         AF13_3430_MMC3_DAT2,
839         AF13_3430_MMC3_DAT3,
840
841         /* SYS_NIRQ T2 INT1 */
842         AF26_34XX_SYS_NIRQ,
843 };
844
845 struct omap_mux_cfg {
846         struct pin_config       *pins;
847         unsigned long           size;
848         int                     (*cfg_reg)(const struct pin_config *cfg);
849 };
850
851 #ifdef  CONFIG_OMAP_MUX
852 /* setup pin muxing in Linux */
853 extern int omap1_mux_init(void);
854 extern int omap2_mux_init(void);
855 extern int omap_mux_register(struct omap_mux_cfg *);
856 extern int omap_cfg_reg(unsigned long reg_cfg);
857 #else
858 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
859 static inline int omap1_mux_init(void) { return 0; }
860 static inline int omap2_mux_init(void) { return 0; }
861 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
862 #endif
863
864 #endif