d17375e06a1e8f956a674b57c2659e991cb5ebaf
[linux-2.6.git] / arch / arm / plat-omap / dma.c
1 /*
2  * linux/arch/arm/plat-omap/dma.c
3  *
4  * Copyright (C) 2003 - 2008 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15  *
16  * Support functions for the OMAP internal DMA channels.
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License version 2 as
20  * published by the Free Software Foundation.
21  *
22  */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/io.h>
32
33 #include <asm/system.h>
34 #include <mach/hardware.h>
35 #include <plat/dma.h>
36
37 #include <plat/tc.h>
38
39 #undef DEBUG
40
41 #ifndef CONFIG_ARCH_OMAP1
42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
44 };
45
46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
47 #endif
48
49 #define OMAP_DMA_ACTIVE                 0x01
50 #define OMAP_DMA_CCR_EN                 (1 << 7)
51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
52
53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
54
55 static int enable_1510_mode;
56
57 static struct omap_dma_global_context_registers {
58         u32 dma_irqenable_l0;
59         u32 dma_ocp_sysconfig;
60         u32 dma_gcr;
61 } omap_dma_global_context;
62
63 struct omap_dma_lch {
64         int next_lch;
65         int dev_id;
66         u16 saved_csr;
67         u16 enabled_irqs;
68         const char *dev_name;
69         void (*callback)(int lch, u16 ch_status, void *data);
70         void *data;
71
72 #ifndef CONFIG_ARCH_OMAP1
73         /* required for Dynamic chaining */
74         int prev_linked_ch;
75         int next_linked_ch;
76         int state;
77         int chain_id;
78
79         int status;
80 #endif
81         long flags;
82 };
83
84 struct dma_link_info {
85         int *linked_dmach_q;
86         int no_of_lchs_linked;
87
88         int q_count;
89         int q_tail;
90         int q_head;
91
92         int chain_state;
93         int chain_mode;
94
95 };
96
97 static struct dma_link_info *dma_linked_lch;
98
99 #ifndef CONFIG_ARCH_OMAP1
100
101 /* Chain handling macros */
102 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
103         do {                                                            \
104                 dma_linked_lch[chain_id].q_head =                       \
105                 dma_linked_lch[chain_id].q_tail =                       \
106                 dma_linked_lch[chain_id].q_count = 0;                   \
107         } while (0)
108 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
109                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
110                 dma_linked_lch[chain_id].q_count)
111 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
112         do {                                                            \
113                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
114                 dma_linked_lch[chain_id].q_count)                       \
115         } while (0)
116 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
117                 (0 == dma_linked_lch[chain_id].q_count)
118 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
119         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
120 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
121         do {                                                            \
122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
123                 dma_linked_lch[chain_id].q_count--;                     \
124         } while (0)
125
126 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
127         do {                                                            \
128                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
129                 dma_linked_lch[chain_id].q_count++; \
130         } while (0)
131 #endif
132
133 static int dma_lch_count;
134 static int dma_chan_count;
135 static int omap_dma_reserve_channels;
136
137 static spinlock_t dma_chan_lock;
138 static struct omap_dma_lch *dma_chan;
139 static void __iomem *omap_dma_base;
140
141 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
142         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
143         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
144         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
145         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
146         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
147 };
148
149 static inline void disable_lnk(int lch);
150 static void omap_disable_channel_irq(int lch);
151 static inline void omap_enable_channel_irq(int lch);
152
153 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
154                                                 __func__);
155
156 #define dma_read(reg)                                                   \
157 ({                                                                      \
158         u32 __val;                                                      \
159         if (cpu_class_is_omap1())                                       \
160                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
161         else                                                            \
162                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
163         __val;                                                          \
164 })
165
166 #define dma_write(val, reg)                                             \
167 ({                                                                      \
168         if (cpu_class_is_omap1())                                       \
169                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
170         else                                                            \
171                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
172 })
173
174 #ifdef CONFIG_ARCH_OMAP15XX
175 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
176 int omap_dma_in_1510_mode(void)
177 {
178         return enable_1510_mode;
179 }
180 #else
181 #define omap_dma_in_1510_mode()         0
182 #endif
183
184 #ifdef CONFIG_ARCH_OMAP1
185 static inline int get_gdma_dev(int req)
186 {
187         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
188         int shift = ((req - 1) % 5) * 6;
189
190         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
191 }
192
193 static inline void set_gdma_dev(int req, int dev)
194 {
195         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
196         int shift = ((req - 1) % 5) * 6;
197         u32 l;
198
199         l = omap_readl(reg);
200         l &= ~(0x3f << shift);
201         l |= (dev - 1) << shift;
202         omap_writel(l, reg);
203 }
204 #else
205 #define set_gdma_dev(req, dev)  do {} while (0)
206 #endif
207
208 /* Omap1 only */
209 static void clear_lch_regs(int lch)
210 {
211         int i;
212         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
213
214         for (i = 0; i < 0x2c; i += 2)
215                 __raw_writew(0, lch_base + i);
216 }
217
218 void omap_set_dma_priority(int lch, int dst_port, int priority)
219 {
220         unsigned long reg;
221         u32 l;
222
223         if (cpu_class_is_omap1()) {
224                 switch (dst_port) {
225                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
226                         reg = OMAP_TC_OCPT1_PRIOR;
227                         break;
228                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
229                         reg = OMAP_TC_OCPT2_PRIOR;
230                         break;
231                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
232                         reg = OMAP_TC_EMIFF_PRIOR;
233                         break;
234                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
235                         reg = OMAP_TC_EMIFS_PRIOR;
236                         break;
237                 default:
238                         BUG();
239                         return;
240                 }
241                 l = omap_readl(reg);
242                 l &= ~(0xf << 8);
243                 l |= (priority & 0xf) << 8;
244                 omap_writel(l, reg);
245         }
246
247         if (cpu_class_is_omap2()) {
248                 u32 ccr;
249
250                 ccr = dma_read(CCR(lch));
251                 if (priority)
252                         ccr |= (1 << 6);
253                 else
254                         ccr &= ~(1 << 6);
255                 dma_write(ccr, CCR(lch));
256         }
257 }
258 EXPORT_SYMBOL(omap_set_dma_priority);
259
260 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
261                                   int frame_count, int sync_mode,
262                                   int dma_trigger, int src_or_dst_synch)
263 {
264         u32 l;
265
266         l = dma_read(CSDP(lch));
267         l &= ~0x03;
268         l |= data_type;
269         dma_write(l, CSDP(lch));
270
271         if (cpu_class_is_omap1()) {
272                 u16 ccr;
273
274                 ccr = dma_read(CCR(lch));
275                 ccr &= ~(1 << 5);
276                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
277                         ccr |= 1 << 5;
278                 dma_write(ccr, CCR(lch));
279
280                 ccr = dma_read(CCR2(lch));
281                 ccr &= ~(1 << 2);
282                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
283                         ccr |= 1 << 2;
284                 dma_write(ccr, CCR2(lch));
285         }
286
287         if (cpu_class_is_omap2() && dma_trigger) {
288                 u32 val;
289
290                 val = dma_read(CCR(lch));
291
292                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
293                 val &= ~((3 << 19) | 0x1f);
294                 val |= (dma_trigger & ~0x1f) << 14;
295                 val |= dma_trigger & 0x1f;
296
297                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
298                         val |= 1 << 5;
299                 else
300                         val &= ~(1 << 5);
301
302                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
303                         val |= 1 << 18;
304                 else
305                         val &= ~(1 << 18);
306
307                 if (src_or_dst_synch)
308                         val |= 1 << 24;         /* source synch */
309                 else
310                         val &= ~(1 << 24);      /* dest synch */
311
312                 dma_write(val, CCR(lch));
313         }
314
315         dma_write(elem_count, CEN(lch));
316         dma_write(frame_count, CFN(lch));
317 }
318 EXPORT_SYMBOL(omap_set_dma_transfer_params);
319
320 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
321 {
322         BUG_ON(omap_dma_in_1510_mode());
323
324         if (cpu_class_is_omap1()) {
325                 u16 w;
326
327                 w = dma_read(CCR2(lch));
328                 w &= ~0x03;
329
330                 switch (mode) {
331                 case OMAP_DMA_CONSTANT_FILL:
332                         w |= 0x01;
333                         break;
334                 case OMAP_DMA_TRANSPARENT_COPY:
335                         w |= 0x02;
336                         break;
337                 case OMAP_DMA_COLOR_DIS:
338                         break;
339                 default:
340                         BUG();
341                 }
342                 dma_write(w, CCR2(lch));
343
344                 w = dma_read(LCH_CTRL(lch));
345                 w &= ~0x0f;
346                 /* Default is channel type 2D */
347                 if (mode) {
348                         dma_write((u16)color, COLOR_L(lch));
349                         dma_write((u16)(color >> 16), COLOR_U(lch));
350                         w |= 1;         /* Channel type G */
351                 }
352                 dma_write(w, LCH_CTRL(lch));
353         }
354
355         if (cpu_class_is_omap2()) {
356                 u32 val;
357
358                 val = dma_read(CCR(lch));
359                 val &= ~((1 << 17) | (1 << 16));
360
361                 switch (mode) {
362                 case OMAP_DMA_CONSTANT_FILL:
363                         val |= 1 << 16;
364                         break;
365                 case OMAP_DMA_TRANSPARENT_COPY:
366                         val |= 1 << 17;
367                         break;
368                 case OMAP_DMA_COLOR_DIS:
369                         break;
370                 default:
371                         BUG();
372                 }
373                 dma_write(val, CCR(lch));
374
375                 color &= 0xffffff;
376                 dma_write(color, COLOR(lch));
377         }
378 }
379 EXPORT_SYMBOL(omap_set_dma_color_mode);
380
381 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
382 {
383         if (cpu_class_is_omap2()) {
384                 u32 csdp;
385
386                 csdp = dma_read(CSDP(lch));
387                 csdp &= ~(0x3 << 16);
388                 csdp |= (mode << 16);
389                 dma_write(csdp, CSDP(lch));
390         }
391 }
392 EXPORT_SYMBOL(omap_set_dma_write_mode);
393
394 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
395 {
396         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
397                 u32 l;
398
399                 l = dma_read(LCH_CTRL(lch));
400                 l &= ~0x7;
401                 l |= mode;
402                 dma_write(l, LCH_CTRL(lch));
403         }
404 }
405 EXPORT_SYMBOL(omap_set_dma_channel_mode);
406
407 /* Note that src_port is only for omap1 */
408 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
409                              unsigned long src_start,
410                              int src_ei, int src_fi)
411 {
412         u32 l;
413
414         if (cpu_class_is_omap1()) {
415                 u16 w;
416
417                 w = dma_read(CSDP(lch));
418                 w &= ~(0x1f << 2);
419                 w |= src_port << 2;
420                 dma_write(w, CSDP(lch));
421         }
422
423         l = dma_read(CCR(lch));
424         l &= ~(0x03 << 12);
425         l |= src_amode << 12;
426         dma_write(l, CCR(lch));
427
428         if (cpu_class_is_omap1()) {
429                 dma_write(src_start >> 16, CSSA_U(lch));
430                 dma_write((u16)src_start, CSSA_L(lch));
431         }
432
433         if (cpu_class_is_omap2())
434                 dma_write(src_start, CSSA(lch));
435
436         dma_write(src_ei, CSEI(lch));
437         dma_write(src_fi, CSFI(lch));
438 }
439 EXPORT_SYMBOL(omap_set_dma_src_params);
440
441 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
442 {
443         omap_set_dma_transfer_params(lch, params->data_type,
444                                      params->elem_count, params->frame_count,
445                                      params->sync_mode, params->trigger,
446                                      params->src_or_dst_synch);
447         omap_set_dma_src_params(lch, params->src_port,
448                                 params->src_amode, params->src_start,
449                                 params->src_ei, params->src_fi);
450
451         omap_set_dma_dest_params(lch, params->dst_port,
452                                  params->dst_amode, params->dst_start,
453                                  params->dst_ei, params->dst_fi);
454         if (params->read_prio || params->write_prio)
455                 omap_dma_set_prio_lch(lch, params->read_prio,
456                                       params->write_prio);
457 }
458 EXPORT_SYMBOL(omap_set_dma_params);
459
460 void omap_set_dma_src_index(int lch, int eidx, int fidx)
461 {
462         if (cpu_class_is_omap2())
463                 return;
464
465         dma_write(eidx, CSEI(lch));
466         dma_write(fidx, CSFI(lch));
467 }
468 EXPORT_SYMBOL(omap_set_dma_src_index);
469
470 void omap_set_dma_src_data_pack(int lch, int enable)
471 {
472         u32 l;
473
474         l = dma_read(CSDP(lch));
475         l &= ~(1 << 6);
476         if (enable)
477                 l |= (1 << 6);
478         dma_write(l, CSDP(lch));
479 }
480 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
481
482 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
483 {
484         unsigned int burst = 0;
485         u32 l;
486
487         l = dma_read(CSDP(lch));
488         l &= ~(0x03 << 7);
489
490         switch (burst_mode) {
491         case OMAP_DMA_DATA_BURST_DIS:
492                 break;
493         case OMAP_DMA_DATA_BURST_4:
494                 if (cpu_class_is_omap2())
495                         burst = 0x1;
496                 else
497                         burst = 0x2;
498                 break;
499         case OMAP_DMA_DATA_BURST_8:
500                 if (cpu_class_is_omap2()) {
501                         burst = 0x2;
502                         break;
503                 }
504                 /* not supported by current hardware on OMAP1
505                  * w |= (0x03 << 7);
506                  * fall through
507                  */
508         case OMAP_DMA_DATA_BURST_16:
509                 if (cpu_class_is_omap2()) {
510                         burst = 0x3;
511                         break;
512                 }
513                 /* OMAP1 don't support burst 16
514                  * fall through
515                  */
516         default:
517                 BUG();
518         }
519
520         l |= (burst << 7);
521         dma_write(l, CSDP(lch));
522 }
523 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
524
525 /* Note that dest_port is only for OMAP1 */
526 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
527                               unsigned long dest_start,
528                               int dst_ei, int dst_fi)
529 {
530         u32 l;
531
532         if (cpu_class_is_omap1()) {
533                 l = dma_read(CSDP(lch));
534                 l &= ~(0x1f << 9);
535                 l |= dest_port << 9;
536                 dma_write(l, CSDP(lch));
537         }
538
539         l = dma_read(CCR(lch));
540         l &= ~(0x03 << 14);
541         l |= dest_amode << 14;
542         dma_write(l, CCR(lch));
543
544         if (cpu_class_is_omap1()) {
545                 dma_write(dest_start >> 16, CDSA_U(lch));
546                 dma_write(dest_start, CDSA_L(lch));
547         }
548
549         if (cpu_class_is_omap2())
550                 dma_write(dest_start, CDSA(lch));
551
552         dma_write(dst_ei, CDEI(lch));
553         dma_write(dst_fi, CDFI(lch));
554 }
555 EXPORT_SYMBOL(omap_set_dma_dest_params);
556
557 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
558 {
559         if (cpu_class_is_omap2())
560                 return;
561
562         dma_write(eidx, CDEI(lch));
563         dma_write(fidx, CDFI(lch));
564 }
565 EXPORT_SYMBOL(omap_set_dma_dest_index);
566
567 void omap_set_dma_dest_data_pack(int lch, int enable)
568 {
569         u32 l;
570
571         l = dma_read(CSDP(lch));
572         l &= ~(1 << 13);
573         if (enable)
574                 l |= 1 << 13;
575         dma_write(l, CSDP(lch));
576 }
577 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
578
579 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
580 {
581         unsigned int burst = 0;
582         u32 l;
583
584         l = dma_read(CSDP(lch));
585         l &= ~(0x03 << 14);
586
587         switch (burst_mode) {
588         case OMAP_DMA_DATA_BURST_DIS:
589                 break;
590         case OMAP_DMA_DATA_BURST_4:
591                 if (cpu_class_is_omap2())
592                         burst = 0x1;
593                 else
594                         burst = 0x2;
595                 break;
596         case OMAP_DMA_DATA_BURST_8:
597                 if (cpu_class_is_omap2())
598                         burst = 0x2;
599                 else
600                         burst = 0x3;
601                 break;
602         case OMAP_DMA_DATA_BURST_16:
603                 if (cpu_class_is_omap2()) {
604                         burst = 0x3;
605                         break;
606                 }
607                 /* OMAP1 don't support burst 16
608                  * fall through
609                  */
610         default:
611                 printk(KERN_ERR "Invalid DMA burst mode\n");
612                 BUG();
613                 return;
614         }
615         l |= (burst << 14);
616         dma_write(l, CSDP(lch));
617 }
618 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
619
620 static inline void omap_enable_channel_irq(int lch)
621 {
622         u32 status;
623
624         /* Clear CSR */
625         if (cpu_class_is_omap1())
626                 status = dma_read(CSR(lch));
627         else if (cpu_class_is_omap2())
628                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
629
630         /* Enable some nice interrupts. */
631         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
632 }
633
634 static void omap_disable_channel_irq(int lch)
635 {
636         if (cpu_class_is_omap2())
637                 dma_write(0, CICR(lch));
638 }
639
640 void omap_enable_dma_irq(int lch, u16 bits)
641 {
642         dma_chan[lch].enabled_irqs |= bits;
643 }
644 EXPORT_SYMBOL(omap_enable_dma_irq);
645
646 void omap_disable_dma_irq(int lch, u16 bits)
647 {
648         dma_chan[lch].enabled_irqs &= ~bits;
649 }
650 EXPORT_SYMBOL(omap_disable_dma_irq);
651
652 static inline void enable_lnk(int lch)
653 {
654         u32 l;
655
656         l = dma_read(CLNK_CTRL(lch));
657
658         if (cpu_class_is_omap1())
659                 l &= ~(1 << 14);
660
661         /* Set the ENABLE_LNK bits */
662         if (dma_chan[lch].next_lch != -1)
663                 l = dma_chan[lch].next_lch | (1 << 15);
664
665 #ifndef CONFIG_ARCH_OMAP1
666         if (cpu_class_is_omap2())
667                 if (dma_chan[lch].next_linked_ch != -1)
668                         l = dma_chan[lch].next_linked_ch | (1 << 15);
669 #endif
670
671         dma_write(l, CLNK_CTRL(lch));
672 }
673
674 static inline void disable_lnk(int lch)
675 {
676         u32 l;
677
678         l = dma_read(CLNK_CTRL(lch));
679
680         /* Disable interrupts */
681         if (cpu_class_is_omap1()) {
682                 dma_write(0, CICR(lch));
683                 /* Set the STOP_LNK bit */
684                 l |= 1 << 14;
685         }
686
687         if (cpu_class_is_omap2()) {
688                 omap_disable_channel_irq(lch);
689                 /* Clear the ENABLE_LNK bit */
690                 l &= ~(1 << 15);
691         }
692
693         dma_write(l, CLNK_CTRL(lch));
694         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
695 }
696
697 static inline void omap2_enable_irq_lch(int lch)
698 {
699         u32 val;
700         unsigned long flags;
701
702         if (!cpu_class_is_omap2())
703                 return;
704
705         spin_lock_irqsave(&dma_chan_lock, flags);
706         val = dma_read(IRQENABLE_L0);
707         val |= 1 << lch;
708         dma_write(val, IRQENABLE_L0);
709         spin_unlock_irqrestore(&dma_chan_lock, flags);
710 }
711
712 int omap_request_dma(int dev_id, const char *dev_name,
713                      void (*callback)(int lch, u16 ch_status, void *data),
714                      void *data, int *dma_ch_out)
715 {
716         int ch, free_ch = -1;
717         unsigned long flags;
718         struct omap_dma_lch *chan;
719
720         spin_lock_irqsave(&dma_chan_lock, flags);
721         for (ch = 0; ch < dma_chan_count; ch++) {
722                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
723                         free_ch = ch;
724                         if (dev_id == 0)
725                                 break;
726                 }
727         }
728         if (free_ch == -1) {
729                 spin_unlock_irqrestore(&dma_chan_lock, flags);
730                 return -EBUSY;
731         }
732         chan = dma_chan + free_ch;
733         chan->dev_id = dev_id;
734
735         if (cpu_class_is_omap1())
736                 clear_lch_regs(free_ch);
737
738         if (cpu_class_is_omap2())
739                 omap_clear_dma(free_ch);
740
741         spin_unlock_irqrestore(&dma_chan_lock, flags);
742
743         chan->dev_name = dev_name;
744         chan->callback = callback;
745         chan->data = data;
746         chan->flags = 0;
747
748 #ifndef CONFIG_ARCH_OMAP1
749         if (cpu_class_is_omap2()) {
750                 chan->chain_id = -1;
751                 chan->next_linked_ch = -1;
752         }
753 #endif
754
755         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
756
757         if (cpu_class_is_omap1())
758                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
759         else if (cpu_class_is_omap2())
760                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
761                         OMAP2_DMA_TRANS_ERR_IRQ;
762
763         if (cpu_is_omap16xx()) {
764                 /* If the sync device is set, configure it dynamically. */
765                 if (dev_id != 0) {
766                         set_gdma_dev(free_ch + 1, dev_id);
767                         dev_id = free_ch + 1;
768                 }
769                 /*
770                  * Disable the 1510 compatibility mode and set the sync device
771                  * id.
772                  */
773                 dma_write(dev_id | (1 << 10), CCR(free_ch));
774         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
775                 dma_write(dev_id, CCR(free_ch));
776         }
777
778         if (cpu_class_is_omap2()) {
779                 omap2_enable_irq_lch(free_ch);
780                 omap_enable_channel_irq(free_ch);
781                 /* Clear the CSR register and IRQ status register */
782                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
783                 dma_write(1 << free_ch, IRQSTATUS_L0);
784         }
785
786         *dma_ch_out = free_ch;
787
788         return 0;
789 }
790 EXPORT_SYMBOL(omap_request_dma);
791
792 void omap_free_dma(int lch)
793 {
794         unsigned long flags;
795
796         if (dma_chan[lch].dev_id == -1) {
797                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
798                        lch);
799                 return;
800         }
801
802         if (cpu_class_is_omap1()) {
803                 /* Disable all DMA interrupts for the channel. */
804                 dma_write(0, CICR(lch));
805                 /* Make sure the DMA transfer is stopped. */
806                 dma_write(0, CCR(lch));
807         }
808
809         if (cpu_class_is_omap2()) {
810                 u32 val;
811
812                 spin_lock_irqsave(&dma_chan_lock, flags);
813                 /* Disable interrupts */
814                 val = dma_read(IRQENABLE_L0);
815                 val &= ~(1 << lch);
816                 dma_write(val, IRQENABLE_L0);
817                 spin_unlock_irqrestore(&dma_chan_lock, flags);
818
819                 /* Clear the CSR register and IRQ status register */
820                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
821                 dma_write(1 << lch, IRQSTATUS_L0);
822
823                 /* Disable all DMA interrupts for the channel. */
824                 dma_write(0, CICR(lch));
825
826                 /* Make sure the DMA transfer is stopped. */
827                 dma_write(0, CCR(lch));
828                 omap_clear_dma(lch);
829         }
830
831         spin_lock_irqsave(&dma_chan_lock, flags);
832         dma_chan[lch].dev_id = -1;
833         dma_chan[lch].next_lch = -1;
834         dma_chan[lch].callback = NULL;
835         spin_unlock_irqrestore(&dma_chan_lock, flags);
836 }
837 EXPORT_SYMBOL(omap_free_dma);
838
839 /**
840  * @brief omap_dma_set_global_params : Set global priority settings for dma
841  *
842  * @param arb_rate
843  * @param max_fifo_depth
844  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
845  *                                                 DMA_THREAD_RESERVE_ONET
846  *                                                 DMA_THREAD_RESERVE_TWOT
847  *                                                 DMA_THREAD_RESERVE_THREET
848  */
849 void
850 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
851 {
852         u32 reg;
853
854         if (!cpu_class_is_omap2()) {
855                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
856                 return;
857         }
858
859         if (max_fifo_depth == 0)
860                 max_fifo_depth = 1;
861         if (arb_rate == 0)
862                 arb_rate = 1;
863
864         reg = 0xff & max_fifo_depth;
865         reg |= (0x3 & tparams) << 12;
866         reg |= (arb_rate & 0xff) << 16;
867
868         dma_write(reg, GCR);
869 }
870 EXPORT_SYMBOL(omap_dma_set_global_params);
871
872 /**
873  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
874  *
875  * @param lch
876  * @param read_prio - Read priority
877  * @param write_prio - Write priority
878  * Both of the above can be set with one of the following values :
879  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
880  */
881 int
882 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
883                       unsigned char write_prio)
884 {
885         u32 l;
886
887         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
888                 printk(KERN_ERR "Invalid channel id\n");
889                 return -EINVAL;
890         }
891         l = dma_read(CCR(lch));
892         l &= ~((1 << 6) | (1 << 26));
893         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
894                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
895         else
896                 l |= ((read_prio & 0x1) << 6);
897
898         dma_write(l, CCR(lch));
899
900         return 0;
901 }
902 EXPORT_SYMBOL(omap_dma_set_prio_lch);
903
904 /*
905  * Clears any DMA state so the DMA engine is ready to restart with new buffers
906  * through omap_start_dma(). Any buffers in flight are discarded.
907  */
908 void omap_clear_dma(int lch)
909 {
910         unsigned long flags;
911
912         local_irq_save(flags);
913
914         if (cpu_class_is_omap1()) {
915                 u32 l;
916
917                 l = dma_read(CCR(lch));
918                 l &= ~OMAP_DMA_CCR_EN;
919                 dma_write(l, CCR(lch));
920
921                 /* Clear pending interrupts */
922                 l = dma_read(CSR(lch));
923         }
924
925         if (cpu_class_is_omap2()) {
926                 int i;
927                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
928                 for (i = 0; i < 0x44; i += 4)
929                         __raw_writel(0, lch_base + i);
930         }
931
932         local_irq_restore(flags);
933 }
934 EXPORT_SYMBOL(omap_clear_dma);
935
936 void omap_start_dma(int lch)
937 {
938         u32 l;
939
940         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
941                 int next_lch, cur_lch;
942                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
943
944                 dma_chan_link_map[lch] = 1;
945                 /* Set the link register of the first channel */
946                 enable_lnk(lch);
947
948                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
949                 cur_lch = dma_chan[lch].next_lch;
950                 do {
951                         next_lch = dma_chan[cur_lch].next_lch;
952
953                         /* The loop case: we've been here already */
954                         if (dma_chan_link_map[cur_lch])
955                                 break;
956                         /* Mark the current channel */
957                         dma_chan_link_map[cur_lch] = 1;
958
959                         enable_lnk(cur_lch);
960                         omap_enable_channel_irq(cur_lch);
961
962                         cur_lch = next_lch;
963                 } while (next_lch != -1);
964         } else if (cpu_is_omap242x() ||
965                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
966
967                 /* Errata: Need to write lch even if not using chaining */
968                 dma_write(lch, CLNK_CTRL(lch));
969         }
970
971         omap_enable_channel_irq(lch);
972
973         l = dma_read(CCR(lch));
974
975         /*
976          * Errata: On ES2.0 BUFFERING disable must be set.
977          * This will always fail on ES1.0
978          */
979         if (cpu_is_omap24xx())
980                 l |= OMAP_DMA_CCR_EN;
981
982         l |= OMAP_DMA_CCR_EN;
983         dma_write(l, CCR(lch));
984
985         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
986 }
987 EXPORT_SYMBOL(omap_start_dma);
988
989 void omap_stop_dma(int lch)
990 {
991         u32 l;
992
993         /* Disable all interrupts on the channel */
994         if (cpu_class_is_omap1())
995                 dma_write(0, CICR(lch));
996
997         l = dma_read(CCR(lch));
998         l &= ~OMAP_DMA_CCR_EN;
999         dma_write(l, CCR(lch));
1000
1001         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1002                 int next_lch, cur_lch = lch;
1003                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1004
1005                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1006                 do {
1007                         /* The loop case: we've been here already */
1008                         if (dma_chan_link_map[cur_lch])
1009                                 break;
1010                         /* Mark the current channel */
1011                         dma_chan_link_map[cur_lch] = 1;
1012
1013                         disable_lnk(cur_lch);
1014
1015                         next_lch = dma_chan[cur_lch].next_lch;
1016                         cur_lch = next_lch;
1017                 } while (next_lch != -1);
1018         }
1019
1020         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1021 }
1022 EXPORT_SYMBOL(omap_stop_dma);
1023
1024 /*
1025  * Allows changing the DMA callback function or data. This may be needed if
1026  * the driver shares a single DMA channel for multiple dma triggers.
1027  */
1028 int omap_set_dma_callback(int lch,
1029                           void (*callback)(int lch, u16 ch_status, void *data),
1030                           void *data)
1031 {
1032         unsigned long flags;
1033
1034         if (lch < 0)
1035                 return -ENODEV;
1036
1037         spin_lock_irqsave(&dma_chan_lock, flags);
1038         if (dma_chan[lch].dev_id == -1) {
1039                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1040                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1041                 return -EINVAL;
1042         }
1043         dma_chan[lch].callback = callback;
1044         dma_chan[lch].data = data;
1045         spin_unlock_irqrestore(&dma_chan_lock, flags);
1046
1047         return 0;
1048 }
1049 EXPORT_SYMBOL(omap_set_dma_callback);
1050
1051 /*
1052  * Returns current physical source address for the given DMA channel.
1053  * If the channel is running the caller must disable interrupts prior calling
1054  * this function and process the returned value before re-enabling interrupt to
1055  * prevent races with the interrupt handler. Note that in continuous mode there
1056  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1057  * in incorrect return value.
1058  */
1059 dma_addr_t omap_get_dma_src_pos(int lch)
1060 {
1061         dma_addr_t offset = 0;
1062
1063         if (cpu_is_omap15xx())
1064                 offset = dma_read(CPC(lch));
1065         else
1066                 offset = dma_read(CSAC(lch));
1067
1068         /*
1069          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1070          * read before the DMA controller finished disabling the channel.
1071          */
1072         if (!cpu_is_omap15xx() && offset == 0)
1073                 offset = dma_read(CSAC(lch));
1074
1075         if (cpu_class_is_omap1())
1076                 offset |= (dma_read(CSSA_U(lch)) << 16);
1077
1078         return offset;
1079 }
1080 EXPORT_SYMBOL(omap_get_dma_src_pos);
1081
1082 /*
1083  * Returns current physical destination address for the given DMA channel.
1084  * If the channel is running the caller must disable interrupts prior calling
1085  * this function and process the returned value before re-enabling interrupt to
1086  * prevent races with the interrupt handler. Note that in continuous mode there
1087  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1088  * in incorrect return value.
1089  */
1090 dma_addr_t omap_get_dma_dst_pos(int lch)
1091 {
1092         dma_addr_t offset = 0;
1093
1094         if (cpu_is_omap15xx())
1095                 offset = dma_read(CPC(lch));
1096         else
1097                 offset = dma_read(CDAC(lch));
1098
1099         /*
1100          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1101          * read before the DMA controller finished disabling the channel.
1102          */
1103         if (!cpu_is_omap15xx() && offset == 0)
1104                 offset = dma_read(CDAC(lch));
1105
1106         if (cpu_class_is_omap1())
1107                 offset |= (dma_read(CDSA_U(lch)) << 16);
1108
1109         return offset;
1110 }
1111 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1112
1113 int omap_get_dma_active_status(int lch)
1114 {
1115         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1116 }
1117 EXPORT_SYMBOL(omap_get_dma_active_status);
1118
1119 int omap_dma_running(void)
1120 {
1121         int lch;
1122
1123         /*
1124          * On OMAP1510, internal LCD controller will start the transfer
1125          * when it gets enabled, so assume DMA running if LCD enabled.
1126          */
1127         if (cpu_is_omap1510())
1128                 if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
1129                         return 1;
1130
1131         /* Check if LCD DMA is running */
1132         if (cpu_is_omap16xx())
1133                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1134                         return 1;
1135
1136         for (lch = 0; lch < dma_chan_count; lch++)
1137                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1138                         return 1;
1139
1140         return 0;
1141 }
1142
1143 /*
1144  * lch_queue DMA will start right after lch_head one is finished.
1145  * For this DMA link to start, you still need to start (see omap_start_dma)
1146  * the first one. That will fire up the entire queue.
1147  */
1148 void omap_dma_link_lch(int lch_head, int lch_queue)
1149 {
1150         if (omap_dma_in_1510_mode()) {
1151                 if (lch_head == lch_queue) {
1152                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1153                                                                 CCR(lch_head));
1154                         return;
1155                 }
1156                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1157                 BUG();
1158                 return;
1159         }
1160
1161         if ((dma_chan[lch_head].dev_id == -1) ||
1162             (dma_chan[lch_queue].dev_id == -1)) {
1163                 printk(KERN_ERR "omap_dma: trying to link "
1164                        "non requested channels\n");
1165                 dump_stack();
1166         }
1167
1168         dma_chan[lch_head].next_lch = lch_queue;
1169 }
1170 EXPORT_SYMBOL(omap_dma_link_lch);
1171
1172 /*
1173  * Once the DMA queue is stopped, we can destroy it.
1174  */
1175 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1176 {
1177         if (omap_dma_in_1510_mode()) {
1178                 if (lch_head == lch_queue) {
1179                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1180                                                                 CCR(lch_head));
1181                         return;
1182                 }
1183                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1184                 BUG();
1185                 return;
1186         }
1187
1188         if (dma_chan[lch_head].next_lch != lch_queue ||
1189             dma_chan[lch_head].next_lch == -1) {
1190                 printk(KERN_ERR "omap_dma: trying to unlink "
1191                        "non linked channels\n");
1192                 dump_stack();
1193         }
1194
1195         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1196             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1197                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1198                        "before unlinking\n");
1199                 dump_stack();
1200         }
1201
1202         dma_chan[lch_head].next_lch = -1;
1203 }
1204 EXPORT_SYMBOL(omap_dma_unlink_lch);
1205
1206 /*----------------------------------------------------------------------------*/
1207
1208 #ifndef CONFIG_ARCH_OMAP1
1209 /* Create chain of DMA channesls */
1210 static void create_dma_lch_chain(int lch_head, int lch_queue)
1211 {
1212         u32 l;
1213
1214         /* Check if this is the first link in chain */
1215         if (dma_chan[lch_head].next_linked_ch == -1) {
1216                 dma_chan[lch_head].next_linked_ch = lch_queue;
1217                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1218                 dma_chan[lch_queue].next_linked_ch = lch_head;
1219                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1220         }
1221
1222         /* a link exists, link the new channel in circular chain */
1223         else {
1224                 dma_chan[lch_queue].next_linked_ch =
1225                                         dma_chan[lch_head].next_linked_ch;
1226                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1227                 dma_chan[lch_head].next_linked_ch = lch_queue;
1228                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1229                                         lch_queue;
1230         }
1231
1232         l = dma_read(CLNK_CTRL(lch_head));
1233         l &= ~(0x1f);
1234         l |= lch_queue;
1235         dma_write(l, CLNK_CTRL(lch_head));
1236
1237         l = dma_read(CLNK_CTRL(lch_queue));
1238         l &= ~(0x1f);
1239         l |= (dma_chan[lch_queue].next_linked_ch);
1240         dma_write(l, CLNK_CTRL(lch_queue));
1241 }
1242
1243 /**
1244  * @brief omap_request_dma_chain : Request a chain of DMA channels
1245  *
1246  * @param dev_id - Device id using the dma channel
1247  * @param dev_name - Device name
1248  * @param callback - Call back function
1249  * @chain_id -
1250  * @no_of_chans - Number of channels requested
1251  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1252  *                                            OMAP_DMA_DYNAMIC_CHAIN
1253  * @params - Channel parameters
1254  *
1255  * @return - Success : 0
1256  *           Failure: -EINVAL/-ENOMEM
1257  */
1258 int omap_request_dma_chain(int dev_id, const char *dev_name,
1259                            void (*callback) (int lch, u16 ch_status,
1260                                              void *data),
1261                            int *chain_id, int no_of_chans, int chain_mode,
1262                            struct omap_dma_channel_params params)
1263 {
1264         int *channels;
1265         int i, err;
1266
1267         /* Is the chain mode valid ? */
1268         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1269                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1270                 printk(KERN_ERR "Invalid chain mode requested\n");
1271                 return -EINVAL;
1272         }
1273
1274         if (unlikely((no_of_chans < 1
1275                         || no_of_chans > dma_lch_count))) {
1276                 printk(KERN_ERR "Invalid Number of channels requested\n");
1277                 return -EINVAL;
1278         }
1279
1280         /* Allocate a queue to maintain the status of the channels
1281          * in the chain */
1282         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1283         if (channels == NULL) {
1284                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1285                 return -ENOMEM;
1286         }
1287
1288         /* request and reserve DMA channels for the chain */
1289         for (i = 0; i < no_of_chans; i++) {
1290                 err = omap_request_dma(dev_id, dev_name,
1291                                         callback, NULL, &channels[i]);
1292                 if (err < 0) {
1293                         int j;
1294                         for (j = 0; j < i; j++)
1295                                 omap_free_dma(channels[j]);
1296                         kfree(channels);
1297                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1298                         return err;
1299                 }
1300                 dma_chan[channels[i]].prev_linked_ch = -1;
1301                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1302
1303                 /*
1304                  * Allowing client drivers to set common parameters now,
1305                  * so that later only relevant (src_start, dest_start
1306                  * and element count) can be set
1307                  */
1308                 omap_set_dma_params(channels[i], &params);
1309         }
1310
1311         *chain_id = channels[0];
1312         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1313         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1314         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1315         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1316
1317         for (i = 0; i < no_of_chans; i++)
1318                 dma_chan[channels[i]].chain_id = *chain_id;
1319
1320         /* Reset the Queue pointers */
1321         OMAP_DMA_CHAIN_QINIT(*chain_id);
1322
1323         /* Set up the chain */
1324         if (no_of_chans == 1)
1325                 create_dma_lch_chain(channels[0], channels[0]);
1326         else {
1327                 for (i = 0; i < (no_of_chans - 1); i++)
1328                         create_dma_lch_chain(channels[i], channels[i + 1]);
1329         }
1330
1331         return 0;
1332 }
1333 EXPORT_SYMBOL(omap_request_dma_chain);
1334
1335 /**
1336  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1337  * params after setting it. Dont do this while dma is running!!
1338  *
1339  * @param chain_id - Chained logical channel id.
1340  * @param params
1341  *
1342  * @return - Success : 0
1343  *           Failure : -EINVAL
1344  */
1345 int omap_modify_dma_chain_params(int chain_id,
1346                                 struct omap_dma_channel_params params)
1347 {
1348         int *channels;
1349         u32 i;
1350
1351         /* Check for input params */
1352         if (unlikely((chain_id < 0
1353                         || chain_id >= dma_lch_count))) {
1354                 printk(KERN_ERR "Invalid chain id\n");
1355                 return -EINVAL;
1356         }
1357
1358         /* Check if the chain exists */
1359         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1360                 printk(KERN_ERR "Chain doesn't exists\n");
1361                 return -EINVAL;
1362         }
1363         channels = dma_linked_lch[chain_id].linked_dmach_q;
1364
1365         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1366                 /*
1367                  * Allowing client drivers to set common parameters now,
1368                  * so that later only relevant (src_start, dest_start
1369                  * and element count) can be set
1370                  */
1371                 omap_set_dma_params(channels[i], &params);
1372         }
1373
1374         return 0;
1375 }
1376 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1377
1378 /**
1379  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1380  *
1381  * @param chain_id
1382  *
1383  * @return - Success : 0
1384  *           Failure : -EINVAL
1385  */
1386 int omap_free_dma_chain(int chain_id)
1387 {
1388         int *channels;
1389         u32 i;
1390
1391         /* Check for input params */
1392         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1393                 printk(KERN_ERR "Invalid chain id\n");
1394                 return -EINVAL;
1395         }
1396
1397         /* Check if the chain exists */
1398         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1399                 printk(KERN_ERR "Chain doesn't exists\n");
1400                 return -EINVAL;
1401         }
1402
1403         channels = dma_linked_lch[chain_id].linked_dmach_q;
1404         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1405                 dma_chan[channels[i]].next_linked_ch = -1;
1406                 dma_chan[channels[i]].prev_linked_ch = -1;
1407                 dma_chan[channels[i]].chain_id = -1;
1408                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1409                 omap_free_dma(channels[i]);
1410         }
1411
1412         kfree(channels);
1413
1414         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1415         dma_linked_lch[chain_id].chain_mode = -1;
1416         dma_linked_lch[chain_id].chain_state = -1;
1417
1418         return (0);
1419 }
1420 EXPORT_SYMBOL(omap_free_dma_chain);
1421
1422 /**
1423  * @brief omap_dma_chain_status - Check if the chain is in
1424  * active / inactive state.
1425  * @param chain_id
1426  *
1427  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1428  *           Failure : -EINVAL
1429  */
1430 int omap_dma_chain_status(int chain_id)
1431 {
1432         /* Check for input params */
1433         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1434                 printk(KERN_ERR "Invalid chain id\n");
1435                 return -EINVAL;
1436         }
1437
1438         /* Check if the chain exists */
1439         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1440                 printk(KERN_ERR "Chain doesn't exists\n");
1441                 return -EINVAL;
1442         }
1443         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1444                         dma_linked_lch[chain_id].q_count);
1445
1446         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1447                 return OMAP_DMA_CHAIN_INACTIVE;
1448
1449         return OMAP_DMA_CHAIN_ACTIVE;
1450 }
1451 EXPORT_SYMBOL(omap_dma_chain_status);
1452
1453 /**
1454  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1455  * set the params and start the transfer.
1456  *
1457  * @param chain_id
1458  * @param src_start - buffer start address
1459  * @param dest_start - Dest address
1460  * @param elem_count
1461  * @param frame_count
1462  * @param callbk_data - channel callback parameter data.
1463  *
1464  * @return  - Success : 0
1465  *            Failure: -EINVAL/-EBUSY
1466  */
1467 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1468                         int elem_count, int frame_count, void *callbk_data)
1469 {
1470         int *channels;
1471         u32 l, lch;
1472         int start_dma = 0;
1473
1474         /*
1475          * if buffer size is less than 1 then there is
1476          * no use of starting the chain
1477          */
1478         if (elem_count < 1) {
1479                 printk(KERN_ERR "Invalid buffer size\n");
1480                 return -EINVAL;
1481         }
1482
1483         /* Check for input params */
1484         if (unlikely((chain_id < 0
1485                         || chain_id >= dma_lch_count))) {
1486                 printk(KERN_ERR "Invalid chain id\n");
1487                 return -EINVAL;
1488         }
1489
1490         /* Check if the chain exists */
1491         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1492                 printk(KERN_ERR "Chain doesn't exist\n");
1493                 return -EINVAL;
1494         }
1495
1496         /* Check if all the channels in chain are in use */
1497         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1498                 return -EBUSY;
1499
1500         /* Frame count may be negative in case of indexed transfers */
1501         channels = dma_linked_lch[chain_id].linked_dmach_q;
1502
1503         /* Get a free channel */
1504         lch = channels[dma_linked_lch[chain_id].q_tail];
1505
1506         /* Store the callback data */
1507         dma_chan[lch].data = callbk_data;
1508
1509         /* Increment the q_tail */
1510         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1511
1512         /* Set the params to the free channel */
1513         if (src_start != 0)
1514                 dma_write(src_start, CSSA(lch));
1515         if (dest_start != 0)
1516                 dma_write(dest_start, CDSA(lch));
1517
1518         /* Write the buffer size */
1519         dma_write(elem_count, CEN(lch));
1520         dma_write(frame_count, CFN(lch));
1521
1522         /*
1523          * If the chain is dynamically linked,
1524          * then we may have to start the chain if its not active
1525          */
1526         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1527
1528                 /*
1529                  * In Dynamic chain, if the chain is not started,
1530                  * queue the channel
1531                  */
1532                 if (dma_linked_lch[chain_id].chain_state ==
1533                                                 DMA_CHAIN_NOTSTARTED) {
1534                         /* Enable the link in previous channel */
1535                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1536                                                                 DMA_CH_QUEUED)
1537                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1538                         dma_chan[lch].state = DMA_CH_QUEUED;
1539                 }
1540
1541                 /*
1542                  * Chain is already started, make sure its active,
1543                  * if not then start the chain
1544                  */
1545                 else {
1546                         start_dma = 1;
1547
1548                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1549                                                         DMA_CH_STARTED) {
1550                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1551                                 dma_chan[lch].state = DMA_CH_QUEUED;
1552                                 start_dma = 0;
1553                                 if (0 == ((1 << 7) & dma_read(
1554                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1555                                         disable_lnk(dma_chan[lch].
1556                                                     prev_linked_ch);
1557                                         pr_debug("\n prev ch is stopped\n");
1558                                         start_dma = 1;
1559                                 }
1560                         }
1561
1562                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1563                                                         == DMA_CH_QUEUED) {
1564                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1565                                 dma_chan[lch].state = DMA_CH_QUEUED;
1566                                 start_dma = 0;
1567                         }
1568                         omap_enable_channel_irq(lch);
1569
1570                         l = dma_read(CCR(lch));
1571
1572                         if ((0 == (l & (1 << 24))))
1573                                 l &= ~(1 << 25);
1574                         else
1575                                 l |= (1 << 25);
1576                         if (start_dma == 1) {
1577                                 if (0 == (l & (1 << 7))) {
1578                                         l |= (1 << 7);
1579                                         dma_chan[lch].state = DMA_CH_STARTED;
1580                                         pr_debug("starting %d\n", lch);
1581                                         dma_write(l, CCR(lch));
1582                                 } else
1583                                         start_dma = 0;
1584                         } else {
1585                                 if (0 == (l & (1 << 7)))
1586                                         dma_write(l, CCR(lch));
1587                         }
1588                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1589                 }
1590         }
1591
1592         return 0;
1593 }
1594 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1595
1596 /**
1597  * @brief omap_start_dma_chain_transfers - Start the chain
1598  *
1599  * @param chain_id
1600  *
1601  * @return - Success : 0
1602  *           Failure : -EINVAL/-EBUSY
1603  */
1604 int omap_start_dma_chain_transfers(int chain_id)
1605 {
1606         int *channels;
1607         u32 l, i;
1608
1609         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1610                 printk(KERN_ERR "Invalid chain id\n");
1611                 return -EINVAL;
1612         }
1613
1614         channels = dma_linked_lch[chain_id].linked_dmach_q;
1615
1616         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1617                 printk(KERN_ERR "Chain is already started\n");
1618                 return -EBUSY;
1619         }
1620
1621         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1622                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1623                                                                         i++) {
1624                         enable_lnk(channels[i]);
1625                         omap_enable_channel_irq(channels[i]);
1626                 }
1627         } else {
1628                 omap_enable_channel_irq(channels[0]);
1629         }
1630
1631         l = dma_read(CCR(channels[0]));
1632         l |= (1 << 7);
1633         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1634         dma_chan[channels[0]].state = DMA_CH_STARTED;
1635
1636         if ((0 == (l & (1 << 24))))
1637                 l &= ~(1 << 25);
1638         else
1639                 l |= (1 << 25);
1640         dma_write(l, CCR(channels[0]));
1641
1642         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1643
1644         return 0;
1645 }
1646 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1647
1648 /**
1649  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1650  *
1651  * @param chain_id
1652  *
1653  * @return - Success : 0
1654  *           Failure : EINVAL
1655  */
1656 int omap_stop_dma_chain_transfers(int chain_id)
1657 {
1658         int *channels;
1659         u32 l, i;
1660         u32 sys_cf;
1661
1662         /* Check for input params */
1663         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1664                 printk(KERN_ERR "Invalid chain id\n");
1665                 return -EINVAL;
1666         }
1667
1668         /* Check if the chain exists */
1669         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1670                 printk(KERN_ERR "Chain doesn't exists\n");
1671                 return -EINVAL;
1672         }
1673         channels = dma_linked_lch[chain_id].linked_dmach_q;
1674
1675         /*
1676          * DMA Errata:
1677          * Special programming model needed to disable DMA before end of block
1678          */
1679         sys_cf = dma_read(OCP_SYSCONFIG);
1680         l = sys_cf;
1681         /* Middle mode reg set no Standby */
1682         l &= ~((1 << 12)|(1 << 13));
1683         dma_write(l, OCP_SYSCONFIG);
1684
1685         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1686
1687                 /* Stop the Channel transmission */
1688                 l = dma_read(CCR(channels[i]));
1689                 l &= ~(1 << 7);
1690                 dma_write(l, CCR(channels[i]));
1691
1692                 /* Disable the link in all the channels */
1693                 disable_lnk(channels[i]);
1694                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1695
1696         }
1697         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1698
1699         /* Reset the Queue pointers */
1700         OMAP_DMA_CHAIN_QINIT(chain_id);
1701
1702         /* Errata - put in the old value */
1703         dma_write(sys_cf, OCP_SYSCONFIG);
1704
1705         return 0;
1706 }
1707 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1708
1709 /* Get the index of the ongoing DMA in chain */
1710 /**
1711  * @brief omap_get_dma_chain_index - Get the element and frame index
1712  * of the ongoing DMA in chain
1713  *
1714  * @param chain_id
1715  * @param ei - Element index
1716  * @param fi - Frame index
1717  *
1718  * @return - Success : 0
1719  *           Failure : -EINVAL
1720  */
1721 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1722 {
1723         int lch;
1724         int *channels;
1725
1726         /* Check for input params */
1727         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1728                 printk(KERN_ERR "Invalid chain id\n");
1729                 return -EINVAL;
1730         }
1731
1732         /* Check if the chain exists */
1733         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1734                 printk(KERN_ERR "Chain doesn't exists\n");
1735                 return -EINVAL;
1736         }
1737         if ((!ei) || (!fi))
1738                 return -EINVAL;
1739
1740         channels = dma_linked_lch[chain_id].linked_dmach_q;
1741
1742         /* Get the current channel */
1743         lch = channels[dma_linked_lch[chain_id].q_head];
1744
1745         *ei = dma_read(CCEN(lch));
1746         *fi = dma_read(CCFN(lch));
1747
1748         return 0;
1749 }
1750 EXPORT_SYMBOL(omap_get_dma_chain_index);
1751
1752 /**
1753  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1754  * ongoing DMA in chain
1755  *
1756  * @param chain_id
1757  *
1758  * @return - Success : Destination position
1759  *           Failure : -EINVAL
1760  */
1761 int omap_get_dma_chain_dst_pos(int chain_id)
1762 {
1763         int lch;
1764         int *channels;
1765
1766         /* Check for input params */
1767         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1768                 printk(KERN_ERR "Invalid chain id\n");
1769                 return -EINVAL;
1770         }
1771
1772         /* Check if the chain exists */
1773         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1774                 printk(KERN_ERR "Chain doesn't exists\n");
1775                 return -EINVAL;
1776         }
1777
1778         channels = dma_linked_lch[chain_id].linked_dmach_q;
1779
1780         /* Get the current channel */
1781         lch = channels[dma_linked_lch[chain_id].q_head];
1782
1783         return dma_read(CDAC(lch));
1784 }
1785 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1786
1787 /**
1788  * @brief omap_get_dma_chain_src_pos - Get the source position
1789  * of the ongoing DMA in chain
1790  * @param chain_id
1791  *
1792  * @return - Success : Destination position
1793  *           Failure : -EINVAL
1794  */
1795 int omap_get_dma_chain_src_pos(int chain_id)
1796 {
1797         int lch;
1798         int *channels;
1799
1800         /* Check for input params */
1801         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1802                 printk(KERN_ERR "Invalid chain id\n");
1803                 return -EINVAL;
1804         }
1805
1806         /* Check if the chain exists */
1807         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1808                 printk(KERN_ERR "Chain doesn't exists\n");
1809                 return -EINVAL;
1810         }
1811
1812         channels = dma_linked_lch[chain_id].linked_dmach_q;
1813
1814         /* Get the current channel */
1815         lch = channels[dma_linked_lch[chain_id].q_head];
1816
1817         return dma_read(CSAC(lch));
1818 }
1819 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1820 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1821
1822 /*----------------------------------------------------------------------------*/
1823
1824 #ifdef CONFIG_ARCH_OMAP1
1825
1826 static int omap1_dma_handle_ch(int ch)
1827 {
1828         u32 csr;
1829
1830         if (enable_1510_mode && ch >= 6) {
1831                 csr = dma_chan[ch].saved_csr;
1832                 dma_chan[ch].saved_csr = 0;
1833         } else
1834                 csr = dma_read(CSR(ch));
1835         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1836                 dma_chan[ch + 6].saved_csr = csr >> 7;
1837                 csr &= 0x7f;
1838         }
1839         if ((csr & 0x3f) == 0)
1840                 return 0;
1841         if (unlikely(dma_chan[ch].dev_id == -1)) {
1842                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1843                        "%d (CSR %04x)\n", ch, csr);
1844                 return 0;
1845         }
1846         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1847                 printk(KERN_WARNING "DMA timeout with device %d\n",
1848                        dma_chan[ch].dev_id);
1849         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1850                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1851                        "with device %d\n", dma_chan[ch].dev_id);
1852         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1853                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1854         if (likely(dma_chan[ch].callback != NULL))
1855                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1856
1857         return 1;
1858 }
1859
1860 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1861 {
1862         int ch = ((int) dev_id) - 1;
1863         int handled = 0;
1864
1865         for (;;) {
1866                 int handled_now = 0;
1867
1868                 handled_now += omap1_dma_handle_ch(ch);
1869                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1870                         handled_now += omap1_dma_handle_ch(ch + 6);
1871                 if (!handled_now)
1872                         break;
1873                 handled += handled_now;
1874         }
1875
1876         return handled ? IRQ_HANDLED : IRQ_NONE;
1877 }
1878
1879 #else
1880 #define omap1_dma_irq_handler   NULL
1881 #endif
1882
1883 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1884                         defined(CONFIG_ARCH_OMAP4)
1885
1886 static int omap2_dma_handle_ch(int ch)
1887 {
1888         u32 status = dma_read(CSR(ch));
1889
1890         if (!status) {
1891                 if (printk_ratelimit())
1892                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1893                                 ch);
1894                 dma_write(1 << ch, IRQSTATUS_L0);
1895                 return 0;
1896         }
1897         if (unlikely(dma_chan[ch].dev_id == -1)) {
1898                 if (printk_ratelimit())
1899                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1900                                         "channel %d\n", status, ch);
1901                 return 0;
1902         }
1903         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1904                 printk(KERN_INFO
1905                        "DMA synchronization event drop occurred with device "
1906                        "%d\n", dma_chan[ch].dev_id);
1907         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1908                 printk(KERN_INFO "DMA transaction error with device %d\n",
1909                        dma_chan[ch].dev_id);
1910                 if (cpu_class_is_omap2()) {
1911                         /* Errata: sDMA Channel is not disabled
1912                          * after a transaction error. So we explicitely
1913                          * disable the channel
1914                          */
1915                         u32 ccr;
1916
1917                         ccr = dma_read(CCR(ch));
1918                         ccr &= ~OMAP_DMA_CCR_EN;
1919                         dma_write(ccr, CCR(ch));
1920                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1921                 }
1922         }
1923         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1924                 printk(KERN_INFO "DMA secure error with device %d\n",
1925                        dma_chan[ch].dev_id);
1926         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1927                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1928                        dma_chan[ch].dev_id);
1929
1930         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1931         dma_write(1 << ch, IRQSTATUS_L0);
1932
1933         /* If the ch is not chained then chain_id will be -1 */
1934         if (dma_chan[ch].chain_id != -1) {
1935                 int chain_id = dma_chan[ch].chain_id;
1936                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1937                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1938                         dma_chan[dma_chan[ch].next_linked_ch].state =
1939                                                         DMA_CH_STARTED;
1940                 if (dma_linked_lch[chain_id].chain_mode ==
1941                                                 OMAP_DMA_DYNAMIC_CHAIN)
1942                         disable_lnk(ch);
1943
1944                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1945                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1946
1947                 status = dma_read(CSR(ch));
1948         }
1949
1950         dma_write(status, CSR(ch));
1951
1952         if (likely(dma_chan[ch].callback != NULL))
1953                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1954
1955         return 0;
1956 }
1957
1958 /* STATUS register count is from 1-32 while our is 0-31 */
1959 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1960 {
1961         u32 val, enable_reg;
1962         int i;
1963
1964         val = dma_read(IRQSTATUS_L0);
1965         if (val == 0) {
1966                 if (printk_ratelimit())
1967                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1968                 return IRQ_HANDLED;
1969         }
1970         enable_reg = dma_read(IRQENABLE_L0);
1971         val &= enable_reg; /* Dispatch only relevant interrupts */
1972         for (i = 0; i < dma_lch_count && val != 0; i++) {
1973                 if (val & 1)
1974                         omap2_dma_handle_ch(i);
1975                 val >>= 1;
1976         }
1977
1978         return IRQ_HANDLED;
1979 }
1980
1981 static struct irqaction omap24xx_dma_irq = {
1982         .name = "DMA",
1983         .handler = omap2_dma_irq_handler,
1984         .flags = IRQF_DISABLED
1985 };
1986
1987 #else
1988 static struct irqaction omap24xx_dma_irq;
1989 #endif
1990
1991 /*----------------------------------------------------------------------------*/
1992
1993 static struct lcd_dma_info {
1994         spinlock_t lock;
1995         int reserved;
1996         void (*callback)(u16 status, void *data);
1997         void *cb_data;
1998
1999         int active;
2000         unsigned long addr, size;
2001         int rotate, data_type, xres, yres;
2002         int vxres;
2003         int mirror;
2004         int xscale, yscale;
2005         int ext_ctrl;
2006         int src_port;
2007         int single_transfer;
2008 } lcd_dma;
2009
2010 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
2011                          int data_type)
2012 {
2013         lcd_dma.addr = addr;
2014         lcd_dma.data_type = data_type;
2015         lcd_dma.xres = fb_xres;
2016         lcd_dma.yres = fb_yres;
2017 }
2018 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2019
2020 void omap_set_lcd_dma_src_port(int port)
2021 {
2022         lcd_dma.src_port = port;
2023 }
2024
2025 void omap_set_lcd_dma_ext_controller(int external)
2026 {
2027         lcd_dma.ext_ctrl = external;
2028 }
2029 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2030
2031 void omap_set_lcd_dma_single_transfer(int single)
2032 {
2033         lcd_dma.single_transfer = single;
2034 }
2035 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2036
2037 void omap_set_lcd_dma_b1_rotation(int rotate)
2038 {
2039         if (omap_dma_in_1510_mode()) {
2040                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2041                 BUG();
2042                 return;
2043         }
2044         lcd_dma.rotate = rotate;
2045 }
2046 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2047
2048 void omap_set_lcd_dma_b1_mirror(int mirror)
2049 {
2050         if (omap_dma_in_1510_mode()) {
2051                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2052                 BUG();
2053         }
2054         lcd_dma.mirror = mirror;
2055 }
2056 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2057
2058 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2059 {
2060         if (omap_dma_in_1510_mode()) {
2061                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2062                                 "in 1510 mode\n");
2063                 BUG();
2064         }
2065         lcd_dma.vxres = vxres;
2066 }
2067 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2068
2069 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2070 {
2071         if (omap_dma_in_1510_mode()) {
2072                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2073                 BUG();
2074         }
2075         lcd_dma.xscale = xscale;
2076         lcd_dma.yscale = yscale;
2077 }
2078 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2079
2080 static void set_b1_regs(void)
2081 {
2082         unsigned long top, bottom;
2083         int es;
2084         u16 w;
2085         unsigned long en, fn;
2086         long ei, fi;
2087         unsigned long vxres;
2088         unsigned int xscale, yscale;
2089
2090         switch (lcd_dma.data_type) {
2091         case OMAP_DMA_DATA_TYPE_S8:
2092                 es = 1;
2093                 break;
2094         case OMAP_DMA_DATA_TYPE_S16:
2095                 es = 2;
2096                 break;
2097         case OMAP_DMA_DATA_TYPE_S32:
2098                 es = 4;
2099                 break;
2100         default:
2101                 BUG();
2102                 return;
2103         }
2104
2105         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2106         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2107         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2108         BUG_ON(vxres < lcd_dma.xres);
2109
2110 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2111                 ((y) * vxres * yscale + (x) * xscale) * es)
2112 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2113
2114         switch (lcd_dma.rotate) {
2115         case 0:
2116                 if (!lcd_dma.mirror) {
2117                         top = PIXADDR(0, 0);
2118                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2119                         /* 1510 DMA requires the bottom address to be 2 more
2120                          * than the actual last memory access location. */
2121                         if (omap_dma_in_1510_mode() &&
2122                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2123                                         bottom += 2;
2124                         ei = PIXSTEP(0, 0, 1, 0);
2125                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2126                 } else {
2127                         top = PIXADDR(lcd_dma.xres - 1, 0);
2128                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2129                         ei = PIXSTEP(1, 0, 0, 0);
2130                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2131                 }
2132                 en = lcd_dma.xres;
2133                 fn = lcd_dma.yres;
2134                 break;
2135         case 90:
2136                 if (!lcd_dma.mirror) {
2137                         top = PIXADDR(0, lcd_dma.yres - 1);
2138                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2139                         ei = PIXSTEP(0, 1, 0, 0);
2140                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2141                 } else {
2142                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2143                         bottom = PIXADDR(0, 0);
2144                         ei = PIXSTEP(0, 1, 0, 0);
2145                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2146                 }
2147                 en = lcd_dma.yres;
2148                 fn = lcd_dma.xres;
2149                 break;
2150         case 180:
2151                 if (!lcd_dma.mirror) {
2152                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2153                         bottom = PIXADDR(0, 0);
2154                         ei = PIXSTEP(1, 0, 0, 0);
2155                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2156                 } else {
2157                         top = PIXADDR(0, lcd_dma.yres - 1);
2158                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2159                         ei = PIXSTEP(0, 0, 1, 0);
2160                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2161                 }
2162                 en = lcd_dma.xres;
2163                 fn = lcd_dma.yres;
2164                 break;
2165         case 270:
2166                 if (!lcd_dma.mirror) {
2167                         top = PIXADDR(lcd_dma.xres - 1, 0);
2168                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2169                         ei = PIXSTEP(0, 0, 0, 1);
2170                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2171                 } else {
2172                         top = PIXADDR(0, 0);
2173                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2174                         ei = PIXSTEP(0, 0, 0, 1);
2175                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2176                 }
2177                 en = lcd_dma.yres;
2178                 fn = lcd_dma.xres;
2179                 break;
2180         default:
2181                 BUG();
2182                 return; /* Suppress warning about uninitialized vars */
2183         }
2184
2185         if (omap_dma_in_1510_mode()) {
2186                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2187                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2188                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2189                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2190
2191                 return;
2192         }
2193
2194         /* 1610 regs */
2195         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2196         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2197         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2198         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2199
2200         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2201         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2202
2203         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2204         w &= ~0x03;
2205         w |= lcd_dma.data_type;
2206         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2207
2208         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2209         /* Always set the source port as SDRAM for now*/
2210         w &= ~(0x03 << 6);
2211         if (lcd_dma.callback != NULL)
2212                 w |= 1 << 1;            /* Block interrupt enable */
2213         else
2214                 w &= ~(1 << 1);
2215         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2216
2217         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2218               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2219                 return;
2220
2221         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2222         /* Set the double-indexed addressing mode */
2223         w |= (0x03 << 12);
2224         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2225
2226         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2227         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2228         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2229 }
2230
2231 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2232 {
2233         u16 w;
2234
2235         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2236         if (unlikely(!(w & (1 << 3)))) {
2237                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2238                 return IRQ_NONE;
2239         }
2240         /* Ack the IRQ */
2241         w |= (1 << 3);
2242         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2243         lcd_dma.active = 0;
2244         if (lcd_dma.callback != NULL)
2245                 lcd_dma.callback(w, lcd_dma.cb_data);
2246
2247         return IRQ_HANDLED;
2248 }
2249
2250 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2251                          void *data)
2252 {
2253         spin_lock_irq(&lcd_dma.lock);
2254         if (lcd_dma.reserved) {
2255                 spin_unlock_irq(&lcd_dma.lock);
2256                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2257                 BUG();
2258                 return -EBUSY;
2259         }
2260         lcd_dma.reserved = 1;
2261         spin_unlock_irq(&lcd_dma.lock);
2262         lcd_dma.callback = callback;
2263         lcd_dma.cb_data = data;
2264         lcd_dma.active = 0;
2265         lcd_dma.single_transfer = 0;
2266         lcd_dma.rotate = 0;
2267         lcd_dma.vxres = 0;
2268         lcd_dma.mirror = 0;
2269         lcd_dma.xscale = 0;
2270         lcd_dma.yscale = 0;
2271         lcd_dma.ext_ctrl = 0;
2272         lcd_dma.src_port = 0;
2273
2274         return 0;
2275 }
2276 EXPORT_SYMBOL(omap_request_lcd_dma);
2277
2278 void omap_free_lcd_dma(void)
2279 {
2280         spin_lock(&lcd_dma.lock);
2281         if (!lcd_dma.reserved) {
2282                 spin_unlock(&lcd_dma.lock);
2283                 printk(KERN_ERR "LCD DMA is not reserved\n");
2284                 BUG();
2285                 return;
2286         }
2287         if (!enable_1510_mode)
2288                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2289                             OMAP1610_DMA_LCD_CCR);
2290         lcd_dma.reserved = 0;
2291         spin_unlock(&lcd_dma.lock);
2292 }
2293 EXPORT_SYMBOL(omap_free_lcd_dma);
2294
2295 void omap_enable_lcd_dma(void)
2296 {
2297         u16 w;
2298
2299         /*
2300          * Set the Enable bit only if an external controller is
2301          * connected. Otherwise the OMAP internal controller will
2302          * start the transfer when it gets enabled.
2303          */
2304         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2305                 return;
2306
2307         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2308         w |= 1 << 8;
2309         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2310
2311         lcd_dma.active = 1;
2312
2313         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2314         w |= 1 << 7;
2315         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2316 }
2317 EXPORT_SYMBOL(omap_enable_lcd_dma);
2318
2319 void omap_setup_lcd_dma(void)
2320 {
2321         BUG_ON(lcd_dma.active);
2322         if (!enable_1510_mode) {
2323                 /* Set some reasonable defaults */
2324                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2325                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2326                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2327         }
2328         set_b1_regs();
2329         if (!enable_1510_mode) {
2330                 u16 w;
2331
2332                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2333                 /*
2334                  * If DMA was already active set the end_prog bit to have
2335                  * the programmed register set loaded into the active
2336                  * register set.
2337                  */
2338                 w |= 1 << 11;           /* End_prog */
2339                 if (!lcd_dma.single_transfer)
2340                         w |= (3 << 8);  /* Auto_init, repeat */
2341                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2342         }
2343 }
2344 EXPORT_SYMBOL(omap_setup_lcd_dma);
2345
2346 void omap_stop_lcd_dma(void)
2347 {
2348         u16 w;
2349
2350         lcd_dma.active = 0;
2351         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2352                 return;
2353
2354         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2355         w &= ~(1 << 7);
2356         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2357
2358         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2359         w &= ~(1 << 8);
2360         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2361 }
2362 EXPORT_SYMBOL(omap_stop_lcd_dma);
2363
2364 void omap_dma_global_context_save(void)
2365 {
2366         omap_dma_global_context.dma_irqenable_l0 =
2367                 dma_read(IRQENABLE_L0);
2368         omap_dma_global_context.dma_ocp_sysconfig =
2369                 dma_read(OCP_SYSCONFIG);
2370         omap_dma_global_context.dma_gcr = dma_read(GCR);
2371 }
2372
2373 void omap_dma_global_context_restore(void)
2374 {
2375         int ch;
2376
2377         dma_write(omap_dma_global_context.dma_gcr, GCR);
2378         dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2379                 OCP_SYSCONFIG);
2380         dma_write(omap_dma_global_context.dma_irqenable_l0,
2381                 IRQENABLE_L0);
2382
2383         /*
2384          * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2385          * after secure sram context save and restore. Hence we need to
2386          * manually clear those IRQs to avoid spurious interrupts. This
2387          * affects only secure devices.
2388          */
2389         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2390                 dma_write(0x3 , IRQSTATUS_L0);
2391
2392         for (ch = 0; ch < dma_chan_count; ch++)
2393                 if (dma_chan[ch].dev_id != -1)
2394                         omap_clear_dma(ch);
2395 }
2396
2397 /*----------------------------------------------------------------------------*/
2398
2399 static int __init omap_init_dma(void)
2400 {
2401         unsigned long base;
2402         int ch, r;
2403
2404         if (cpu_class_is_omap1()) {
2405                 base = OMAP1_DMA_BASE;
2406                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2407         } else if (cpu_is_omap24xx()) {
2408                 base = OMAP24XX_DMA4_BASE;
2409                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2410         } else if (cpu_is_omap34xx()) {
2411                 base = OMAP34XX_DMA4_BASE;
2412                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2413         } else if (cpu_is_omap44xx()) {
2414                 base = OMAP44XX_DMA4_BASE;
2415                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2416         } else {
2417                 pr_err("DMA init failed for unsupported omap\n");
2418                 return -ENODEV;
2419         }
2420
2421         omap_dma_base = ioremap(base, SZ_4K);
2422         BUG_ON(!omap_dma_base);
2423
2424         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2425                         && (omap_dma_reserve_channels <= dma_lch_count))
2426                 dma_lch_count = omap_dma_reserve_channels;
2427
2428         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2429                                 GFP_KERNEL);
2430         if (!dma_chan) {
2431                 r = -ENOMEM;
2432                 goto out_unmap;
2433         }
2434
2435         if (cpu_class_is_omap2()) {
2436                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2437                                                 dma_lch_count, GFP_KERNEL);
2438                 if (!dma_linked_lch) {
2439                         r = -ENOMEM;
2440                         goto out_free;
2441                 }
2442         }
2443
2444         if (cpu_is_omap15xx()) {
2445                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2446                 dma_chan_count = 9;
2447                 enable_1510_mode = 1;
2448         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2449                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2450                        dma_read(HW_ID));
2451                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2452                        (dma_read(CAPS_0_U) << 16) |
2453                        dma_read(CAPS_0_L),
2454                        (dma_read(CAPS_1_U) << 16) |
2455                        dma_read(CAPS_1_L),
2456                        dma_read(CAPS_2), dma_read(CAPS_3),
2457                        dma_read(CAPS_4));
2458                 if (!enable_1510_mode) {
2459                         u16 w;
2460
2461                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2462                         w = dma_read(GSCR);
2463                         w |= 1 << 3;
2464                         dma_write(w, GSCR);
2465                         dma_chan_count = 16;
2466                 } else
2467                         dma_chan_count = 9;
2468                 if (cpu_is_omap16xx()) {
2469                         u16 w;
2470
2471                         /* this would prevent OMAP sleep */
2472                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2473                         w &= ~(1 << 8);
2474                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2475                 }
2476         } else if (cpu_class_is_omap2()) {
2477                 u8 revision = dma_read(REVISION) & 0xff;
2478                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2479                        revision >> 4, revision & 0xf);
2480                 dma_chan_count = dma_lch_count;
2481         } else {
2482                 dma_chan_count = 0;
2483                 return 0;
2484         }
2485
2486         spin_lock_init(&lcd_dma.lock);
2487         spin_lock_init(&dma_chan_lock);
2488
2489         for (ch = 0; ch < dma_chan_count; ch++) {
2490                 omap_clear_dma(ch);
2491                 dma_chan[ch].dev_id = -1;
2492                 dma_chan[ch].next_lch = -1;
2493
2494                 if (ch >= 6 && enable_1510_mode)
2495                         continue;
2496
2497                 if (cpu_class_is_omap1()) {
2498                         /*
2499                          * request_irq() doesn't like dev_id (ie. ch) being
2500                          * zero, so we have to kludge around this.
2501                          */
2502                         r = request_irq(omap1_dma_irq[ch],
2503                                         omap1_dma_irq_handler, 0, "DMA",
2504                                         (void *) (ch + 1));
2505                         if (r != 0) {
2506                                 int i;
2507
2508                                 printk(KERN_ERR "unable to request IRQ %d "
2509                                        "for DMA (error %d)\n",
2510                                        omap1_dma_irq[ch], r);
2511                                 for (i = 0; i < ch; i++)
2512                                         free_irq(omap1_dma_irq[i],
2513                                                  (void *) (i + 1));
2514                                 goto out_free;
2515                         }
2516                 }
2517         }
2518
2519         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2520                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2521                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2522
2523         if (cpu_class_is_omap2()) {
2524                 int irq;
2525                 if (cpu_is_omap44xx())
2526                         irq = INT_44XX_SDMA_IRQ0;
2527                 else
2528                         irq = INT_24XX_SDMA_IRQ0;
2529                 setup_irq(irq, &omap24xx_dma_irq);
2530         }
2531
2532         if (cpu_is_omap34xx()) {
2533                 /* Enable smartidle idlemodes and autoidle */
2534                 u32 v = dma_read(OCP_SYSCONFIG);
2535                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2536                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2537                                 DMA_SYSCONFIG_AUTOIDLE);
2538                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2539                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2540                         DMA_SYSCONFIG_AUTOIDLE);
2541                 dma_write(v , OCP_SYSCONFIG);
2542                 /* reserve dma channels 0 and 1 in high security devices */
2543                 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
2544                         printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2545                                         "HS ROM code\n");
2546                         dma_chan[0].dev_id = 0;
2547                         dma_chan[1].dev_id = 1;
2548                 }
2549         }
2550
2551
2552         /* FIXME: Update LCD DMA to work on 24xx */
2553         if (cpu_class_is_omap1()) {
2554                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2555                                 "LCD DMA", NULL);
2556                 if (r != 0) {
2557                         int i;
2558
2559                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2560                                "(error %d)\n", r);
2561                         for (i = 0; i < dma_chan_count; i++)
2562                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2563                         goto out_free;
2564                 }
2565         }
2566
2567         return 0;
2568
2569 out_free:
2570         kfree(dma_chan);
2571
2572 out_unmap:
2573         iounmap(omap_dma_base);
2574
2575         return r;
2576 }
2577
2578 arch_initcall(omap_init_dma);
2579
2580 /*
2581  * Reserve the omap SDMA channels using cmdline bootarg
2582  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2583  */
2584 static int __init omap_dma_cmdline_reserve_ch(char *str)
2585 {
2586         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2587                 omap_dma_reserve_channels = 0;
2588         return 1;
2589 }
2590
2591 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2592
2593